JPH04182835A - Bus monitor device for multiprocessor system - Google Patents

Abstract

PURPOSE:To handle abnormality occurrence immediately and to minimize and suppress damage by latching the signal state on a bus at the point of time of the abnormality occurrence and specifying the processor where the abnormality occurs and the kind of the abnormality by other processors according to the signal state. CONSTITUTION:While each processor accesses other processors normally, this bus monitor device updates the signal state of the bus 4 latched in a common bus latch circuit 7 every time access is started. If abnormality occurs on the bus 4, the signal state in the abnormality occurrence which is latched in the circuit 7 is not updated. Therefore, each processor 5 which receives error occurrence information from the bus monitor device 6 reads the signal state in abnormality occurrence which is latched in the circuit 7 to judge the processor where the abnormality occurs and the kind of the abnormality. Therefore, a countermeasure corresponding to the abnormality occurrence is speedily taken and the damage of the system in case of the abnormality occurrence suppressed to a minimum.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multiprocessor system in which a plurality of processors are connected to one bus, and particularly relates to a multiprocessor system in which a plurality of processors are connected to one bus. The present invention relates to a bus monitoring device for a multiprocessor system that monitors bus occurrences.

(Prior Art) As shown in FIG. 3, for example, a multiprocessor system includes one or more CPUs ( A plurality of processors 2 each having a built-in central processing unit (central processing unit) are connected to each other.

In such a multiprocessor system, when one processor communicates with another processor, it secures the right to use bus 1 and then accesses the other processor via bus 1. Therefore, all data including various control information exchanged between the processors 2 is sent onto the bus 1.

In such a multiprocessor system, if some kind of abnormality occurs in one processor 2, in addition to the other processors accessing the processor in which this abnormality has occurred, the other processors will not be able to access the processor in which the abnormality has occurred. could not be detected. Therefore, a problem arises in which detection of the occurrence of an abnormality is delayed.

Furthermore, if the abnormality that occurs is serious, other processors that access the processor in which this abnormality has occurred will also acquire abnormal data from the processor in which the abnormality has occurred, so the abnormality may adversely affect other processors and There is a concern that even normal processors may become abnormal. Therefore, there is a concern that the system's overall operations will be seriously affected.

(Problems to be Solved by the Invention) As described above, in conventional multiprocessor systems, the abnormality can only be confirmed by accessing the processor in which the abnormality has occurred. That is, since only the accessed processor can grasp that an abnormality has occurred in the relevant processor, information processing continues in a state in which each processor is unaware of the occurrence of an abnormality. Therefore, in some cases, there is a problem in which information processing is performed even though it is known to be wasteful. There is also concern that the detection of serious abnormalities may be delayed.

The present invention has been made in view of the above circumstances, and by latching the signal state on the bus at the time of occurrence of an abnormality, other processors can easily know that an abnormality has occurred, and can prevent the occurrence of an abnormality. It is an object of the present invention to provide a bus monitoring device for a multiprocessor system that can immediately deal with abnormalities and minimize damage caused by the occurrence of abnormalities.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention connects a plurality of processors to one bus, and each processor has access to other processors via the bus. In a bus monitoring device for a multiprocessor system that monitors the occurrence of abnormalities in a multiprocessor system, each time a latch signal is manually input, a common bus latch circuit that latches the signal state on the bus at that time and a bus of each processor are connected. Each time we detect the start of an access to
An access start detection circuit that sends a latch signal to the common bus latch circuit, an error detection circuit that detects errors in the access operation of each processor and outputs an error detection signal, and responds to the error detection signal of this error detection circuit, and a latch prohibition circuit that prohibits input of the latch signal to the common bus latch circuit.

(Function) According to the bus monitoring device of the multiprocessor system configured as described above, during the period when the multiprocessor system is operating normally, access from one processor to another bromo source via the bus is prevented. Once initiated, a latch signal is applied to the common bus latch circuit. As a result, the signal state on the bus at that time is latched into the common bus latch circuit. Therefore, each time an access occurs, the signal state on the bus latched by the common bus latch circuit is updated to the latest signal state.

If any error occurs during the access process, the latch prohibition circuit is activated by the error detection signal.
Latch signal is cut off. Therefore, in the common bus latch circuit, the signal state on the bus at the time the error occurs remains latched and is not updated. Therefore, since the error signal state is recorded in this common bus latch circuit, other processors can grasp error information by accessing this common bus latch circuit.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a schematic diagram showing a multiprocessor system incorporating the bus monitoring device of the embodiment. One or more CPUs that execute various information processing on one bus 4 consisting of an address bus, a data bus, a control bus, etc.
N processors 5 incorporating (central processing unit K) and one bus monitoring device 6 are connected.

In such a multiprocessor system, when one processor 5 communicates with another processor 5, the right to use the bus 4 is secured 17, and then the other processor 5 is accessed via this bus 4. . Therefore, all the data of the processors 5 is sent out on the bus 4.

The bus monitoring device 6 is configured as shown in FIG. 1, for example.

That is, the common bus latch circuit 7 is directly connected to the bus 4. In this common bus latch circuit 7, the signal level of the latch terminal LE changes from high (H) level to low (L) level.
) The signal state on the bus 4 is captured and latched at the timing when the level changes.

Therefore, the latch signal a at L level is sent to the latch terminal LE.
Each time the signal is applied, the signal state latched in the common bus latch circuit 7 is updated to the latest signal state. Also,
Since this common bus latch circuit 7 is directly connected to the bus 4, each processor 5 can freely read the signal state latched in this common bus latch circuit 7.

Further, an access start detection circuit 8, an error detection circuit 9, and a control section 10 are connected to the bus 4 via an input/output port 11.

The access start detection circuit 8 monitors the signal state of one or more predetermined specific signal lines in the control bus constituting the bus 4, and detects the start of access from one processor 5 to another processor 5. Detect signal changes indicated. When the access start is detected, the latch terminal L of the common bus latch circuit 7 is connected via the latch inhibit circuit 12.
The L level latch signal a is sent to E. in particular,
An L-level latch signal output from the access start detection circuit 8 that detects the access start is sent to the access prohibition circuit 12.
The level of the signal is inverted by the inverter 12a inside the signal, and the signal is input to one input terminal of the Nandt gate 12b. The error detection signal S from the error detection circuit 9 is input to the other input terminal of the Nant gate 12b, or when no error is detected, this error detection signal S is high (H).
level. Therefore, the Nant gate 12b is established, and the L level latch signal a is applied from the Nant gate 12b to the common bus buffer circuit 7. Therefore,
The common path buffer circuit 7 takes in and latches the signal state of the bus 4 at that time. That is, latch signal a
will pass through the latch inhibit circuit 12 as is.

The error detection circuit 9 monitors the signal states of the address bus, data bus, and control bus of the bus 4 to determine whether any abnormality has occurred in the process of one processor 5 accessing another processor 5. to monitor. When an abnormality is detected, the L-level error detection signal is output to the Nant gate 12b of the latch prohibition circuit 12 and the control unit 1.
Send to 0. For example, a method for determining that an abnormality has occurred is as follows. If the access time is abnormally long, it is determined as an error. Furthermore, it is determined that an error occurs if the data corresponding to the successive signal is not output to the bus.

When the error detection circuit 9 outputs the error detection signal S at the L level, the Nant gate 12b is not established, and the latch signal a at the L level is applied from the Nant gate 12b to the latch terminal LE of the common bus latch circuit 7. There isn't. When the error detection signal S is output, the signal state of the bus 4 latched by the common bus latch circuit 7 will not be updated even if the next access is started.

When the control unit 10 receives the error detection signal S at the L level, it transmits error occurrence information to each processor 5 via the input/output port 11 and the bus 4.

When each processor 5 receives the error occurrence information from the bus monitoring device 6, it reads the signal state latched by the common bus latch circuit 7 at the time of occurrence of an abnormality on the bus 4. and,
Based on the read signal state, the processor 5 in which the abnormality has occurred is specified, and the type of abnormality is specified.

In the bus monitoring device of the multiprocessor system configured as described above, when each processor is normally accessing other processors, each time an access is started, the bus latched in the common bus latch circuit 7 is The signal status of No. 4 is updated to the latest status. If any access abnormality occurs on the bus 4, the signal state latched in the common bus latch circuit 7 at the time of the abnormality occurrence is not updated. Therefore, each processor 5 that receives the error occurrence information from the bus monitoring device 6 reads the signal state latched in the common bus latch circuit 7 at the time of the occurrence of the error, thereby determining the processor and type of the error. can.

Therefore, it is possible to quickly take measures to deal with the occurrence of the abnormality. Therefore, damage to the system when an abnormality occurs can be minimized.

Therefore, unlike the conventional system shown in FIG. 3, it is possible to prevent a processor from continuing normal processing without noticing the occurrence of an abnormality even though it occurs in another processor. Therefore, the safety of the entire multiprocessor system can be improved.

[Effects of the Invention] As explained above, according to the bus monitoring device for a multiprocessor system of the present invention, the signal state on the bus at the time of occurrence of an abnormality is latched. Therefore, each of the other processors can identify the processor in which the abnormality has occurred and the type of abnormality based on the latched signal state. Therefore, the occurrence of an abnormality can be dealt with immediately, and damage caused by the occurrence of an abnormality can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a bus monitoring device of a multiprocessor system according to an embodiment, FIG. 2 is a schematic diagram showing the entire multiprocessor system in which the device of the embodiment is incorporated, and FIG.
The figure is a schematic diagram showing a conventional multiprocessor system. 4... Bus, 5... Processor, 6... Bus monitoring device, 7... Common bus latch circuit, 8... Access start detection circuit, 9... Error detection circuit, 10... Control Section 11... Input/output board, 12... Latch inhibition circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 '

Claims (1)

[Scope of Claims] A bus monitoring device for a multiprocessor system that monitors the occurrence of an abnormality in a multiprocessor system in which a plurality of processors are connected to one bus and each processor accesses other processors via the bus. A common bus latch circuit that latches the signal state on the bus at that time every time a latch signal is input, and a common bus latch circuit that latches the signal state on the bus at that time every time a start of access via the bus of each processor is detected. an access start detection circuit that sends out a signal; an error detection circuit that detects an error in the access operation of each of the processors and outputs an error detection signal; A bus monitoring device for a multiprocessor system, comprising a latch prohibition circuit that prohibits input to the common bus latch circuit.