JPS62278642A - Retrial control system - Google Patents

Abstract

PURPOSE:To improve the retrial success factor when intermittent errors occur by setting the retrial start waiting time and the retrial frequency suited to the system environment. CONSTITUTION:The retrial start waiting time can be optionally set to a retrial start waiting time memory means 9 in a system rise mode. While the optional value can be set to a maximum allowable retrial frequency memory means 12 to decide the maximum retrial frequency. Then a retrial property display means 8 displays whether the retrial is possible or not when error detecting means 1 and 2 detect the errors within a system. If the retrial is possible, a retrial executing means carries out the retrial after waiting for a time designated by the means 9. When such retrial is not successful, the retrial is repeated within a range of the maximum allowable retrial frequency stored in a maximum allowable retrial frequency memory means 12.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a retry control method in an information processing device (prior art) Conventionally, this type of retry control method has been A detection means for detecting an error occurring in the system, a retryability determination bit indicating whether or not a retry can be performed depending on the state of the system at the time of error detection, and a means for executing a retry. When an error occurs in the system, the content of the above-mentioned retry permission determination bit is determined, and if a retry is possible, the retry is immediately performed.

[Problem that the invention seeks to solve]

By the way, errors that occur within the system, especially intermittent errors, can be caused by various things such as static electricity mischief, radio wave noise, and poor contact at the cable connector.
The time during which these causes act usually varies depending on the environment of the system. Therefore, in the conventional retry control method described above, in which retry is performed immediately without waiting time after determining whether or not a retry is possible and the contents of step 7) are determined, depending on the system environment, The present invention solves these conventional drawbacks, and its purpose is to improve the retry success rate when intermittent errors occur. The objective is to provide a control method.

[Means for solving problems]

In order to achieve the above object, the present invention provides a maximum allowable number of retry storage means that can set the maximum allowable number of retries at system start-up, and a retry start waiting time that can set a retry start waiting time at system start-up. A time storage means, an error detection means for detecting an error occurring in the system, a retry possibility display means for displaying whether or not a retry is possible according to the error detected by the error detection means, and the retry possibility display. a retry execution means that executes a retry after waiting for a time specified by the retry start waiting time storage means when the retry is indicated as possible by the means; and when the retry fails, the maximum allowable retry and means for repeating retries within the range of the maximum allowable number of retries stored in the number of retries storage means. This repeating means includes, for example, a retry number storage means that is updated and stored each time a retry is executed, and when a retry fails, the contents of the retry number storage means are compared with the contents of the maximum allowable retry number storage means. do the
If it is still within the permissible range, the method repeats the retry.

[Effect]

In the retry startup waiting time storage means, a retry startup waiting time can be arbitrarily set at the time of system startup, and in the maximum allowable number of retries storage means, the maximum number of retries can be performed. If an error in the system is detected by the error detection means, the retry possibility display means will display whether or not retry is possible, and if retry is possible, The retry execution means executes the retry after waiting for a time specified by the retry activation waiting time storage means. If this retry is not successful, the retry is repeated within the maximum allowable number of retries stored in the maximum allowable number of retries storage means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a plurality of error detection circuits (hereinafter referred to as CHK) 1゜2 for detecting errors in each hardware (not shown), and this CHKI.
, a plurality of error indicators (hereinafter referred to as ErF) for storing that there is an error in accordance with the error detection of 2.
3, 4, and an OR circuit 5 that takes the logical sum of the output signal of EIF3.4, and the output of this OR circuit 5 and C) (Kl, CHK
A NOR circuit 6 that takes a NOR condition with the output of 2, an AND circuit 7 that takes a logical product of this request and the output of the above-mentioned NOR circuit 6 when a program visible register write request occurs, and starts execution of each instruction. sent by the signal, AND circuit 7
A retry possibility display circuit (hereinafter referred to as RTB) 8 which is reset by the output of , that is, a register write signal for actually writing to the program visible register, and an arbitrary retry start waiting time are set at the time of system startup. a retry activation waiting time storage circuit (this is configured with, for example, non-volatile memory, hereinafter referred to as DLY) 9 and a counter (hereinafter referred to as CNTR) 10 to which the output of DLY9 is set before retry activation. and C for each countdown request.
A subtracter 16 that counts down the NTR100 value, and C
If the output of NTRl0 and the value "0" are manually input, CNTRl0
Comparison circuit 11 for detecting whether the value of becomes 0 or not
and a maximum allowable retry count storage circuit (hereinafter referred to as MAXRCT) 12 that can store any value at system startup.
MAXRCT when performing fault processing due to error occurrence.
Counter 13 (hereinafter referred to as RTYR) to which the contents of 12 are set
CT13) and RTYR for each countdown request.
A subtracter 15 that counts down the value of CT13, and RT
RTYRC inputs the output of YRCT13 and the value "0"
The comparison circuit 14 for detecting whether the value of T13 becomes 0 or not, the output of the OR circuit 5, the output of RTB8, and the output of the comparison circuit 11.14 are each manually operated, and the contents of DLY9 are sent to CNTRl0. Control, MAXRCT12
Control to send the contents of to RTYRCT13, subtractor 1
The fault processing mechanism 17 performs operations such as sending a countdown request to 5.16 and determining the output of the comparator 11.14, and performs fault processing to be described later.

FIG. 2 is a flowchart of a processing example of the failure handling mechanism 17, and the operation of this embodiment will be explained below with reference to each figure.

When a certain hardware error is detected in CHKI, CHK2, the corresponding EIF3. The content of EIF4 becomes "1", the output of OR circuit 5 becomes "1", and fault handling mechanism 17 is activated.

When the failure processing mechanism 17 is activated, it stops the clock and temporarily logs out to a working storage section (not shown) in order to retrieve the internal state of the hardware to an external storage device (not shown) (process 100).

Next, the failure handling mechanism 17 resets the hardware to an error prior to retry activation (process 101).

As a result, the stopped clock is restarted, and initial settings are made except for program-visible information, system control information, and the like.

Next, the failure processing mechanism 17 determines the contents of the RTB 8 (
Process 102). RTB8 receives the execution start signal of each instruction.
1”, CHKl, CHK2゜EIF3.E
None of IF4 is “1” and is reset to “0°” when the contents of the program visible register are updated. Therefore, RTB8-“0”, that is, when retry is not possible, is the value when retry is not possible. Failure handling, for example, in a multiprocessor configuration, perform processing such as disconnecting the affected processor, aborting the job, and continuing processing (Processing 1)
03).

On the other hand, when RTB8-"1", retry is possible, and retry activation waiting processing is performed. That is, the process 104) transfers the contents of DLY9 to CNTR10, the process 105) subtracts the value of CNTR10 by issuing a countdown request a to the subtractor 16 every microsecond, for example,
Process 106) to determine whether the value of TRl0 has become O based on the output of the comparison circuit 11, and if the value is 0, it is assumed that a predetermined retry activation waiting time has elapsed and a retry is activated. If the value is not yet 0, ma the waiting time. In addition, in the routine to start a retry, first, the content set in MAXRCT12 is added to RTYRCT13 by adding signal C to RTYR.
CT13 returns to normal processing 107), and then retry is started (processing 10B).

Next, a process 109) is performed to determine whether the retry result is successful or not, and if it is successful, the process is continued 110).
If unsuccessful, a countdown request is sent to the subtractor 15 to count down the value of RTYRCT13 by 1 (processing 111), and the value of RTYRCT13 is set to 0.
It is determined whether it has become (process 112). And R
If TYRCT13≠0, perform error reset (processing 114) and judge the output of RTB 8 again.processing 11
5) If it is RTB-0, perform the above-mentioned process when retry is not possible, and if RTB-1, repeat the retry again.On the other hand, if it is determined that RTYRCT13=O in process 112,
In other words, if the retry is unsuccessful even after the allowable number of retries, it is determined to be a fixed failure, and the failure processing is performed when the retry is unsuccessful. For example, in a multiprocessor configuration, the Nvi processor is disconnected and a normal processor is installed. Processing such as retrying is performed (processing 113).

In addition, in FIG. 1, EIF3. E [output of OR circuit 5 that ORs the output of F4, and CH, Kl.

The reason why the program visible register write request is gated in the AND circuit 7 by the output of the NOR circuit 6 which takes the NOR condition signal with each output of CHK2 is to improve the retry possibility rate.

〔Effect of the invention〕

As explained above, the present invention provides a maximum allowable retry count storage means that can set the maximum allowable retry count at system start-up, and a retry start waiting time that can also set a retry start waiting time at system start-up. a time storage means, an error detection means for detecting an error occurring in the system, a retry possibility display means for displaying whether or not a retry is possible according to the error detected by the error detection means, and this retry possibility display. If the means indicates that retry is possible, a retry execution means executes a retry after waiting for the time specified by the retry start waiting time storage means, and when the retry fails, the maximum allowable retry is performed. Since a means for repeating retries within the range of the maximum allowable number of retries stored in the number of retries storage means is provided, it is possible to set the retry startup waiting time and number of retries suitable for the system environment. This has the effect of improving the retry success rate when intermittent errors occur.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a flowchart of an example of processing by the fault handling mechanism 17. In the figure, 1.2...Error detection circuit (CHK), 3
．． 4...Error indicator (EIF), 5...
OR circuit, 6...NOR circuit, 7...AND circuit, 8
... Retry possibility display circuit (RTB), 9... Retry activation waiting time memory circuit (DLY), 10... Counter (CNTR), 11.14... Comparison circuit, 1
2... Maximum allowable retry count storage circuit (MAXRCT)
, 13... Counter (RTYRCT), 15.1
6... Subtractor, 17... Failure handling mechanism.

Claims (1)

[Scope of Claims] Maximum allowable retry count storage means capable of setting a maximum allowable retry count at system start-up; retry start waiting time storage means capable of setting a retry start waiting time at system start-up; an error detection means for detecting an error occurring in the system; a retry possibility display means for displaying whether a retry is possible according to the error detected by the error detection means; and a retry possibility display means for indicating whether a retry is possible. is displayed, retry execution means executes a retry after waiting for the time specified in the retry start waiting time storage means; and when the retry fails, the maximum allowable number of retries storage means and means for repeating retries within a stored maximum allowable number of retries.