JP3045888B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a main processor,
The present invention relates to a data processing device having a main storage unit and an input / output unit, and more particularly to a data processing device having a function of preventing runaway of a main processor when an abnormality occurs.

[0002]

2. Description of the Related Art In a data processing device, when an exception process occurs while a main processor is executing a regular operation such as data access, the internal state of the main processor is saved to an external storage device. And then execute exception processing. Then, after the end of the exception processing, the saved internal state is read out, and the regular operation by the main processor is started again. FIG. 3 is a schematic configuration diagram of the data processing device, and FIG. 4 is a schematic operation flowchart in the example of FIG. 3 and 4, an MPU (main processor) 4 uses an address signal 1 on an address bus, a data signal 2 on a data bus, and a control signal 3 on a control bus, and an I / O (input / output unit) 6 And the operation of the main storage unit 5.

[0003] In step 100 of FIG.
Performs a steady operation, and determines in step 110 whether exception processing such as a bus error has occurred. If no exception processing has occurred, the process returns to step 100 to execute a regular operation. If an exception process occurs in step 110, the process proceeds to step 150, and it is determined whether or not an exception process has occurred. If no exception processing has occurred, the process proceeds to step 120.

In step 120, the MPU 4 sends the MP
Various register information in U4 is saved in the main storage unit 5. Then, in step 130, an exception process is executed,
Upon completion of the processing, the process proceeds to a step 140, and a step 1
The information saved at 20 is returned to the register of the MPU 4 and the process returns to step 100.

If an exception process occurs in step 150, the MPU 4 cannot save the various register information in the main storage unit 5 properly, and may run away. In order to avoid this runaway, if an exception process occurs in step 150, the process proceeds to step 170, and the operation of the MPU 4 is stopped. Next, the routine proceeds to step 180, where the reset signal 8 is sent to the MPU 4.
It is determined whether or not is input. If the reset signal 8 has not been input, the apparatus enters a standby state until the reset signal 8 is input. When the reset signal 8 is input, the apparatus returns to the start state, that is, the initial state.

In the example shown in FIGS. 3 and 4, when exception processing occurs (step 110) and when exception processing occurs (step 150), the operation of the MPU 4 is stopped as described above. You. Then, various register information of the MPU 4 is cleared by the reset signal 8. Therefore, the cause of the exception processing becomes unknown, and the interrupted data processing must be restarted from the beginning. On the other hand, there is a data processing device that latches an address signal and a data signal when an exception process occurs again while the internal state of the MPU is being saved in the storage unit when the exception process occurs. With this data processing device,
Even if the MPU is reset by the reset signal, the cause of the exception processing can be known from the latched address signal and data signal after the normal operation returns.

FIG. 5 is a schematic configuration diagram of a data processing device having the above-described latch function. A latch section for address signals and data signals is added to the example of FIG. FIG. 6 is a schematic operation flowchart of the example of FIG.
5 and 6, an MPU 4 uses an address signal 1, a data signal 2, and a control signal 3 to control an I / O unit 6 and a main storage unit 5, and a latch unit 7 includes an address bus, a data bus, and a control bus. It is connected to the. If an exception process (step 110) such as a bus error occurs during the normal operation of the MPU 4 (step 100), the MPU 4 attempts to save various register information inside the MPU 4 to the main memory (step 120). When exception processing occurs (step 150), the process proceeds to step 160. Then, in this step 160, the latch unit 7 holds the address signal 1 and the data signal 2 at that time. Next, step 1
Proceeding to 70, MPU 4 stops to avoid runaway.
Then, in step 180, the reset signal 8 becomes M
It waits until it is input to PU4. When the reset signal 8 is input to the MPU 4, various register information of the MPU 4 is cleared, but the information held in the latch unit 7 causes the address signal 1 and the data signal 1 when an exception process (step 150) occurs. You can know the contents of 2.

[0008] Examples of a device similar to the data processing device described above include a method for detecting an abnormality in an input / output device described in Japanese Patent Application Laid-Open No. 60-3732 and Japanese Patent Application Laid-Open No.
Further, a data processing device described in JP-A-19448
There is a recording / reproducing apparatus, an information processing apparatus, and the like described in JP-A-4-195617.

[0009]

In the example shown in FIGS. 5 and 6, when exception processing occurs (step 110),
Further, when an exception process such as a bus error occurs (step 150), the latch unit 7 functions to hold information on the address signal 1 and the data signal 2 at the time when the exception process occurs (step 160). Thereby, when the MPU 4 returns to the normal operation, it is possible to search for the information of the address signal 1 and the data signal 2 at the time of occurrence of the exception processing.

However, in the data processing device of FIG. 5 as well, it is difficult to determine the cause of the exception occurrence in which the exception processing in step 100 and the exception processing in step 150 are associated with each other. Data recovery was difficult. Therefore, M
Automatic return from the stop state or runaway state of PU4 was impossible. SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing device that can easily determine the cause of occurrence of exception processing in a data processing device and that can automatically return from a stopped state or a runaway state of an MPU.

[0011]

SUMMARY OF THE INVENTION The present invention is configured as follows to achieve the above object. In the data processing device, a main storage unit that stores instructions and data, a main processor that performs data processing using the instructions and data stored in the main storage unit, and an input / output unit that operates according to instructions from the main processor. A sub-storage unit for storing an address signal indicating a data address, a data signal, a control signal for controlling the transfer of the address signal and the data signal, an address bus for transmitting the address signal, and a data bus for transmitting the data signal. It is connected to a control bus that transmits signals, monitors the access state of the address bus, data bus, and control bus by the main processor, main storage unit, and input / output unit, interrupts, exception processing, or main storage units other than the main processor or When the occurrence of direct memory access by the input / output unit is detected,
The states of the address signal, the data signal, and the control signal are stored in a time-series manner in the sub-storage unit, and further, interrupt and exception processing is performed.
Main memory or input / output unit other than the main processor
When direct memory access is detected due to
Contains at least the internal register information of the main processor.
Are collected and stored in the secondary storage unit, and stored in the secondary storage unit.
Address and data signals and control signals
Main based on in-processor internal register information
Determines whether the processor can be automatically restored, and returns automatically
When possible , a reset signal for supplying a reset signal to at least the main processor on the basis of an exception process occurrence monitoring unit that outputs a reset signal for reset, and an external reset signal supplied from the outside. And a signal selection / synthesis unit.

Preferably, in the above data processing device, the sub-storage section is a storage means capable of circulating a storage area. Preferably, in the data processing device, the sub-storage unit has a backup power supply capable of retaining the stored information even when a power failure occurs.

Preferably, in the data processing device, the reset signal selection / synthesis unit supplies a reset signal to the main processor only when both the reset signal for recovery and the external reset signal are supplied. Preferably, in the data processing device, the exception processing occurrence monitoring unit includes an address signal stored in the secondary storage unit,
The main processor has a determination unit that determines whether or not the normal recovery can be performed based on the state of the data signal and the control signal. When the normal recovery can be performed, the main processor executes data correction and automatically indicates that the normal recovery is possible. A resettable signal is supplied to the reset signal selection / synthesis unit, and the reset signal selection / synthesis unit supplies the reset signal to the main processor when the automatic resettable signal is supplied, regardless of whether an external reset signal is supplied or not. I do.

[0014]

The main processor processes data using instructions and data in the main memory. The main storage unit stores instructions and data necessary for data processing performed by the main processor. The input / output unit is an application circuit according to the needs of the system in accordance with data processing performed by the main processor, and includes an auxiliary storage unit such as a floppy disk and a hard disk, an auxiliary calculation unit, and an image display unit. The address bus transmits a target address signal for a master having the right to use the bus to process data. The data bus transmits information for the master having the right to use the bus to process data. The control bus transmits control signals such as strobes for smoothly transmitting address signals and data signals between the devices. The exception processing occurrence monitoring unit uses the address bus, data bus, and control bus to monitor the state of access by the main processor and the state of bus access by a bus master other than the main processor.

When exception processing occurs or direct memory access occurs by a bus master other than the main processor, the state of the address signal, data signal, and control signal at that time is stored in the secondary storage unit in time series. When the main processor stops abnormally, it analyzes the information in the sub storage unit, the information in the main storage unit, the internal register of the main processor, and the like, and if the main processor can return to normal, generates a reset signal for return.

The sub-storage section stores information sent from the exception processing occurrence monitoring section. The reset signal selection / synthesis unit generates a signal for resetting the main processor based on an externally input reset signal and a reset signal generated by the exception process monitoring unit.

[0017]

FIG. 1 is a schematic block diagram of a data processing apparatus according to an embodiment of the present invention. In FIG. 1, an MPU (main processor) 4 uses an address signal 1 on an address bus, a data signal 2 on a data bus, and a control signal 3 on a control bus to control a main storage unit 5 and an I / O (input / output). The operation of the output unit 6 is controlled. The main storage unit 5 mainly stores the MP
The U4 stores instructions and data necessary for data processing executed by the U4, but also supports direct memory access by a component serving as a bus master such as the I / O 6 and the sequencer unit (exception process occurrence monitoring unit) 12. The address bus 1B, the data bus 2B, and the control bus 3B are connected to the MPU 4,
It is connected to the main storage unit 5, the I / O 6, and the sequencer unit 12.

Address bus 1B transmits a target address for the master unit having the right to use the bus to process data. The data bus 2B transmits information for the master unit having the right to use the bus to perform data processing. The control bus 3B transmits a signal such as a strobe for smoothly transmitting the address signal 2 and the data signal 3 between the respective units, an interrupt signal, a status signal of the MPU 4, and the like.

The sequencer section 12 receives the address signal 1
, Using the data signal 2 and the control signal 3 to monitor the state of the access by the MPU 4 and the bus access by the bus master unit other than the MPU 4 to detect the occurrence of exception processing, the occurrence of the direct memory access by the bus master unit other than the MPU 4, and the like. The states of the address signal 1, the data signal 2, and the control signal 3 when those states occur are stored in the dedicated storage unit (sub-storage unit) 13 of the sequencer unit 12 in time series.

Next, the operation of the example of FIG. 1 will be described. In step 100 of FIG. 2, the MPU 4 executes a steady operation. Then, in step 110, it is determined whether or not exception processing has occurred. If no exception processing has occurred, the process returns to step 100 to execute a regular operation. When an exception process such as a bus error occurs in step 110, the process proceeds to step 190, where the sequencer unit 12 collects information of the address signal 1, the data signal 2, and the control signal 3, and stores the information in the storage unit 13 in time series. I do. Then, the process proceeds to step 150, and it is determined whether or not an exception process has occurred. If the exception process has not occurred, the process proceeds to step 120.

In step 120, information such as the internal register of the MPU 4 is stored in the main storage unit 5. Next, in step 130, the MPU 4 executes the exception processing that has occurred. Then, in step 140, the information stored in the main storage unit 5 is restored, and the process returns to step 100. In step 100, the steady operation is performed again.

If an exception process occurs in step 150, the process proceeds to step 200, where the sequencer unit 1
2 collects the information of the address signal 1, the data signal 2, and the control signal 3 at that time, and stores the information in the storage unit 13 in time series. Then, the process proceeds to step 170, where the operation of the MPU 4 is stopped. Next, in step 210, the sequencer unit 12 collects information such as internal registers of the MPU 4 and stores the information in the dedicated storage unit 13. Further, the sequencer unit 12 in step 220
It is determined whether or not the MPU 4 can automatically return from the information of the internal register 4 and the information of the address signal 1, the data signal 2, and the control signal 3 if the automatic return is possible. move on. In step 230,
The sequencer unit 12 executes the correction if the data in the main storage unit 5 and the like is corrected, and supplies the reset signal 10 for restoration to the reset block (reset signal selection / synthesis unit) 11 in step 240. Then, the reset block 11
Supplies the MPU reset signal 9 to the MPU 4. Then, the normal operation (Step 100) by the MPU 4 is restarted.

If it is determined in step 220 that automatic recovery is not possible, a signal indicating that automatic recovery is not possible is supplied from the sequencer unit 12 to the reset block 11, and the process proceeds to step 180. In step 180, the reset block 11 determines whether the external reset signal 8 has been supplied to the reset block 11. When the external reset signal 8 is supplied, the reset block 11
Supplies the MPU reset signal 9 to the MPU 4. Then, the normal operation (Step 100) by the MPU 4 is restarted.

The sequencer unit 12 and the dedicated storage unit 13
Even if the external reset signal 8 is supplied to the reset block 11, the external reset signal 8 is not affected, that is, the internal storage state is not changed. The sequencer unit 12 is initialized only when the power is turned on. Also,
The dedicated storage unit 13 is provided with a backup power supply at the time of power failure as necessary, and is configured to be initialized only by a command from the sequencer unit 12 or the MPU 4.

As described above, according to one embodiment of the present invention, the sequencer 12
When detecting the occurrence of exception processing, the occurrence of direct memory access by a bus master other than the MPU 4, etc., the internal register information of the MPU 4, the address signal 1,
The dedicated storage unit 1 stores the data signal 2 and the control signal 3 in time series.
3 is stored. Therefore, even if the MPU 4 is abnormally stopped due to exception processing, the cause of the exception processing can be easily investigated, and a data processing device capable of automatically returning from the stopped state or the runaway state of the MPU 4 is realized. can do. The above-described embodiment can be applied to various devices that execute data processing, but is particularly effective when applied to a data processing device that performs image data processing or the like in a nuclear magnetic resonance imaging diagnostic apparatus.

In addition, a normal memory can be used as the dedicated storage unit 13, and when the storage content exceeds the storage capacity range, the oldest storage data is updated to the latest data and stored. An available storage means (ring buffer) may be used. Further, the storage unit 13 may be configured to include a non-volatile memory so that stored contents are not lost even during a power failure.

In the above embodiment, when the automatic return is possible, the reset block 11
Supply of only the reset signal 10 for return from the
Although the U reset signal 9 is configured to be output, the MPU reset signal 9 may be output after both the external reset signal 8 and the resetting reset signal 10 are supplied. Also, the reset block 11
Sends the reset signal not only to the main processor 4,
It can also be supplied to the input / output unit 6 and the like.

[0028]

The present invention is configured as described above and has the following effects. In the data processing device, a main storage unit, a main processor, an input / output unit, a sub-storage unit that stores an address signal, a data signal, and a control signal, an address bus, a data bus, and a control bus. When the access state of the bus is monitored and the occurrence of an interrupt, exception processing, or direct memory access by a device other than the main processor is detected, the states of the address signal, the data signal, and the control signal are stored in time series in the secondary storage unit. And a reset signal selection / synthesis unit that supplies a reset signal to the main processor based on the return reset signal and the external reset signal. Thereby, even when the main processor is stopped abnormally, it is possible to retain the state of the address signal, the data signal, and the control signal and the information such as the internal register of the main processor. In this case, it is easy to find the cause of the abnormality. Therefore, it is possible to easily determine the cause of the occurrence of the exception processing, and to realize a data processing device capable of automatically returning from the stopped state or the runaway state of the main processor.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention.

FIG. 2 is an operation flowchart of the example of FIG. 1;

FIG. 3 is a schematic configuration diagram of a conventional example of a data processing device.

FIG. 4 is an operation flowchart of the example of FIG. 3;

FIG. 5 is a schematic configuration diagram of another conventional example of a data processing device.

FIG. 6 is an operation flowchart of the example of FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 address signal 1B address bus 2 data signal 2B data bus 3 control signal 3B control bus 4 MPU (main processor) 5 main storage unit 6 I / O (input / output unit) 8 external reset signal 9 MPU reset signal 10 return reset signal 11 Reset block 12 Sequencer unit 13 Dedicated storage unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 11/14 G06F 11/00 G06F 11/30-11/34 G06F 13/00

Claims (5)

(57) [Claims] 1. A data processing apparatus, comprising: a main storage unit for storing instructions and data; a main processor for performing data processing using the instructions and data stored in the main storage unit; An input / output unit, an address signal indicating a data address, a data signal, a control signal for controlling transfer of the address signal and the data signal, and a sub storage unit for storing the address signal; and an address bus for transmitting the address signal. And a data bus for transmitting the data signal, and a control bus for transmitting the control signal. The main bus, the main storage unit, and the input / output unit control the access state of the address bus, data bus, and control bus. Monitor,
When the occurrence of an interrupt, an exception process, or the occurrence of a direct memory access by a main storage unit or an input / output unit other than the main processor is detected, the states of the address signal, the data signal, and the control signal are stored in time series in the sub-storage unit. And
In addition, interrupts, exception handling, or
Direct memory access by external main memory or input / output unit
When the occurrence of a process is detected, at least the main
Collects the internal register information of the processor and stores it in the sub-storage section.
Address and data stored in the secondary storage unit.
Data signal and control signal status and the internal
The main processor automatically recovers based on the
It is determined whether or not return is possible, and if automatic recovery is possible, an exception process occurrence monitoring unit that outputs a reset signal for recovery, the reset signal for recovery, and an external reset signal supplied from the outside. And a reset signal selection / synthesis unit that supplies a reset signal to at least the main processor. 2. The data processing device according to claim 1, wherein
The data processing device according to claim 1, wherein the sub-storage unit is a storage unit capable of circulating a storage area. 3. The data processing apparatus according to claim 1, wherein said sub-storage unit has a backup power supply capable of retaining stored information even when a power failure occurs. apparatus. 4. The data processing device according to claim 1, wherein said reset signal selecting / combining section only outputs the reset signal when said reset signal and said external reset signal are supplied. A data processing device for supplying a reset signal to the main processor. 5. The data processing device according to claim 1, wherein the exception processing occurrence monitoring unit determines the state of the address signal, the data signal, and the control signal stored in the secondary storage unit. The main processor has a determination unit for determining whether or not normal recovery is possible. If normal recovery is possible, data correction is performed, and an automatic recovery enable signal indicating that normal recovery is possible is reset signal selective synthesis. Wherein the reset signal selection / synthesis unit supplies a reset signal to the main processor regardless of whether an external reset signal is supplied or not, when the automatic resettable signal is supplied. Processing equipment.