JP2592360B2 - Computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system such as a microprocessor application system, and more particularly, to a computer system for performing hardware initialization at the time of system reset independently of an application by a main processor. .

[0002]

2. Description of the Related Art Conventionally, when initializing hardware (hereinafter abbreviated as H / W) of a computer system, a user sets a dip switch or a jumper to an initial value by referring to a system manual, or Activate an initialization routine stored in the main processor and execute H /
It was necessary to perform W initialization. FIG.
1 is a block diagram of a conventional computer system disclosed in Japanese Patent No. 54705. In the figure, reference numeral 1 denotes a main processor which controls the central processing of the system.
Is connected to a peripheral device 2 such as a memory and a peripheral LSI via an address bus and a data bus. The main processor 1 further includes an address decoding unit 36 for outputting a select signal for a peripheral device including a memory map setting register 46 and a ROM 56, which will be described later.
Memory map setting register 4 for initialization of W, that is, memory configuration for setting a memory map
6 and a ROM 56 storing an initialization routine for performing H / W configuration at power ON and initial values.
Is connected.

Next, a conventional initialization method by a computer system will be described with reference to a flowchart shown in FIG. When the power is turned on, the main processor 1 starts up and enters a reset state (S11). When the reset state is released, the main processor 1 accesses the ROM 56 and starts an initialization routine stored in the ROM 56 (S12). By the initialization routine, the main processor 1 reads out the initial setting values stored in the ROM 56 and sets them in the memory map setting register 46 (S13). This setting operation (H / W configuration) is called H / W initialization. The configuration of the main processor 1 and the peripheral device 2 is performed according to the initial setting value set in the memory map setting register 46 (S14). However, the ROM 56 is allocated to an area to which the main processor 1 immediately accesses after the reset is released, and its address is fixed, and an address map does not need to be set.

[0004] When the H / W initialization operation is completed, the main processor 1 is ready to execute an application (S15). That is, the address decoding unit 36 decodes the address from the main processor 1 in accordance with the information stored in the memory map setting register 46, and the chip select signal can be output to the peripheral device 2. When the user sets a dip switch or a jumper to an initial value, the setting is performed before the power is turned on. In this case, among the operations described above, H / W for setting the memory map
The configuration (S13) is not required.

[0005]

As described above, in the conventional computer system, the user sets the DIP switches and jumpers to the initial values with reference to the manual of the system, or sets the initial values stored in the main processor. It is necessary to initialize the H / W by activating the initialization routine, so that a failure due to an incorrect setting of a dip switch or a jumper by a user is likely to occur, and the main processor can access the setting register of the memory map. Therefore, when a failure occurs in the application and the main processor runs away, there is a risk that the set value of H / W is changed, and it becomes difficult to perform failure processing or return from the failure. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and it is an object of the present invention to provide a coprocessor for executing an initialization sequence and to provide a means for making a main processor inaccessible to an initial value setting register. Accordingly, an object of the present invention is to provide a computer system which can avoid occurrence of a failure due to a setting error at the time of initialization by a user, and can easily perform failure processing or return from a failure even when the main processor runs away.

[0006]

SUMMARY OF THE INVENTION A computer system of the present invention initializes constituent hardware so that a main processor can access a peripheral device and execute an application. A coprocessor having means for setting a value, operating independently of the main processor, a register storing an initial value set by the coprocessor, means for requesting the coprocessor to initialize hardware, and a main processor Means for making it impossible to access the register by the first processor.
The entire system including the coprocessor according to the
A first processing unit for initializing hardware, and a second resetting unit.
Processor and its peripheral devices according to the reset signal
A second processing unit for initializing the control unit .

[0007]

The computer system according to the present invention has two systems.
Since initialization is performed using the set signal, both reset signals
While selectively performing initialization of coprocessors and systems that operate independently of the main processor by selectively using
Since the main processor executing the application cannot access this register, even if the main processor runs away due to an application failure, the register setting value is not destroyed and the trouble of resetting is prevented.
I can stop it.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing the configuration of a first embodiment of the computer system according to the present invention. In FIG. 1, reference numeral 1 denotes a main processor which controls the central processing of the system and executes an application. The main processor 1 is connected to a peripheral device 2 such as a memory and a peripheral LSI and a peripheral device 2 via an address bus and a data bus. Peripheral device control unit 3 that outputs a control command to
Is connected. In the figure, reference numeral 5 denotes a coprocessor for performing a reset sequence at the time of power-on and H / W configuration. The coprocessor 5 controls all systems including the coprocessor 5 in accordance with a cold reset (CRST) signal given from the system. A CRST processing unit 501 for initializing H / W, and a coprocessor 5 and an H / W configuration register 4 according to an output of a warm reset (WRST) signal from the coprocessor 5
And a WRST processing unit 502 for initializing the main processor 1 and the peripheral device control unit 3 except for the above, and an H / W configuration processing unit 503 for executing the H / W configuration of the peripheral device 2. The coprocessor 5 is connected via an address bus and a data bus to an H / W configuration register 4 in which an initial value of H / W is set. The H / W configuration register 4 is connected to the peripheral device control unit 3 via a bus. That is, the H / W configuration register 4 is not connected to the main processor 1, and only the coprocessor 5 can access the H / W configuration register 4, but cannot access the main processor 1. .

The H / H according to the first embodiment having the above-described configuration is used.
The operation of W initialization will be described based on the flowchart shown in FIG. The computer system is CRST and W
Initialized by two reset signals of RST. When the power is turned on, the coprocessor 5 enters the CRST state in response to the input of the CRST signal from the system (S21). CR
When the ST is released, the CRST processing unit 501 is started, and the coprocessor 5 initializes itself (S22). CRST
When the processing is completed, the coprocessor 5
2 (S23), and outputs a WRST signal to the main processor 1 and the peripheral device controller 3 to initialize the main processor 1 and the peripheral device controller 3 (S2).
4). The coprocessor 5 activates the H / W configuration processing unit 53 while continuously outputting the WRST signal (S25), and accesses the H / W configuration register 4 to set the initial value of the peripheral device 2 (S26). ). That is, by this setting, the main processor 1 obtains H / W information necessary for accessing the peripheral device 2 from the H / W configuration register 4, and
Access according to the setting can be performed to the peripheral device 2.

After the setting is completed, the coprocessor 5 sends the WR to the main processor 1 and the peripheral device control unit 3.
The ST is released (S27), and the main processor 1 executes an application including an access to the peripheral device 2 (S28).

Further, even if a failure occurs in the application of the main processor 1 and the main processor 1 goes out of control, the main processor 1 cannot access the H / W configuration register 4, so that the register setting value Is not destroyed. Coprocessor 5
After detecting runaway of the main processor 1, for example, when the main processor 1 is restarted, a WRST signal is output to the main processor 1 to perform a reset operation. In this case, a CRST signal is not generated. H
It is not necessary to execute the initial setting for the / W configuration register 4 again.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the computer system according to the present invention. In this embodiment, a memory map setting register for address decoding is used as the hardware configuration register in the first embodiment. In the figure, the same or corresponding parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the figure, reference numeral 41 denotes a memory map setting register for initializing H / W, that is, for memory configuration (setting a memory map). The memory map setting register 41 is connected to the address decoding unit 31 that outputs a select signal (chip select) for the peripheral device 2 based on address data given from the main processor 1.

The memory map setting register 41 is not connected to the main processor 1, so that only the coprocessor 5 can access the memory map setting register 41 and cannot access the main processor 1. Note that the H / W initialization operation and the processing operation during runaway of the main processor 1 are the same as those in the first embodiment, and similar effects can be obtained.

FIG. 3 is a block diagram showing the configuration of a third embodiment of the computer system according to the present invention. In this embodiment, a watchdog timer (hereinafter referred to as WDT) is used as an H / W configuration register in the first embodiment.
Abbreviated as "). In the figure, the same or corresponding parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the figure, 6 is the main processor 1
A watchdog timer (hereinafter abbreviated as WDT) 42 for monitoring the runaway of the application is connected to the WDT 6, and is used to set whether the operation of the WDT 6 is enabled or disabled and to set the monitoring time of the WDT 6. Is a WDT setting register.

The main processor 1 is not connected to the WDT setting register 42, and only the coprocessor 5
The configuration is such that the setting register 42 can be accessed and the main processor 1 cannot. Also,
The error information at the time of the WDT error is stored in the WDT setting register 42.
And can be read by the coprocessor 5. The H / W initialization operation and the main processor 1
Is similar to that of the first embodiment, and the same effects as those of the first embodiment can be obtained.

FIG. 4 is a block diagram showing the configuration of a fourth embodiment of the computer system according to the present invention. In this embodiment, a register for setting a timeout period of a READY signal returned from a peripheral device to the main processor is used as the H / W configuration register in the first embodiment. In the figure, the same or corresponding parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the figure, reference numeral 7 denotes READ for monitoring the timeout of the READY signal returned from the peripheral device 2 to the main processor 1.
The Y timeout monitoring unit 43 is connected to the READY timeout monitoring unit 7, and is used to set whether to enable or disable the operation of the READY timeout monitoring unit 7 and to set a READY timeout setting register for setting the READY timeout time. It is.

READY timeout setting register 43
Is not connected to the main processor 1, only the coprocessor 5 can access the READY timeout setting register 43, and the main processor 1 cannot. Error information in the case of a READY timeout error is stored in the READY timeout setting register 43 and can be read by the coprocessor 5. Note that the H / W initialization operation and the processing operation during runaway of the main processor 1 are the same as in the first embodiment, and the same effects as in the first embodiment can be obtained.

FIG. 5 is a block diagram showing the configuration of a fifth embodiment of the computer system according to the present invention. In the present embodiment, a register for setting the area and size of the cache memory is used as the H / W configuration register in the first embodiment. In the figure, the same or corresponding parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the figure, reference numeral 8 denotes a cache memory, 9 denotes a cache control unit for controlling the cache memory, and 44 is connected to the cache control unit 9, and is used to set whether the operation of the cache control unit 9 is enabled or disabled and A cache setting register for setting the area and size of the cache memory 8.

The cache setting register 44 is not connected to the main processor 1, so that only the coprocessor 5 can access the cache setting register 44 and cannot access the main processor 1. The H / W initialization operation and the processing operation during runaway of the main processor 1 are the same as those in the first embodiment.
The same effects as in the first embodiment can be obtained.

FIG. 6 is a block diagram showing the configuration of a sixth embodiment of the computer system according to the present invention. In the figure, the same or corresponding parts as those of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the figure, reference numerals 111 to 11n denote H / W1 of the main processor 1, memory, setting register, and the like.
This is an IC card incorporating 2n and a coprocessor 5n for performing a reset sequence and H / W configuration when the power is turned on. The coprocessors 51 to 5n have a CR
An ST processing unit, a WRST processing unit, and an H / W configuration processing unit are provided. Further, reference numeral 13 in the figure has a system initialization management program 13A for managing H / W initial values for each of the IC cards 111 to 11n.
This is a system initialization management card that issues an initialization request to the IC cards 111 to 11n connected via the bus 10.
It manages the initialization of W121 to 12n. Also, inside the IC cards 111 to 11n, the H / W initial value setting register is not connected to the main processor 1, and only the coprocessors 51 to 5n can access the setting register. The configuration cannot access the setting register.

Next, the operation of the hardware initialization according to the sixth embodiment will be described with reference to the system initialization management card 1 shown in FIG.
3 will be described based on a flowchart showing an initialization request procedure and a flowchart showing an initialization procedure by the coprocessors 51 to 5n incorporated in the IC cards 111 to 11n shown in FIG. When the power is turned on, by executing the system initialization management program 13A (S31), the IC is transmitted from the system initialization management card 13 via the bus 10 to the IC.
H / is provided to the coprocessors 51 to 5n of the cards 111 to 11n.
A request to initialize W is notified (S32). At this time, I
The C cards 111 to 11n receive the same CRST signal as in the first embodiment (S4) by the coprocessors 51 to 5n.
The reset sequence from 1) to WRST signal output (S44) is completed, and the system is in a state of waiting for an H / W initialization request from the system initialization management card 13 (S45). The coprocessors 51 to 5n are connected to the system initialization management card 13
When the H / W initialization request is received from the CPU, the H / W configuration unit is started (S46), and the IC cards 111 to 1 are activated.
Initial setting of the corresponding H / Ws 121 to 12n is performed for each 1n (S47). When WRST is released (S4
8), the main processor 1 can execute the application (S49). The processing operation during the runaway of the main processor 1 inside the IC cards 111 to 11n is the same as in the above-described embodiment.

The above-described multiprocessor system is provided with each IC card 11 according to the H / W configuration of the IC card.
H / provided in the coprocessors 51 to 5n of 1 to 11n
Even if the W configuration processing unit is not changed, system initialization data is managed by the system initialization management program 13A of the system initialization management card 13, and at the time of change, the data of the system initialization program 13A is changed. Since the changed H / W initialization data is notified to the coprocessor of each IC card, H / W initialization suitable for the IC card can be easily managed.

[0023]

As described above, in the computer system according to the present invention , the coprocessor has two channels of reset.
The entire system, including the coprocessor, is
Hardware or main processor and its peripheral control parts
Together with selective initializing timing necessary initialization, since the impossible access to the initial value setting register by the main processor, it can prevent the destruction of the set value by runaway main processor, resetting Times of annoyance
It has excellent effects such as avoidance.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a computer system according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of the computer system according to the present invention.

FIG. 3 is a block diagram showing a configuration of a third embodiment of the computer system according to the present invention.

FIG. 4 is a block diagram showing a configuration of a fourth embodiment of the computer system according to the present invention.

FIG. 5 is a block diagram showing a configuration of a fifth embodiment of the computer system according to the present invention.

FIG. 6 is a block diagram showing a configuration of a sixth embodiment of the computer system according to the present invention.

FIG. 7 is a flowchart illustrating an operation of H / W initialization according to the first to fifth embodiments of the computer system according to the present invention.

FIG. 8 is a flowchart illustrating an operation of H / W initialization according to a sixth embodiment of the computer system according to the present invention.

FIG. 9 is a flowchart illustrating an operation of H / W initialization according to a sixth embodiment of the computer system according to the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional computer system.

FIG. 11 is a flowchart illustrating an operation of H / W initialization by a conventional computer system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main processor 2 Peripheral device 3 Peripheral device control part 4 H / W configuration register 5 Coprocessor 6 WDT 7 READY monitoring part 8 Cache memory 9 Cache control part 10 Bus 13 System initialization management card 13A System initialization management program 22 Peripheral Device control unit 41 Memory map setting register 42 WDT setting register 43 READY timeout setting register 44 Cache setting register 51-5n Coprocessor 111-11n IC card 121-12n H / W 501 CRST processing unit 502 WRST processing unit 503 H / W configuration Processing unit

Claims (1)

(57) [Claims] Claims: 1. A main processor accesses a peripheral device to execute an application.
In a computer system for initializing the configuration hardware, having means for setting an initial value of the hardware,
A coprocessor that operates independently of the main processor,
A register for storing an initial value set by the coprocessor,
Means for requesting the coprocessor to perform hardware initialization, and means for making the main processor inaccessible to the register , wherein the coprocessor comprises a first processor.
System including the coprocessor according to the reset signal of
A first processing unit for initializing the hardware of the body;
The main processor and its peripheral data are
A second processing unit for initializing the device control unit .