JP3299115B2 - Redundant system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplex system, and more particularly, to a data sharing method between systems using a main memory.

[0002]

2. Description of the Related Art Conventionally, a storage device for shared data (hereinafter referred to as GM: global memory) is provided in a system separately from a main storage device of each processor, and a processor of each system is connected via an I / O bus. We used commonly.

FIG. 11 shows a configuration of a conventional duplex system. The regular system is an I / O bus 064, a processor 010 containing a main memory 030 and a regular system GM for shared data.
005 is connected, the standby system is an I / O bus 164, and the processor 110 including the main memory 130 and the standby system GM1 are connected.
05 is connected, and the shared data between the regular GM 005 and the standby GM 105 is matched via the matching bus 060. In this method, the size of the shared memory area is fixed.

[0004]

In the conventional data sharing method between dual processors, a GM is required in addition to the main memory, which not only complicates the system configuration but also causes the two storage devices to have a problem. Therefore, there is a problem that memory resources cannot be used effectively, which leads to an increase in cost. Of course, the failure of the GM stops the processing of the entire system using the shared data.

[0005] Further, depending on the type of data, two memory accesses for storing data in both the main memory and the GM are required, and there is a problem that the processing time of the duplex system is increased as compared with the single system. In particular, in a multiprocessor system, the GM is used via a common I / O bus. Therefore, when the amount of shared data increases, the access waiting time of each processor increases, and the advantage of the processing performance improvement by the multiprocessor is diminished. Resulting in.

Further, when constructing multitask software with each processor, it is necessary to allocate a shared data area used for each task to a predetermined area on the GM, so that the system development and change become more complicated. There was a problem.

An object of the present invention is to provide a simple and highly processable duplex system that does not use GM by handling shared data on a main memory in view of the above-mentioned problems of the prior art.

Each task (job) of each processor
By arbitrarily and dynamically switching the shared data area for each task, when building software using a multitasking program, there is no need to allocate a shared area between tasks, making software development and changes easy. To provide a redundant system.

Another object of the present invention is to provide a high-speed duplex system capable of performing parallel processing of communication between processors in a system and matching of shared data between systems in the case of a multiprocessor.
Another object of the present invention is to provide a highly reliable duplex system that enables a matching process by a detour route by another processor in a system when a route between the systems has an abnormality.

[0010]

An object of the present invention is to provide an MPU and a main storage device connected by a main memory bus, and a shared data matching device (hereinafter referred to as CME) having a transmission / reception circuit for transmitting / receiving shared information to / from a partner system. Abbreviated name), the main storage device has a shared area for storing the shared data, and the CME transmits access information including an address and data to be written from the MPU to the main storage device from the main memory bus. Memory access information obtaining means for snooping, memory access means for writing to the shared area when received information from a partner system is the shared data, shared area setting means for specifying a range of the shared area, the access information or the received information When the address in the shared area is within the range of the shared area, the shared data is determined to be the shared data. It is achieved by providing the monitoring means.

The CME transmits / receives data from its own processor.
It has a transmission / reception state management means for switching a flow of information in the CME to a transmission side or a reception side according to a reception state. Further, a matching bus is provided for connecting the processor of the own system and the processor of the partner system for transmitting and receiving the shared data, so that the matching processing can be performed in parallel with the processing of the MPU.

[0012] In addition, when the main storage device stores multitasks, the main storage device has a shared area for each task for storing the shared data, a setting area for each shared area range,
A storage area that temporarily saves the shared area range of the certain task when another task is executed during the execution of a certain task, wherein the CME manages the shared area range according to task switching; When the access information or the address in the reception report is within the range of the shared area, this is achieved by providing a shared data monitoring unit that determines the information as shared data.

Further, the above object is to provide a multiprocessor duplex system having a shared area for storing the shared data in a main storage device, and connecting the transmission / reception circuit between a corresponding system processor and a corresponding system processor. This is achieved by providing a matching bus that performs shared data matching processing in parallel with communication between processors in the system by the IO bus.

The CME includes an abnormality monitoring means for monitoring a response signal from a partner system via the matching bus, a transfer area setting means for designating a transfer area address of another processor, and the abnormality monitoring means comprising: A bus I that outputs the transfer area address and the access information to the I / O bus interface when detecting (no response).
F means is provided, and the shared data is transmitted to the partner system through a detour route passing through another processor in the system and its matching bus.

The transfer area address is set in an address range of a transfer data buffer provided in the CME of the other processor. Alternatively, it is set in the address range of the transfer area provided in the main storage device of the other processor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a duplex system according to the present invention and embodiments of a multiprocessor duplex system will be described below in detail with reference to the drawings.

[Embodiment 1] FIG. 1 shows a schematic configuration of a duplex system according to the present embodiment. An ordinary processor 010 mainly includes an MPU 020 for performing data processing, memory control, or input / output control, a main memory 030 for storing programs and data, a shared area 033 for storing shared data, and a standby system via a matching bus 060. Processor 1
10 and a shared data matching device (CME: Common Memory Equlizer) 040 for matching the shared data.

The MPU 020 and the main memory 030 are connected by a main memory bus 21 for performing memory access, and the CME 040 is connected to the main memory bus 21. The CME 040 includes a memory access information acquisition circuit 0 that directly fetches access information from the processor 010 to the main memory from the main memory bus 021 by snoop.
41 and the shared data received from the regular system
A memory access circuit 046 for writing on 0, a transfer range comparison circuit 042 for checking whether the transfer range arbitrarily specified and the address of the main memory access information are within the transfer range, and the standby processor 110. It comprises a transmission / reception circuit 043 for transmitting / receiving shared data.

The transfer range comparison circuit 042 is a register for arbitrarily setting a common area, and includes a common area lower limit register 045 and a common area upper limit register 044. Also, the transmission buffer 24
4. A reception buffer 245 is provided. The hardware of the standby processor 110 has the same configuration as the hardware of the service processor 010. The service system / standby system is switched to the service system by a well-known switching function when there is an accident in the service system.

In the present system, matching of shared data is performed as follows. FIG. 2 shows main memory maps of the service system and the standby system. The service processor 010 specifies the address range of the shared area 033 in the shared area lower limit register 045 and the shared area upper limit register 044 at the time of initial startup.

When the MPU 020 accesses the main memory 030, the CME 040 transfers the main memory access information on the main memory bus 21 to the memory access information acquisition circuit 0.
If the address in the main memory access information is within the address range of the shared area 033 (here, the shared area 033 is set to an address from 500 to 1000 in the main memory) if the address in the main memory access information is within the address range of the shared area 033. The access information is determined to be shared data. Then, the shared data including the address and the data is transferred to the transmission buffer 244 of the transmission / reception circuit 043, and transmitted to the standby processor 110 via the matching bus 060.

The operation of the standby processor 110 is similar to that of the service processor, and the address range of the shared area 133 is set by the shared area lower limit register 145 and the shared area upper limit register 144 at the time of initial startup. Standby CME
140 receives from the service system, transfers the address and data of the reception information stored in the reception buffer 345 to the transfer range comparison circuit 142, and checks whether or not the data is within the address range of the shared area 133. Within the address range of the common area 133 (in this case, the common area 133 is set at addresses 500 to
If the address is set to 1000), the data is sent via the memory access circuit 146 and the main memory bus 121,
The data is written to the shared area 133 of the main memory 130. Thereby, the shared data matching (sharing) of the service processor 010 and the standby processor 110 ends.

As described above, the duplex system of the present embodiment has a function of snooping access information (address and data) to the main memory directly from the main memory and comparing the information with a preset shared data area. Each processor is provided with a shared data matching device having a function of transmitting only the data area to the partner system and a function of writing the data in the main memory of the own system when the information received from the partner system is the shared data area. Data matching between the main memory of the processor and the standby processor is performed. Hereinafter, the configuration and operation of the present embodiment will be described in detail.

FIG. 3 shows the configuration of the shared data matching device (CME) according to the first embodiment. The figure shows the CME 040 of the regular system, but the CME 140 of the standby system.
Is the same. The shared data matching function between the service system and the standby system for the CME 040 will be described below.

First, the operation at the time of transmitting shared data will be described. In the ordinary system, the access information acquisition timing circuit 050 in the memory access information acquisition circuit 041 is
A timing signal is generated from the memory write signal 252 and the memory selection signal 253, and the memory signal 250 is loaded into the memory access information acquisition data register 241 and the memory address 251 is loaded into the memory access information acquisition address register 240 according to the timing signal.

The address in the memory access information acquisition address register 240 corresponds to the shared area range comparison circuit 051.
And compared with the addresses of the shared area upper limit register 044 and the shared area lower limit register 045. It should be noted that a plurality of shared area lower limit registers 045 and shared area upper limit registers 044 are provided, and the shared area 033 to be set is set.
Is not limited to a single range, and a plurality of ranges can be specified.

As a result, if it is determined that the address is within the shared area, the shared area range comparison circuit 051 sends the matching signal 256 to the transmission address buffer 008 and the transmission data buffer 009, and the memory access information acquisition address register 240 The address 001 and the data 002 in the memory access information acquisition data register 241 are stored in the transmission address buffer 008 and the transmission data buffer 0, respectively.
09.

Address 001 in transmission address buffer 008 and data 002 in transmission data buffer 009
Is transferred to the transmission buffer 244 and transmitted to the standby system as shared data 003 by a timing signal generated by the timing circuit 049.

Next, an operation at the time of receiving shared data will be described. In the standby system, the received information is transmitted to the transmission / reception circuit 04.
3, the timing circuit 049 is activated, the state of the transmission / reception state management circuit 047 is switched to the reception system, and the CME0
The signal direction in 40 switches to the receiving side.

The address 001 and the data 0 of the reception buffer 245 are obtained by the timing signal of the timing circuit 049.
02 is transferred to the reception address buffer 006 and the reception data buffer 007. Receive address buffer 006
Are transferred to the shared area range comparison circuit 051, and are compared with the addresses of the shared area upper limit register 044 and the shared area lower limit register 045.

As a result, when it is determined that the address is within the shared area, the shared area range comparison circuit 051 operates the memory access data register 24 in the memory access circuit 046.
2 to the memory access address register 243, and the address 001 in the reception address buffer 006 and the data 00 in the reception data buffer 007.
2 are the memory access address registers 243, respectively.
Is taken into the memory access data register 242.

The memory access right acquisition circuit 052 in the memory access circuit 046 issues a memory bus use right request signal 254 to the MPU 020, and upon receiving the memory bus use permission signal 255 from the MPU 020, activates the memory bus interface 051, A memory write signal 252 and a memory selection signal 253 are transmitted to the main memory 030. Then, the address 001 in the memory access address register 243 and the memory access data register 2
The data 002 in 42 is transferred to the main memory 030 via the memory bus interface 051, and the matching of the shared data ends.

As described above, in the duplex system of the present embodiment,
A common shared area is set in the main memory of each processor, and when the regular MPU writes information to the main memory,
This information is snooped from the main memory bus and transferred to the standby system if the address is in the shared area, while it is transferred to the main memory if the address of the received information is in the standby system from the service system in the local system. It implements a shared data matching method for writing.

According to this, it is not necessary to use the conventional GM, and the system configuration can be simplified and the cost can be reduced. In addition, since the shared area can be arbitrarily set on the main memory, programming can be performed freely without being aware of the difference between single system and dual system and the capacity of the shared data area.
System development and changes are easier. Note that the present embodiment has been described using the example of the standby redundant system, but the present embodiment is also applicable to a parallel redundant system.

[Embodiment 2] FIG. 4 shows a configuration of a duplex system using a multiprocessor according to the present embodiment.
The shared data matching device CME of each processor has the same configuration as that of the first embodiment.

An ordinary system of the present multiprocessor duplex system has a basic processor (# 1) 010 and a plurality of extension processors (# 2) 011 and (# 3) 012, and an I / O bus 064 for performing interprocessor communication. Connected by Each processor has a built-in main memory 030 having a shared area 033. The standby system also has a basic processor (# 1) 110 and a plurality of extended processors (# 2) 111 and (# 3) 112. And I / O bus 1
64.

The basic processor 010 of the service system and the basic processor 110 of the standby system are connected by a matching bus A061 for transferring the shared data in the main memory 030 of the service system to the main memory 130 of the standby system. Similarly, the extension processors 011 and 112 of the regular system respectively correspond to the extension processors 111 and 112 of the standby system and the matching bus B06.
2. Connected by the matching bus C063. Each processor has an I / O bus IF 090 (hatched block in the figure), and an I / O bus 064 or I / O bus
It is connected to the / O bus 164 and exchanges data.

Each processor includes a matching bus A061 and a matching bus B06 provided separately between the service system and the standby system.
2. The shared data matching process in the main memory 030 is performed asynchronously via the matching bus C063. Apart from this matching processing, inter-processor communication is performed in parallel between the processor 010 and the extension processor 011, between the processor 010 and the extension processor 012, or between the extension processor 011 and the extension processor 012 on the I / O bus 064. it can. Similarly, the standby system can process inter-processor communication.

According to the redundant system of the multiprocessor according to the present embodiment, since the main memory of each processor has a common area, the common hardware such as the GM is not required for the entire system. Is simplified in configuration and operation, and the cost can be reduced. In addition to the I / O bus for performing inter-process communication, a matching bus for enabling matching of shared data with other systems is provided, so that communication by task processing between multiprocessors and sharing of shared data are performed. Communication of the matching processing can be performed in parallel, and the processing performance of the multiprocessor system can be ensured.

[Embodiment 3] The basic configuration of the multiprocessor duplex system according to the present embodiment is the same as that of the system of Embodiment 2. Here, a description will be given of another route matching method in which when there is a failure in the route of the matching bus, matching is performed using another route.

FIG. 5 is an explanatory diagram showing the matching by another route in the multiprocessor duplex system.
When an abnormality occurs in the matching bus A061 connecting the service processor 010 and the standby processor 110, the matching routes shown in FIG.

FIG. 6 shows the configuration of the CME in this embodiment. The CME of each processor is configured as follows based on the configuration of FIG. CM of processor 010
E040 is shared data 003 (addresses 001, 001) between adjacent processors via an I / O bus 064 in the system.
In order to bypass the data 002), the bus IF circuit 093
Is provided with a transfer buffer 036 for other processors. In addition, to set the transfer area of the shared data to be transferred,
The transfer range comparison circuit 042 is provided with another processor transfer area upper limit register 095 and transfer area lower limit register 096. Although not shown, the extension processor # 2,
The # 3 CME 040 is also provided with a transfer buffer 036 for buffering shared data of another processor and upper and lower limit registers.

In the normal shared data matching operation according to this configuration, the transmission / reception circuit 043 operates in the transmission address buffer 008.
And the data in the transmission data buffer 009 to the standby system via the matching bus 060, and when the abnormality monitoring unit 098 receives a response signal indicating normal reception from the standby system, the matching bus 060 is normal. Judge. The matching operation in this case is the same as in the first or second embodiment. Next, the operation of each processor when matching is performed using another route when an abnormality occurs on the matching bus will be described in detail.

[Operation of Service Processor # 1] When an abnormality occurs in the matching bus A061, the standby processor 11
0 returns an abnormal reception response signal (no response at disconnection failure) to the service processor 010. Thereby, the abnormality monitoring unit 09 of the transmitting / receiving circuit 043 in the CME of the service processor 010
8 detects an abnormality and transfers the data 002 (AAA) in the transmission data buffer 009 and the address 001 (address 500) in the transmission address buffer 008 to the bus IF circuit 093.
Transfer to

The bus IF circuit 093 is an I / O bus IF09.
0, the transfer destination area (here, the start address = 1000) by the other processor transfer area upper limit register 095 and lower limit register 096 is output to the I / O bus IF 090, and the address 001 and the data 002 is output. As a result, the data 002 of the shared area information and its address 001 are transferred from the transmission / reception unit 092 via the I / O bus 064 to the I / O bus IF 090 of the expansion processor 011.

[Operation of General-purpose Extended Processor # 2] I /
The extension processor 011 that has received the address 001 and the data 002 in the transfer buffer 036 corresponding to the specified start address via the O bus IF 090 passes the transfer destination area to the transfer range comparison circuit 042, and transfers the other processor transfer area. A comparison is made with a setting area (set at addresses 1000 to 1200) set by the upper limit register 095 and the lower limit register 095.

As a result, if the designated transfer destination area is within the set area, it is determined that the data is shared data by detour from another processor, and the address 001 is transmitted to the transmission address buffer 008, and the data 002 is transmitted to the transmission data buffer 009. Transfer to The contents of the buffers 008 and 009 are transferred to the transmission / reception circuit 043 of the standby extended processor 111 (# 2) via the matching bus B062 together with the transfer destination area information.

[Operation of Standby Extended Processor # 2] The address 001 and the data 002 from the regular extended processor 011 are determined according to the transfer destination area information (address 1000).
Receive address buffer 006, Receive data buffer 00
7 is stored. After that, in the transfer range comparison circuit 042,
The transfer destination area information is compared with the set shared area or another processor transfer area, and in the latter area range, it is determined to be shared data by detour from another processor,
The data 002 and the address 001 are transferred to the bus IF circuit 093.

The processor selecting unit 094 in the bus IF circuit 093 sends the other processor transfer area address (1000
Address 001 (address 500) and outputs it to the I / O bus IF090. After that, the data 002 (AAA) is output to the I / O bus IF090, and is transferred to the I / O bus IF090 of the standby processor 110 via the I / O bus 164.

[Operation of Standby Regular Processor # 1] The address information = 500 from the extension processor 111 is
Via the transmission / reception unit 092 in the I / O bus IF090,
The data information = AAA is written to the address 500 on the main memory 130, and the matching is completed.

According to the present embodiment, the CM of each processor
E includes a transfer storage buffer for storing shared information (address and data) transferred for another processor for matching, and when a failure occurs in the matching bus, an adjacent processor of the own system. Since the shared data is transferred to the partner system by a detour via, and the shared data can be matched, the reliability of the system can be improved.

[Embodiment 4] In Embodiment 3, a buffer for transferring shared data of another processor is provided in the CME of each processor. On the other hand, in the multiprocessor system of the present embodiment, a transfer area for shared data of another processor is provided in the main memory of each processor. The configuration of the CME is the transfer buffer 03 for other processors.
6 except that it does not have the configuration 6.

The configuration of the multiprocessor and the duplex system configuration of this embodiment are basically the same as those of the above embodiment, and the matching method will be described using an example using a different route shown in FIG. That is, when a failure or abnormality occurs in the matching bus A061 connecting the service processor 010 and the standby processor 110, the processor 010 receives an abnormality reception response signal (no response at the time of disconnection failure) from the processor 110. , The transfer by the matching bus A061 is determined to be impossible, and the matching process is performed by the route.

FIG . 7 shows a main memory map in this embodiment. A shared area 033 is allocated to addresses 500 to 1000 of the main memory 030 of the service processor 010 (# 1), and in the figure, the shared data = AAA at the address 500.
Is stored. When the coincidence bus A061 fails, # 1
General-purpose extension processor 011 which performs the matching process of
The address transfer area 034 and the data transfer area 035 of # 1 are allocated to addresses 1000 to 1200 of the main memory 030 of (# 2).

The main memory 030 of the standby extension processor 111 (# 2) has the same mapping as the main processor # 2, and the address transfer area 134 and the data transfer area 135 are allocated to addresses 1000 to 1200.
The main memory 030 of the standby processor 110 (# 1), which is the matching destination, has the same mapping as that of the regular processor # 1. Hereinafter, the operation according to this configuration will be described in detail.

[Operation of Service Processor # 1] When an error occurs in the coincidence bus A061 and an abnormal reception response signal (no response at the time of disconnection failure) from the standby processor 110 is received, the service processor 010 is loaded into the CME. Transmission / reception circuit 0
43, the abnormality monitoring unit 098 detects the abnormality, and transfers the data 002 (= AAA) in the transmission data buffer 009 and the address 001 (= 500 address) in the transmission address buffer 008 to the bus IF circuit 093.

The bus IF circuit 093 is connected to the extension processor 0
11 other processor transfer area (upper limit register 0
95, lower limit register 096) area information (here,
I / O bus IF090
And at the same time, the address information = 500 and the data information = AAA, which are shared data, are transmitted to the I / O bus IF0.
90. These pieces of information are transferred to the I / O bus IF090 of the extension processor 011 via the I / O bus 064.

[Operation of the service processor # 2] Destination area information (= 100) from the service processor 010
Address 0) and the address information and data information of the shared data are taken into the transfer range comparison circuit 042 via the bus IF circuit 093 in the CME, where the transfer area is determined by the other processor transfer area upper limit register 095 and lower limit register 095. It is compared with a range (here, addresses 1000 to 1200), and it is checked whether or not the data is shared data. In the case of shared data, the address information is transferred to the transmission address buffer 008, and the data information is transferred to the transmission data buffer 009. Thereafter, the contents of the buffers 008 and 009 are transmitted to the transmission / reception circuit 043 of the standby extension processor 111 via the matching bus B062 as in the case of the third embodiment.

[Operation of Standby Extended Processor # 2] The address information (= 500 address) of the other processor received from the regular extended processor 011 is stored in the reception address buffer 006, and the data information (= AAA) is received in the reception data buffer 007. Once, the transfer range comparison circuit 04
2, transfer area range (addresses 1000 to 1200)
To determine whether the data is shared data of another processor. In the case of shared data from another processor, the bus IF circuit 093
Transfer to

Processor selection unit 0 of bus IF circuit 093
94 is another processor transfer destination area (= 1000 address)
Is converted to an address 001 (= 500 address) and output to the I / O bus IF090. After that, data 002
(= AAA) is output to the I / O bus IF090, and the I / O bus
Via the bus 064, the I
/ O bus IF090.

[Operation of Standby System Regular Processor # 1] The address 001 and data 002 transferred from the extension processor 111 are transmitted and received by the transmitting / receiving unit 09 of the I / O bus IF090.
2, the data is written as data = AAA at the address = 500 in the main memory 030, and the matching is completed.

According to the present embodiment, when an abnormality occurs in the matching bus route, matching can be performed by another route, so that the reliability of the multiprocessor duplex system can be improved. In particular, since a part of the main memory is used as a transfer buffer of another route, the storage area of other processor shared information (address, data) can be made variable.

In the above-described embodiment, when the shared data is made identical between the service processor 010 and the standby processor 110 by a detour, the service expansion processor 011 and the standby expansion processor 111 are connected to each other by the other processor. The shared data can be directly transferred to the matching bus 060 and the I / O bus 064 without writing the shared data to the main memory. As a result, the memory write time during the shared data matching process can be reduced, and the matching process can be sped up.

[Embodiment 5] In this embodiment, a shared data matching system in a multi-task duplex system will be described. In this embodiment, at the time of task switching, the shared area is variably set for each task. Figure 1 shows the hardware
3 is the same as that of FIG.

FIG. 8 shows a main memory map of the present embodiment. Each main memory 030 (130) has a task # 1 to a task # 1.
# 3 shared area 071 for task # 1 which becomes variable
Task # 2 shared area 073, task # 3 shared area 075, and task-specific program storage areas 072, 0
74, 076 and a task setting area 089 are provided.

The task setting area 089 sets the upper limit and lower limit of the address of the shared area for each task. The upper limit areas 081, 083, and 085 and the lower address areas 082, 084, and 086 of the shared address are set at the last time when the task is switched. It has pre-task storage areas 087 and 088 for saving the upper and lower limit of the shared address of the task. In the task setting area 089, the address range of the shared area of each task is specified at the time of initial startup.

FIG. 9 shows a flow of the task switching operation. The task switching is processed by the task management function 099 of the OS. When the task # 2 is activated during the processing of the task # 1, the OS reads the shared address range of the task # 1 indicated by the upper limit register 044 and the lower limit register 045 of the CME, and saves the previous task save area 087 on the main memory 030. , 088 (S1). Next, the OS sets the shared address range of task # 2 indicated by the shared upper limit area 083 and the lower limit area 084 of the main memory to the shared area upper limit register 044 and the lower limit register 045 in the CME 040.
(S2).

FIG. 10 shows an example of a main memory map by task switching. FIG. 9A shows the execution of task # 1, where 100 is stored in the upper limit area 081 of the task # 1 and 200 is stored in the lower limit area 082.
The shared area 071 is located at addresses 100 to 200 on the main memory. FIG. 9B shows the execution of task # 2, and the task # 2 shared area 073 is located at addresses 500 to 600 on the main memory.

Thereafter, the process of task # 2 is started (S2). When the processing of task # 2 ends, the OS writes back the address values in the previous task storage area upper limit 087 and the previous task storage area lower limit 088 to the shared area upper limit register 044 and the lower limit register 045 of the CME 040 (S4). The process of # 1 is restarted.

As described above, since the shared area upper limit register 044 and the lower limit register 045 can be dynamically rewritten at the time of task switching, address management of shared data for each task becomes possible. The operation of matching the shared data by the CME after the task switching is performed in the same manner as in the first embodiment.

According to the present embodiment, the shared area for each task can be dynamically variably set, so that it is not necessary to secure a shared area in consideration of additional tasks, and effective use of memory resources becomes possible. Also, when designing the program,
Because you can program without being aware of other tasks,
Software development becomes easier.

[0072]

According to the duplex system of the present invention, the function of directly snooping the main memory bus, detecting data accessing the shared data area on the main memory, transmitting the data to the partner system, and performing the matching process. Is provided in each processor, so that the conventional system common GM is not required, and there is an effect that the memory resources can be effectively used and the memory management can be simplified.

Further, since the shared data area on the main memory is arbitrarily specified and the data accessing the shared area is centrally managed so as to perform the matching process, software can be developed without being conscious of the shared data. .

According to the multitask duplication system of the present invention, the shared area for each task in the main memory is dynamically switched at the same time as the task switching. Is unnecessary, and system development and change become easy.

According to the multiprocessor duplex system of the present invention, a shared bus is provided between the systems separately from the system common bus (I / O bus) to transfer shared data. Even when the transfer process of the shared data is started and the shared data is increased by the multiprocessor, the matching process can be sped up, and the processing performance of the multiprocessor can be maintained. Alternatively, it is possible to prevent a reduction in processing capacity in a duplex system compared to a single system.

In addition, when a predetermined matching bus route fails, the system has a function of matching another route via an adjacent processor and its matching bus, so that the reliability of the system can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a duplex system according to a basic embodiment of the present invention.

FIG. 2 is a main memory map in the embodiment of FIG. 1;

FIG. 3 is a shared data matching device (CM) according to the first embodiment.
FIG.

FIG. 4 is a configuration diagram of a redundant system of a multiprocessor according to a second embodiment.

FIG. 5 is an explanatory diagram of a route according to a different route matching method according to the third embodiment.

FIG. 6 is a CME of another route matching method according to the third embodiment.
FIG.

FIG. 7 is a main memory map according to the fourth embodiment.

FIG. 8 is a main memory map according to the fifth embodiment.

FIG. 9 is a flowchart of task switching in a fifth embodiment.

FIG. 10 is a main memory map of an operation example according to the fifth embodiment.

FIG. 11 is a configuration diagram of a conventional duplex system using GM.

[Explanation of symbols]

001: address, 002: data, 003: shared data, 006: reception address buffer, 007: reception data buffer, 008: transmission address buffer, 009 ...
Transmission data buffer, 010: regular processor, 01
1 to 012: a general-purpose extended processor, 020: MPU,
021: Main memory bus, 030: Main memory, 033: Shared area, 036: Transfer buffer for other processors, 04
0: CME, 041: memory access information acquisition circuit, 0
42: transfer range comparison circuit, 043: transmission / reception circuit, 044
... shared area upper limit register, 045 ... shared area lower limit register, 046 ... memory access circuit, 047 ... transmission /
Reception state management circuit, 049 timing circuit, 050 ...
Access information acquisition timing circuit, 051: memory bus interface, 052: memory access right acquisition circuit, 060: regular system coincidence bus, 061 ... regular system coincidence bus A, 062 ... regular system coincidence bus B, 063 ... regular system Matching bus C, 064: regular I / O bus, 070: shared area, 071: shared area for task # 1, 073 ...
Shared area for task # 2, 075 ... shared area for task # 3, 081 ... upper limit for shared area of task # 1, 082 ... lower limit for shared area of task # 1, 083 ... upper limit for shared area of task # 3, 084 ... shared area for task # 3 Lower limit, 085 ...
Task # 3 shared area upper limit, 086 ... task # 3 shared area lower limit, 087 ... previous task storage area upper limit, 088 ...
Previous task saving area lower limit, 089 ... task setting area,
090 ... I / O bus IF, 091: Other processor transfer area report register, 092 ... Transceiving unit, 093 ... Bus I
F circuit, 094: processor selection unit, 095: other processor transfer area upper limit register, 096: other processor transfer area lower limit register, 097: buffer control unit, 09
8: abnormality monitoring unit, 099: OS, 110: standby processor, 111, 112: standby extended processor, 120
... MPU, 121 ... main memory bus, 130 ... main memory,
133 ... shared area, 134 ... address transfer area for processor 010, 135 ... data transfer area for processor 010, 136 ... transfer buffer for processor 010,
137 transfer buffer for processor 011 138 address buffer 139 data buffer 140 C
ME, 141... Memory access information acquisition circuit, 142.
Transfer range comparison circuit, 143 transmission / reception circuit, 144 common area upper limit register, 145 common area lower limit register, 146 memory access circuit, 164 general-purpose I / O
O bus, 240 ... memory access information acquisition address register, 241 ... memory access information acquisition data register, 242 ... memory access data register, 243 ...
Memory access address register, 244: transmission buffer, 245: reception buffer, 250: memory data, 2
51: memory address, 252: memory write signal, 2
53: memory selection signal, 254: memory bus use right request signal, 255: memory bus use permission signal, 255, 25
6. Matching signal.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Kurosawa 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Ryoichi Takamatsu 5-2-2, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Omika Plant (72) Inventor Akihiro Ohashi 2-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Omika Plant (72) Inventor Tadahiko Hashimoto 5, Omikacho, Hitachi City, Ibaraki Prefecture No. 2 in Hitachi, Ltd. Omika Plant (72) Inventor Koji Masui 5-2-1, Omika-cho, Hitachi City, Ibaraki Pref. Hitachi, Ltd. In Omika Plant (56) References JP-A-62-169244 (JP) , A) JP-A-4-74233 (JP, A) JP-A-5-113898 (JP, A) JP-A-58-137065 (JP, A) Flat 3-44737 (JP, U) (58 ) investigated the field (Int.Cl. ^7, DB name) G06F 11/16 - 11/20

Claims (2)

(57) [Claims] An MPU, a main storage device, and a plurality of processors having an I / O bus interface are connected by an I / O bus (or a system bus), and are shared with a multiprocessor including a normal system and a standby system, and a partner system. In a multiprocessor duplex system in which each processor includes a shared data matching device (hereinafter abbreviated as CME) having a transmission / reception circuit for transmitting and receiving information, a shared area for storing the shared data in a main storage device is provided. And a matching bus for connecting the transmission / reception circuit between the own system and the other system's processor is provided, and the CME can perform shared data matching processing in parallel with communication between processors in the system by the I / O bus. A duplex system for a multiprocessor, wherein the CME is configured as described above. 2. The CME according to claim 1, wherein the CME is a memory access information acquisition unit that snoops access information including an address and data to be written from an MPU to a main storage device from a main memory bus; Memory access means for writing to the shared area in the case of data, shared area setting means for designating the range of the shared area, when the address in the access information or the received information is within the range of the shared area, A multiprocessor duplex system comprising shared data monitoring means for determining shared data.