JPH09305424A - Dual systems - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide simple fast dual systems which manages common data with main memories without using a system-shared global memory(GM). SOLUTION: When an MPU 020 of an in-use system processor 010 gains write access to the main memory 030, a memory access information acquiring circuit 046 of a CME (common data coincidence device) 040 directly snoops the access information from a main memory bus 021 and transfers it to a transfer circuit comparing circuit 042. The comparing circuit 042 compares the address of the access information with a common area range (upper-limit register 044 and lower-limit register 055), and judges common data in case of writing to the common area 033 and sends it to a transmitting receiving circuit 143 of a stand-by system processor 110. A CME140 of the stand-by system when judging the common data from the address of the receive information by a coincidence bus 060 gains write access to the main memory 130 from a memory access circuit 146.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duplex system, and more particularly to a data sharing system between systems using a main memory.

[0002]

2. Description of the Related Art Conventionally, in addition to a main storage device of each processor, a storage device for shared data (hereinafter, GM: global memory) is provided in a system, and each processor is connected via an I / O bus. It was commonly used.

FIG. 11 shows the configuration of a conventional duplex system. The regular system is the I / O bus 064, and the regular system GM for shared data with the processor 010 having the main memory 030 built therein.
005 is connected, and the standby system is the I / O bus 164, and the processor 110 including the main memory 130 and the standby system GM1.
05 is connected, and shared data is matched between the regular system GM005 and the standby system GM105 via the matching bus 060. In this method, the size of the shared memory area is fixed.

[0004]

In the conventional data sharing method between the dual processors, the GM is required in addition to the main memory, which not only complicates the system configuration but also increases the storage capacity of each of the two storage devices. There is a problem in that the memory resources cannot be effectively used because a certain amount of extra space is required, which leads to an increase in cost. Of course, due to the failure of the GM, the processing of the entire system using the shared data is stopped.

Further, depending on the type of data, it is necessary to access the memory twice to store the data in both the main memory and the GM, which causes a problem that the processing time of the duplex system increases as compared with the single system. In particular, in a multiprocessor system, since GM is used via a common I / O bus, the access wait time of each processor increases as the amount of shared data increases, and the advantage of improving the processing performance by the multiprocessor is diminished. Resulting in.

Further, when building software by multi-tasking in each processor, it is necessary to allocate a shared data area used for each task to a predetermined area on the GM, which makes system development and modification more complicated. There was a problem.

In view of the above-mentioned problems of the prior art, it is an object of the present invention to provide a simple and high-duplex system which does not use a GM by handling shared data on a main memory.

Further, each task (job) of each processor
By freely and dynamically switching the shared data area for each task, when building software with a multi-task program, it is not necessary to allocate the shared area between tasks, making software development and modification easy. To provide a redundant system.

Further, it is another object of the present invention to provide a high-speed duplex system capable of parallel processing of communication between processors in a system and matching of shared data between systems in the case of a multiprocessor.
Another object of the present invention is to provide a highly reliable duplex system that enables matching processing by a bypass route by another processor in the system when the route between the systems is abnormal.

[0010]

The above object is to provide a shared data matching device (hereinafter referred to as CME) having an MPU and a main storage device connected by a main memory bus, and a transmission / reception circuit for transmitting / receiving shared information to / from a partner system. In the duplex system of the processor including the abbreviated name), the main storage device has a shared area for storing the shared data, and the CME provides access information including an address and data to be written from the MPU to the main storage device from the main memory bus. Memory access information acquisition means for snooping, memory access means for writing in the shared area when the received information from the partner system is the shared data, shared area setting means for designating the range of the shared area, the access information or the received information When the address inside is within the range of the shared area, the shared data that determines the information as shared data It is achieved by providing the monitoring means.

The CME transmits / receives data from its own processor.
It is characterized by having a transmission / reception state management means for switching the flow of information in the CME to the transmission side or the reception side according to the reception state. Further, a matching bus for connecting the processors of the own system and the partner system for transmitting and receiving the shared data is provided, and the matching processing can be performed in parallel with the processing of the MPU.

[0012] Further, the above-mentioned object is, when the main storage device stores multitasks, a shared area for each task that stores the shared data, a setting area for each shared area range,
The CME has a storage area for temporarily saving the shared area range of the certain task when another task is executed during execution of the certain task, and the CME manages the shared area range according to task switching. This is achieved by providing shared data monitoring means for determining the information as shared data when the access information or the address in the received information is within the shared area range.

Further, the above-mentioned object is, in a multiprocessor duplex system, having a shared area for storing the shared data in a main memory, and connecting the transmission / reception circuit between corresponding processors of the own system and the partner system. This is achieved by providing a corresponding matching bus and performing the shared data matching process in parallel with the communication between the processors in the system by the IO bus.

In the CME, the abnormality monitoring means for monitoring the response signal from the partner system via the matching bus, the transfer area setting means for designating the transfer area address of another processor, and the abnormality monitoring means for the bus abnormality. A bus I that outputs the transfer area address and the access information to the I / O bus interface when (no response) is detected.
It is characterized in that it is provided with F means and configured to transmit the shared data to the partner system through a bypass route passing through another processor in the system and its matching bus.

The transfer area address is set in the address range of the transfer data buffer provided in the CME of the other processor. Alternatively, it is set in the address range of the transfer area provided in the main memory of the other processor.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a duplex system and a multiprocessor duplex system according to the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 shows a schematic configuration of a duplex system according to the present embodiment. The standby system processor 010 is a standby system mainly via an MPU 020 that mainly performs data processing, memory control or input / output control, a main memory 030 that stores programs and data, a shared area 033 that stores shared data, and a matching bus 060. Processor 1
10 and a shared data matching device (CME: Common Memory Equlizer) 040 for matching shared data.

The MPU 020 and the main memory 030 are connected by a main memory bus 021 for memory access, and the CME 040 is connected to the main memory bus 021. In the CME 040, a memory access information acquisition circuit 0 that directly takes in access information from the processor 010 to the main memory from the main memory bus 021 by snooping.
41 and the shared data received from the regular system to the main memory 03.
Between the memory access circuit 046 for writing onto 0, the transfer range arbitrarily specified and the transfer range comparison circuit 042 for checking whether the address of the main memory access information is within the transfer range, and the standby processor 110. It is composed of a transmission / reception circuit 043 for transmitting / receiving shared data.

The transfer range comparison circuit 042 is a register for arbitrarily setting the shared area, and includes a shared area lower limit register 045 and a shared area upper limit register 044. Further, the transmission / reception circuit 043 has a transmission buffer 24.
4, a reception buffer 245 is provided. The hardware of the standby system processor 110 has the same configuration as the hardware of the regular system processor 010. The standby system / standby system is switched to the standby system by a well-known switching function when the standby system has an accident.

In this system, matching of shared data is performed as follows. FIG. 2 shows main memory maps of the normal system and the standby system. On the regular processor 010 side, the address range of the shared area 033 is designated in the shared area lower limit register 045 and the shared area upper limit register 044 at the time of initial startup.

When the MPU 020 accesses the main memory 030, the CME 040 transfers the main memory access information on the main memory bus 021 to the memory access information acquisition circuit 0.
If the address in the main memory access information is within the address range of the shared area 033 (here, the shared area 033 is set at addresses 500 to 1000 in the main memory) via 41, The access information is determined to be shared data. Then, the shared data including the address and the data is transferred to the transmission buffer 244 of the transmission / reception circuit 043 and transmitted to the standby processor 110 via the matching bus 060.

The operation of the standby system processor 110 side is similar to that of the normal system side, and the address range of the shared area 133 is set by the shared area lower limit register 145 and the shared area upper limit register 144 at the initial startup. Standby CME
140 receives from the regular system, transfers the address and data of the reception information stored in the reception buffer 345 to the transfer range comparison circuit 142, and checks whether the data is within the address range of the shared area 133. Within the address range of the shared area 133 (here, the shared area 133 is from address 500
1000 address), the data passes through the memory access circuit 146 and the main memory bus 121,
It is written in the shared area 133 of the main memory 130. As a result, the shared data matching (sharing) of the regular processor 010 and the standby processor 110 is completed.

As described above, the duplex system of the present embodiment has a function of snooping access information (address, data) to the main memory directly from the main memory, and a function of comparing with a preset shared data area and sharing. Each processor is equipped with a shared data matching device that has a function of transmitting only the data area to the partner system and a function of writing to the main memory of the host system when the information received from the partner system is the shared data area. Performs data matching between the main memory of the processor and the standby system processor. Hereinafter, the configuration and operation of this embodiment will be described in detail.

FIG. 3 shows the configuration of the shared data matching device (CME) according to the first embodiment. In the same figure, the regular CME040 is shown, but the standby CME140
The configuration of is also the same. The shared data matching function of the regular system and the standby system of the CME040 will be described below.

First, the operation when transmitting shared data will be described. In the regular system, the access information acquisition timing circuit 050 in the memory access information acquisition circuit 041 is
A timing signal is generated from the memory write signal 252 and the memory selection signal 253, and the memory signal 250 is fetched into the memory access information acquisition data register 241 and the memory address 251 is fetched into the memory access information acquisition address register 240 by the timing signal.

The address in the memory access information acquisition address register 240 is the shared area range comparison circuit 051.
And is compared with the addresses of the shared area upper limit register 044 and the shared area lower limit register 045. A plurality of shared area lower limit registers 045 and shared area upper limit registers 044 are provided, and the shared area 033 to be set is set.
It is possible to specify a plurality of address ranges as well as the address range of one location.

As a result, when it is determined that the address is within the shared area, the shared area range comparison circuit 051 sends a matching signal 256 to the transmission address buffer 008 and the transmission data buffer 009, and the memory access information acquisition address register 240 stores the same. The address 001 and the data 002 in the memory access information acquisition data register 241 are stored in the transmission address buffer 008 and the transmission data buffer 0, respectively.
Taken in 09.

Address 001 in the transmission address buffer 008 and data 002 in the transmission data buffer 009
Is transferred to the transmission buffer 244 and transmitted as the shared data 003 to the standby system by the timing signal generated by the timing circuit 049.

Next, the operation when receiving the shared data will be described. In the standby system, the received information is the transmission / reception circuit 04
When it is fetched into the reception buffer 245 in No. 3, the timing circuit 049 is activated, the state of the transmission / reception state management circuit 047 is switched to the reception system, and CME0
The signal direction within 40 is switched to the receiving side.

By the timing signal of the timing circuit 049, the address 001 and the data 0 of the reception buffer 245 are
02 is transferred to the reception address buffer 006 and the reception data buffer 007. Receive address buffer 006
The address 001 inside is transferred to the shared area range comparison circuit 051 and compared with the addresses of the shared area upper limit register 044 and the shared area lower limit register 045.

As a result, when it is determined that the address is within the shared area, the shared area range comparison circuit 051 causes the memory access data register 24 within the memory access circuit 046.
2 and a match signal 256 to the memory access address register 243 to send an address 001 in the reception address buffer 006 and a data 00 in the reception data buffer 007.
2 is the memory access address register 243
Are stored in the memory access data register 242.

The memory access right acquisition circuit 052 in the memory access circuit 046 issues a memory bus usage right request signal 254 to the MPU 020, and when receiving the memory bus usage permission signal 255 from the MPU 020, activates the memory bus interface 051. The memory write signal 252 and the memory selection signal 253 are transmitted to the main memory 030. Then, the address 001 in the memory access address register 243 and the memory access data register 2
The data 002 in 42 is transferred to the main memory 030 via the memory bus interface 051, and the matching of shared data ends.

As described above, in the duplex system of this embodiment,
When a common shared area is set in the main memory of each processor and the MPU of the regular system writes information to the main memory,
This information is snooped from the main memory bus and transferred to the standby system if the address is in the shared area. On the other hand, in the standby system, if the address of the received information is from the regular system to the main memory, it is transferred to the main memory. A shared data matching method for writing is realized.

According to this, it is not necessary to use the conventional GM, and the system configuration can be simplified and the cost can be reduced. Also, since the shared area can be set arbitrarily on the main memory, programming can be done freely without being aware of the difference between single and dual systems and the shared data area capacity.
Easier system development and modification. Although the present embodiment has been described by taking the example of the standby duplex system, it can be applied to the parallel duplex system.

[Second Embodiment] FIG. 4 shows the configuration of a duplex system using a multiprocessor according to the present embodiment.
The shared data matching device CME of each processor has the same configuration as that of the first embodiment.

The regular system of this multiprocessor duplex system has a basic processor (# 1) 010 and a plurality of extended processors (# 2) 011 and (# 3) 012, and an I / O bus 064 for performing interprocessor communication. Connected by. Each processor has a built-in main memory 030 having a shared area 033, and the standby system similarly has a basic processor (# 1) 110 and a plurality of extended processors (# 2) 111 and (# 3) 112. I / O bus 1
They are connected by 64.

The basic processor 010 of the standby system and the basic processor 110 of the standby system are connected by a matching bus A061 for transferring the shared data in the main memory 030 of the standby system to the main memory 130 of the standby system. Similarly, the extension processors 011 and 112 of the regular system and the extension processors 111 and 112 of the standby system respectively match the bus B06.
2. Connected by the matching bus C063. Each processor is equipped with an I / O bus IF090 (hatched block in the figure), and I / O bus 064 or I
It is connected to the / O bus 164 to transfer data.

Each processor has a matching bus A061 and a matching bus B06 which are provided separately between the regular system and the standby system.
2. The shared data matching process in the main memory 030 is performed asynchronously via the matching bus C063. Apart from this matching processing, inter-processor communication is processed in parallel on the I / O bus 064 between the processor 010 and the extended processor 011 or between the processor 010 and the extended processor 012 or between the extended processor 011 and the extended processor 012. it can. Similarly, the standby system can process inter-processor communication.

According to the multiprocessor duplex system according to the present embodiment, since the main memory of each processor has a shared area, common hardware for the entire system such as GM is unnecessary, and the system configuration is eliminated. The configuration and operation of is simplified, and the cost can be reduced. In addition to the I / O bus for performing inter-process communication, a matching bus for enabling matching of shared data with other systems is provided. The communication of the matching process can be performed in parallel, and the processability of the multiprocessor system can be secured.

[Third Embodiment] The multiprocessor duplex system according to the present embodiment has the same basic configuration as the system of the second embodiment. Here, a different route matching method will be described in which, when there is a failure in the route of the matching bus, matching is performed using another route.

FIG. 5 is an explanatory diagram showing matching by another route in the multiprocessor duplex system.
When an abnormality occurs in the matching bus A061 route connecting the regular processor 010 and the standby processor 110, the matching routes ~ shown in the figure are established.

FIG. 6 shows the structure of the CME in this embodiment. The CME of each processor is configured as follows based on the configuration of FIG. CM of processor 010
E040 is shared data 003 (address 001, address 001, between adjacent processors) via the I / O bus 064 in the system.
In order to bypass the data 002), the bus IF circuit 093
Further, a transfer buffer 036 for another processor is provided. Also, to set the transfer area for shared data to be transferred,
The transfer range comparison circuit 042 is provided with another processor transfer area upper limit register 095 and transfer area lower limit register 096. Although not shown, the expansion processor # 2,
The # 3 CME 040 is also provided with a transfer buffer 036 for buffering shared data of other processors and an upper and lower limit register.

In the normal shared data matching operation according to this configuration, the transmission / reception circuit 043 causes the transmission address buffer 008.
And the data in the transmission data buffer 009 are transmitted to the standby system via the matching bus 060, and when the abnormality monitoring unit 098 receives a response signal indicating normal reception from the standby system, the matching bus 060 is normal. To judge. The matching operation in this case is the same as that of the first or second embodiment. Next, when an abnormality occurs on the matching bus, the operation of each processor when performing matching using another route will be described in detail.

[Operation of the regular processor # 1] When an abnormality occurs in the matching bus A061, the standby processor 11
0 returns an abnormal reception response signal (no response at the time of disconnection failure) to the regular processor 010. Accordingly, the abnormality monitoring unit 09 of the transmitting / receiving circuit 043 in the CME of the regular processor 010.
8 detects an abnormality, the data 002 (AAA) in the transmission data buffer 009, the address 001 (address 500) in the transmission address buffer 008, and the bus IF circuit 093.
Transfer to

The bus IF circuit 093 is an I / O bus IF09.
With respect to 0, the extension processor 011 outputs the transfer destination area (here, the start address = 1000 address) by the other processor transfer area upper limit register 095 and the lower limit register 096 to the I / O bus IF 090, and further outputs the address 001 and the data. 002 is output. As a result, the shared area information data 002 and its address 001 are transferred from the transmission / reception unit 092 to the I / O bus IF090 of the expansion processor 011 via the I / O bus 064.

[Operation of the normal system expansion processor # 2] I /
The extended processor 011 which has received the address 001 and the data 002 in the transfer buffer 036 corresponding to the designated start address via the O bus IF 090 passes the transfer destination area to the transfer range comparison circuit 042, and the other processor transfer area. The area is set by the upper limit register 095 and the lower limit register 095 (set at addresses 1000 to 1200).

As a result, if the designated transfer destination area is within the set area, it is determined that the shared data is a shared data due to a detour from another processor, and the address 001 is sent to the transmission address buffer 008 and the data 002 is sent to the transmission data buffer 009. Transfer to. The contents of these buffers 008 and 009 are transferred together with the transfer destination area information to the transmission / reception circuit 043 of the standby extended processor 111 (# 2) via the matching bus B062.

[Operation of Standby System Expansion Processor # 2] The address 001 and data 002 from the normal system expansion processor 011 are in accordance with the transfer destination area information (address 1000).
Receive address buffer 006, receive data buffer 00
7 is stored. Then, in the transfer range comparison circuit 042,
Compare the transfer destination area information with the set shared area or the transfer area of another processor, and judge that it is the shared data due to the detour from another processor in the latter area range.
The data 002 and the address 001 are transferred to the bus IF circuit 093.

The processor selection unit 094 in the bus IF circuit 093 uses the other processor transfer area address (1000
The address) is converted into the address of address 001 (address 500) and output to the I / O bus IF090. Thereafter, the data 002 (AAA) is output to the I / O bus IF090 and transferred to the I / O bus IF090 of the standby system regular processor 110 via the I / O bus 164.

[Operation of Standby System Regular Processor # 1] Address information from the extended processor 111 = 500
Via the transceiver 092 in the I / O bus IF090,
The data information = AAA is written to the address 500 on the main memory 130, and the matching is completed.

According to this embodiment, the CM of each processor is
In E, there is provided a transfer storage buffer for storing shared information (address, data) transferred corresponding to another processor for matching, and when a failure occurs in the matching bus, the adjacent processor of its own system Since the shared data is transferred to the partner system by the detour route via the route and the shared data can be made coincident, the reliability of the system can be improved.

[Fourth Embodiment] In the third embodiment, the CME of each processor is provided with a storage buffer for transfer of shared data of another processor. On the other hand, in the multiprocessor system of this embodiment, the transfer area for the shared data of other processors is provided in the main memory of each processor. The configuration of the CME is the transfer buffer 03 for another processor.
The configuration is the same as that of FIG.

The configuration of the multiprocessor and the duplicated system configuration of the present embodiment are basically the same as those of the above-mentioned embodiment, and the matching method will be explained by using the example of another route shown in FIG. That is, when a failure or an abnormality occurs in the matching bus A061 connecting the regular processor 010 and the standby processor 110, when the processor 010 receives an abnormal reception response signal (no response at the time of disconnection failure) from the processor 110. Then, it is determined that the transfer is impossible due to the matching bus A061, and the matching processing is performed by the routes.

FIG. 8 shows a main memory map in this embodiment. A shared area 033 is allocated to addresses 500 to 1000 of the main memory 030 of the active processor 010 (# 1), and shared data = AAA at the address 500 in the figure.
Is stored. # 1 when the matching bus A061 fails
Extension processor 011 for substituting the matching processing of
The address transfer area 034 and the data transfer area 035 of # 1 are allocated to addresses 1000 to 1200 of the main memory 030 of (# 2).

The main memory 030 of the standby extended processor 111 (# 2) has the same mapping as the regular processor # 2, and the address transfer area 134 and the data transfer area 135 are assigned to addresses 1000 to 1200.
The main memory 030 of the standby processor 110 (# 1), which is the matching destination, has the same mapping as the regular processor # 1. The operation of this configuration will be described in detail below.

[Operation of the standby system processor # 1] When an abnormality occurs in the matching bus A061 and an abnormal reception response signal (no response at the time of disconnection failure) is received from the standby system processor 110, the standby system processor 010 is in the CME. Transmitter / receiver circuit 0
The abnormality monitoring unit 098 of 43 detects an abnormality and transfers the data 002 (= AAA) in the transmission data buffer 009 and the address 001 (= 500 address) in the transmission address buffer 008 to the bus IF circuit 093.

The bus IF circuit 093 is the extension processor 0.
11 other processor transfer area (upper limit register 0
95, lower limit register 096) area information (here,
The first address (1000) is the I / O bus IF090
To the I / O bus IF0 of address information = 500 address and data information = AAA which are shared data at the same time.
Output to 90. These pieces of information are transferred to the I / O bus IF090 of the expansion processor 011 via the I / O bus 064.

[Operation of the normal system extended processor # 2] Transfer destination area information (= 100 from the normal system processor 010)
Address 0), and the address information and data information of the shared data are taken into the transfer range comparison circuit 042 via the intra-CME bus IF circuit 093, where the transfer area by the other processor transfer area upper limit register 095 and lower limit register 095 is transferred. It is compared with a range (here, addresses 1000 to 1200) to check whether it is shared data. In the case of shared data, the address information is transferred to the transmission address buffer 008 and the data information is transferred to the transmission data buffer 009. After that, the contents of the buffers 008 and 009 are transmitted to the transmission / reception circuit 043 of the standby expansion processor 111 via the matching bus B062 as in the case of the third embodiment.

[Operation of Standby System Expansion Processor # 2] Address information (= 500 address) of another processor received from the normal system expansion processor 011 is stored in the reception address buffer 006, and data information (= AAA) is received data buffer 007. Once stored in the transfer range comparison circuit 04
Transfer area range (addresses 1000 to 1200) depending on 2
And whether the data is shared by another processor. In the case of shared data from another processor, the bus IF circuit 093
Transfer to

Processor selection unit 0 of bus IF circuit 093
94 is another processor transfer destination area (= 1000 address)
Is converted into an address 001 (= 500 address) and is output to the I / O bus IF090. After that, data 002
(= AAA) is output to the I / O bus IF090, and I / O
I of the standby system regular processor 110 via the bus 064
/ O bus IF090.

[Operation of Standby System Regular Processor # 1] The address 001 and the data 002 transferred from the expansion processor 111 are transmitted / received by the transmitting / receiving unit 09 of the I / O bus IF090.
The data is written as data = AAA at the address = 500 in the main memory 030 via 2 and the matching is completed.

According to the present embodiment, when an abnormality occurs in the matching bus route, the matching can be performed by another route, so that the reliability of the multiprocessor duplex system can be improved. In particular, since a part of the main memory is used as a transfer buffer of another route, the storage area of shared information (address, data) shared by other processors can be made variable.

In the above embodiment, when the shared data is made to match by the detour between the regular processor 010 and the standby processor 110, the regular extended processor 011 and the standby extended processor 111 are separated from other processors. The shared data can be directly transferred to the matching bus 060 and the I / O bus 064 without writing the shared data in the main memory. As a result, the memory writing time during the shared data matching process can be reduced, and the matching process can be speeded up.

[Embodiment 5] In this embodiment, a shared data matching method in a multitasking duplex system will be described. In the present embodiment, when tasks are switched, the shared area is variably set for each task. Figure 1 shows the hardware
To the same as the configuration of FIG.

FIG. 8 shows a main memory map of this embodiment. Each main memory 030 (130) has a task # 1 to task # 1.
The shared area 071 for task # 1 in which the area of # 3 is variable,
Shared area 073 for task # 2, shared area 075 for task # 3, and program storage area 072,0 for each task
74 and 076 and a task setting area 089 are provided.

The task setting area 089 sets the upper limit and lower limit of the address of the shared area for each task, and the shared address upper limit areas 081,083,085 and the shared address lower limit areas 082,084,086 and the previous activation at the time of task switching. It has pre-task save areas 087 and 088 for saving the shared address upper and lower limits of the assigned task. In the task setting area 089, the address range of the shared area of each task is designated at the initial startup.

FIG. 9 shows a flow of task switching operation. The task switching is processed by the task management function 099 of the OS. When the task # 2 is activated during the processing of the task # 1, the OS reads the shared address range of the task # 1 indicated by the upper limit register 044 and the lower limit register 045 of the CME, and saves the previous task area 087 on the main memory 030. , 088 (S1). Next, the OS sets the shared address range of task # 2 indicated by the shared upper limit area 083 and the lower limit area 084 of the main memory to the shared area upper limit register 044 and lower limit register 045 in the CME 040.
(S2).

FIG. 10 shows an example of the main memory map by task switching. In the same figure (a), when task # 1 is executed, 100 is stored in the task # 1 shared upper limit area 081, and 200 is stored in the lower limit area 082.
The shared area for use 071 is addresses 100 to 200 on the main memory. In the same figure (b), when the task # 2 is executed, the task # 2 shared area 073 has addresses 500 to 600 on the main memory.

Thereafter, the processing of task # 2 is started (S2). When the processing of task # 2 is completed, the OS writes back the address values in the previous task storage area upper limit 087 and the previous task storage area lower limit 088 to the shared area upper limit register 044 and lower limit register 045 of the CME 040 (S4), and the task The process of # 1 is restarted.

As described above, since the shared area upper limit register 044 and the lower limit register 045 can be dynamically rewritten at the time of task switching, it becomes possible to manage the shared data address for each task. The shared data matching operation by the CME after task switching is performed in the same manner as in the first embodiment.

According to this embodiment, since the shared area for each task can be dynamically variably set, it is not necessary to secure the shared area in consideration of the additional task, and the memory resources can be effectively used. Also, when designing the program,
Because you can program without being aware of other tasks,
Software development becomes easy.

[0072]

According to the duplex system of the present invention, the function of directly snooping the main memory bus to detect the data for accessing the shared data area on the main memory and transmitting it to the partner system to perform the matching process. Since each processor is provided in each processor, the conventional GM common to the system is not required, and there is an effect that effective use of memory resources and simplification of memory management are possible.

Further, since the shared data area on the main memory is arbitrarily designated and the data to access the shared area is centrally managed so as to be matched, the software can be developed without being aware of the shared data. .

According to the multitasking duplication system of the present invention, the shared area for each task on the main memory is dynamically switched at the same time when the tasks are switched. No need to allocate, which makes system development and modification easier.

According to the multiprocessor duplexing system of the present invention, a shared bus is provided between the systems in addition to the system common bus (I / O bus) to transfer the shared data. Even if the shared data transfer process is started and the shared data is increased by the multiprocessor, the matching process can be speeded up, and the processability of the multiprocessor can be maintained. Alternatively, it is possible to prevent a decrease in processing capacity in the duplex system as compared with the single system.

Further, when a predetermined matching bus route fails, it has a function of another route matching process through the adjacent processor and its matching bus, so that there is an effect that system reliability can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a duplex system according to a basic embodiment of the present invention.

FIG. 2 is a main memory map in the embodiment of FIG.

FIG. 3 is a shared data matching device (CM according to the first embodiment.
The block diagram of E).

FIG. 4 is a configuration diagram of a multiprocessor duplexing system according to a second embodiment.

FIG. 5 is an explanatory diagram of routes of another route matching method according to the third embodiment.

FIG. 6 is a CME of another route matching method according to the third embodiment.
FIG.

FIG. 7 is a main memory map according to the fourth embodiment.

FIG. 8 is a main memory map according to the fifth embodiment.

FIG. 9 is a flowchart of task switching according to the fifth embodiment.

FIG. 10 is a main memory map of an operation example according to the fifth embodiment.

FIG. 11 is a block diagram of a conventional duplex system using GM.

[Explanation of symbols]

001 ... address, 002 ... data, 003 ... shared data, 006 ... reception address buffer, 007 ... reception data buffer, 008 ... transmission address buffer, 009 ...
Transmission data buffer, 010 ... Regular processor, 01
1-012 ... normal system expansion processor, 020 ... MPU,
021 ... main memory bus, 030 ... main memory, 033 ... shared area, 036 ... transfer buffer for other processor, 04
0 ... CME, 041 ... Memory access information acquisition circuit, 0
42 ... Transfer range comparison circuit, 043 ... Transceiver circuit, 044
... shared area upper limit register, 045 ... shared area lower limit register, 046 ... memory access circuit, 047 ... transmission /
Reception state management circuit, 049 ... Timing circuit, 050 ...
Access information acquisition timing circuit, 051 ... Memory bus interface, 052 ... Memory access right acquisition circuit, 060 ... Normal system matching bus, 061 ... Normal system matching bus A, 062 ... Normal system matching bus B, 063 ... Normal system Matching bus C, 064 ... Regular system I / O bus, 070 ... Shared area, 071 ... Task # 1 shared area, 073 ...
Task # 2 shared area, 075 ... Task # 3 shared area, 081 ... Task # 1 shared area upper limit, 082 ... Task # 1 shared area lower limit, 083 ... Task # 3 shared area upper limit, 084 ... Task # 3 shared area Lower limit, 085 ...
Task # 3 shared area upper limit, 086 ... Task # 3 shared area lower limit, 087 ... Previous task storage area upper limit, 088 ...
Previous task save area lower limit, 089 ... task setting area,
090 ... I / O bus IF, 091 ... Other processor transfer area report register, 092 ... Transceiver, 093 ... Bus I
F circuit, 094 ... Processor selection unit, 095 ... Other processor transfer area upper limit register, 096 ... Other processor transfer area lower limit register, 097 ... Buffer control unit, 09
8 ... Abnormality monitoring section, 099 ... OS, 110 ... Standby system processor, 111, 112 ... Standby system extended processor, 120
... MPU, 121 ... Main memory bus, 130 ... Main memory,
133 ... Shared area, 134 ... Processor 010 address transfer area, 135 ... Processor 010 data transfer area, 136 ... Processor 010 transfer buffer,
137 ... Transfer buffer for processor 011, 138 ... Address buffer, 139 ... Data buffer, 140 ... C
ME, 141 ... Memory access information acquisition circuit, 142 ...
Transfer range comparison circuit, 143 ... Transceiver circuit, 144 ... Shared area upper limit register, 145 ... Shared area lower limit register, 146 ... Memory access circuit, 164 ... Normal system I /
O bus, 240 ... Memory access information acquisition address register, 241 ... Memory access information acquisition data register, 242 ... Memory access data register, 243 ...
Memory access address register, 244 ... Transmission buffer, 245 ... Reception buffer, 250 ... Memory data, 2
51 ... Memory address, 252 ... Memory write signal, 2
53 ... Memory selection signal, 254 ... Memory bus usage right request signal, 255 ... Memory bus usage permission signal, 255, 25
6 ... Matching signal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hisao Nagayama 5-2-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Process Computer Engineering Co., Ltd. (72) Inventor Kenichi Kurosawa 7-1, Omika-cho, Hitachi-shi, Ibaraki No. 1 Incorporated company Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Ryoichi Takamatsu 5-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture Incorporated company Hitachi Ltd. Omika Plant (72) Inventor Akihiro Ohashi Mika Oita, Ibaraki Prefecture 5-2-1 machi, Hitachi Ltd. Omika factory (72) Inventor Tadahiko Hashimoto 5-2-1 Omika-cho, Hitachi city, Ibaraki Hitachi Ltd. Omika factory (72) Inventor Koji Masui Ibaraki 2-5-1, Omika-cho, Hitachi-shi, Hitachi Inside the Omika factory of Hitachi, Ltd.

Claims (9)

[Claims] 1. A duplex system of a processor including an MPU and a main storage device connected by a main memory bus, and a shared data matching device (hereinafter, abbreviated as CME) having a transmission / reception circuit for transmitting / receiving shared information to / from a partner system. A main memory device has a shared area for storing the shared data, and the CME snoops access information including an address and data to be written from the MPU to the main memory device from a main memory bus. When the received information from the system is the shared data, the memory access means for writing in the shared area, the shared area setting means for designating the range of the shared area, the address in the access information or the received information is the range of the shared area. When it is inside, it has a shared data monitoring means for judging the information as shared data. Redundant system to be. 2. The CME according to claim 1, further comprising a transmission / reception state management means for switching a flow of information in the CME to a transmission side or a reception side according to a transmission / reception state of a processor of its own system. Redundant system characterized by. 3. The matching bus according to claim 1 or 2, wherein a matching bus for connecting the processors of the own system and the partner system is provided for transmitting / receiving the shared data, and the matching processing can be performed in parallel with the processing of the MPU. A duplex system characterized by the above. 4. A main memory device for storing a multitasking program, an MPU for executing the program while switching tasks, a main memory bus for connecting the main memory device and the MPU, and shared information with a partner system. In a duplex system of a processor including a shared data matching device (hereinafter abbreviated as CME) having a transmission / reception circuit, a main storage device has a shared area for each task that stores the shared data and a set area of each shared area range. , A storage area for temporarily saving the shared area range of the certain task when another task is executed during execution of the certain task, and the CME includes an address and data to be written from the MPU to the main storage device. Memory access information acquisition means for snooping access information from the main memory bus, information received from the partner system is the shared data. In the case of, the memory access means for writing to the shared area, the shared area range is managed according to task switching, and when the access information or the address in the received information is within the shared area range, the information is shared data. A duplex system characterized by having a shared data monitoring means for judging. 5. A multiprocessor for connecting a plurality of processors having an I / O bus interface with an MPU, a main memory, and an I / O bus (or a system bus), and a transmission / reception circuit for transmitting / receiving shared information to / from a partner system. In a multiprocessor duplex system including a shared data matching device (hereinafter, abbreviated as CME) in each processor, a main storage device has a shared area for storing the shared data, and is provided in a corresponding relationship between a self system and a partner system. A matching bus for connecting the transmission / reception circuit is provided between the processors, and the CME is configured so that the CME can perform shared data matching processing in parallel with inter-processor communication in the system by the IO bus. And a multiprocessor duplex system. 6. The CME according to claim 5, wherein the CME snoops access information including an address and data to be written from the MPU to the main storage device from the main memory bus, and the information received from the partner system is shared by the CME. In the case of data, memory access means for writing in the shared area, shared area setting means for designating the range of the shared area, and when the address in the access information or the received information is within the range of the shared area, the information is stored. A multiprocessor duplexing system having a shared data monitoring means for judging shared data. 7. The CME according to claim 6, wherein the CME includes an abnormality monitoring unit that monitors a response signal from the partner system via the matching bus, and a transfer area setting unit that specifies a transfer area address of another processor. When the abnormality monitoring means detects a bus abnormality (no response), it is provided with a bus IF means for outputting the transfer area address and the access information to the I / O bus interface, and makes them coincident with other processors in the system. A multiprocessor duplex system characterized by being configured to transmit shared data to a partner system via a bypass route via a bus. 8. The transfer area address according to claim 7, wherein the transfer area address is a CME of the other processor.
A multiprocessor duplication system characterized in that it is set within an address range of a transfer data buffer provided therein. 9. The dual processor system according to claim 7, wherein the transfer area address is set in an address range of a transfer area provided in a main memory of the other processor.