JPH04205233A - Abnormality diagnostic device for microprocessor - Google Patents

Abstract

PURPOSE:To easily analyze the cause of abnormality with use of another CPU or the like by holding the storing state of a storing means for periodically storing a bus state when receiving an abnormality holding signal so as to hold the state without fail in the case of abnormality. CONSTITUTION:When any abnormality is generated at a CPU 13, an abnormality detecting signal is turned to a low level state by the overflow of a counter circuit 20, and an abnormal state holding circuit 22 outputs a memory holding signal. The output of a memory suppressing circuit 24 is maintained in a high level state even when the normal write instructing signal of a bus 25 is turned to a state showing a recording instruction, and write and storage caused by a FIFO memory 16a for address and a FIFO memory 16b for data/status are suppressed. Thus, the FIFO memories 16a and 16b hold the bus state just before time when the abnormality is generated at the CPU 13, and by reading the contents of the FIFO memories 16a and 16b from the other CPU, the cause of the abnormality can be easily analyzed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a microprocessor abnormality diagnosis device used for monitoring and diagnosing abnormalities in a microprocessor.
In particular, the present invention relates to a microprocessor abnormality diagnosing device with improved abnormal state holding technology.

(Prior Art) Generally, a watchdog timer (hereinafter referred to as WDT) is used to monitor whether a CPU in a microprocessor is operating normally. This WDT
is a timer device that monitors the operating state of the CPU, and is usually composed of a counter circuit that can be reset by software.

FIG. 3 is a diagram showing the configuration of a conventional device for monitoring an abnormal state of a CPU. In the figure, 1 is a clock oscillator that generates a tarok signal, 2 is a counter circuit that constitutes the WDT, 3 is a CPU, 4 is a terminal count signal line that takes out the overflow of the counter circuit 2, and 5 is a peripheral circuit associated with the CPU 3. be.

Therefore, in the above device, the counter circuit 2 is
During normal operation, the CPU3 is connected via the I10 control line 6.
It is reset periodically to prevent overflow. On the other hand, when the CPU 3 operates abnormally due to runaway, etc., the reset signal from the CPU 3 is interrupted.
Counter circuit 2 goes into an overflow condition and generates a terminal count signal. As a result, CPU3 and CP
The U peripheral circuit 5 is reset upon receiving the terminal count signal, and the CPU 3 starts again.

(Problem to be Solved by the Invention) As mentioned above, since the CPU 3 restarts when an abnormality is detected in the WDT, it is not only difficult to investigate the cause of the abnormality, but also to determine whether the runaway is due to a software defect or a hardware abnormality. I can't even analyze whether it's a hang-up caused by something like this.

The present invention has been made in order to solve the above-mentioned problems, and provides a microprocessor abnormality diagnostic device that can reliably maintain the state at the time of an abnormality, and furthermore, can easily analyze the cause of the abnormality from other CPUs, etc. The purpose is to

[Configuration of the Invention (Means for Solving the Problems) In order to solve the above problems, a microprocessor abnormality diagnosis device according to the present invention includes one or more microprocessors, and detects abnormal operations of these microprocessors. In a microprocessor abnormality diagnostic device that diagnoses
an abnormality detection means for detecting an abnormal operation of the microprocessor; a storage means for storing a bus state of the microprocessor; and an abnormality holding means for holding the abnormal state detected by the abnormality detection means and outputting an abnormality holding signal; The apparatus further comprises a memory inhibiting means for suppressing a signal for periodically recording the bus state of the microprocessor to maintain the memory state of the memory means when an abnormality retaining signal is received from the abnormality retaining means.

(Function) Therefore, by taking the above-mentioned measures, the present invention regularly stores the bus state of the microprocessor in the storage means, but when the microprocessor becomes abnormal, , the abnormal state is detected by the abnormality detection means and sent to the abnormality holding means. This abnormality holding means holds the abnormal state and sends an abnormality holding signal to the storage inhibiting means. Here, upon receiving the abnormality holding signal, the storage inhibiting means operates to store the bus state of the microprocessor in the storage means.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In this embodiment, abnormal operation of the CPU in the microprocessor is monitored by the WDT, and addresses and data are collected as abnormality diagnosis information.

An example of recording each bus status will be described.

FIG. 1 is a block diagram showing an embodiment of the apparatus of the present invention.

A clock oscillator 11 generates a clock pulse serving as a reference signal for operation, and the generated lock pulse is sent via a clock signal line 12 to a CPU 13 and a counter circuit to be described later.

After performing predetermined data processing, the CPU 3 transfers the processed data to an address bus 14 and a data bus 15.
The signal is supplied to the address FIFO memory 16a, the data/status FIFO memory 16b, and the peripheral circuit 17 via the I10 control bus 18, and the counter circuit 20 reset signal is supplied via the I10 control bus 18.

This counter circuit 20 counts clock pulses inputted from the clock oscillator 11 as a reference signal, and when it receives a reset signal from the CPU 13, it initializes the contents of the counter and re-counts, but the reset signal from the CPU 13 disappears. CPU if overflow
Terminal signal bus 2 is determined to be an abnormal operation.
1 via the CPU 13. An abnormality detection signal is sent to the abnormal state holding circuit 22 and peripheral circuit 17.

This abnormal state holding circuit 22 is composed of, for example, 5R-F and F circuits, and is reset by inputting a power-on reset signal 23, and holds the abnormal state when an abnormality detection signal is inputted via the terminal signal bus 21. At the same time, a memory holding signal is sent to the memory inhibiting circuit 24.

This storage inhibiting circuit 24 is composed of, for example, a NAND circuit, and when a normal write instruction signal generated at the timing when the address, data, and status are determined is input via the normal write instruction signal bus 25, it is sent to the FIFO memories 16a and 16b. When a storage instruction signal is sent via the storage instruction signal bus 26 and a storage retention signal is received from the abnormal state retention circuit 22, the normal write instruction signal is suppressed and the FI
No storage instruction signal is output to the FO memories 16g and 16b. In other words, control is performed to maintain the abnormal state.

27 is FIFO memo 'J16a after an error occurs.

This is an abnormal state record read line for taking out address data and data/status state from 16b.

Next, the operation of the microprocessor abnormality diagnosis device configured as shown in FIG. 1 will be explained using FIG. 2.

First, when the power is turned on, the power-on reset signal 23 becomes a low level state P1 at time t] as shown in FIG. 2(b). As a result, the abnormal state holding circuit 22 is reset, and the memory holding signal becomes a low level state AO indicating memory holding as shown in FIG. 2(d).

Next, at time t2, as shown in FIG. 2(e), the normal write instruction signal on the bus 25 becomes
When the ABLE state Nl (state N is enabled) is reached, the recording instruction signal 2 of the low level state M1 is sent from the storage inhibiting circuit 24.
6 (see FIG. 2(f)) is output. As a result, FI
Addresses, data, and status are recorded in the FO memories 16a and 16b (see FIG. 2(g)).

Thereafter, immediately after normal writing X is performed at time t3 as shown in FIG.
If any abnormality occurs (see Figure 2 (a)),
An overflow of the counter circuit 20 causes an abnormality detection signal (
(see FIG. 2(c)) becomes a low level state T1 indicating the occurrence of an abnormality.

At this time, the abnormal state holding circuit 22 is in a low level state T1.
In response to this, it outputs a DISABLE state (high level state) AI indicating an abnormality, that is, a memory holding signal as shown in FIG. 2(d). As a result, even if the normal write instruction signal on the bus 25 reaches the state N2 indicating a recording instruction at time t5, the storage inhibit circuit 24 remains in the high level state M2 as shown in FIG. .

It operates to inhibit writing and storage by 16b. Therefore, writing to the FIFO memories 16a and 16b is no longer performed, and the memory retention signal remains in state A1 until the power-on reset signal (see FIG. 2(b)) goes to low level state P2 at time t6. Retained.

Therefore, the FIFO memories 16a and 16b hold the state X at time t3 immediately before time t4 when an abnormality occurred in the CPU.

As a result, the FjFO memory 16a, 16 is accessed from other CPUs.
By reading the contents of b, it becomes possible to easily analyze the cause of the abnormality. In addition, the LED indicates the occurrence of a WDT error.
It is conceivable to give an instruction to the operator by using the CPU, or to contact other CPUs by an interrupt operation.

Note that when the power is turned on again at time t6, the power-on reset signal (see FIG. 2(b)) becomes a low level state P2, and recording S to the FIFO memories 16a and 16b is restarted (see FIG. 2(b)). (see (g)).

Therefore, according to the configuration of the embodiment as described above, the CPU 1B is monitored by the counter circuit 20, and when an abnormality is detected, the abnormal state is held by the abnormal state holding circuit 22, and an abnormality holding signal is outputted, so that the memory suppression circuit 24, even if a normal write instruction signal is generated, the output of the status recording instruction signal is suppressed, and the address and data before the abnormal condition occurs.

The status can be held in the FIFO memories 16g and 16b. Then, this FIFO memory 16a, 16
By investigating the contents of b, it is possible to analyze the cause of the abnormality, to infer a software bug, and to detect a hang-up due to a hardware abnormality. Here, the normal write instruction signal 25 is generated at the timing when the address, data, and status are determined, or the overflow time of the counter circuit 20 is set shorter than this timing interval, so that the normal write instruction signal 25 is sent. The abnormal state holding circuit 22 operates to ensure that the address, data, and status before the occurrence of the abnormal state are stored in the FIFO memory 16a.
, 16b.

Note that the present invention is not limited to the above embodiments.

For example, although the CPU is monitored in this embodiment, input/output devices may also be monitored. Furthermore, although data on the address line, data line, and status line are collected as the CPU status, if there are other signals necessary for error detection depending on the system, they may be added.

In addition, by cascading the FIFO memories 16a and 16b shown in FIG. 1 into a multi-stage configuration, it is possible to store not only the previous state of the CPU 13 but also the history up to the occurrence of an abnormality. Analysis becomes possible.

Further, the occurrence of a failure may be indicated to the operator using an LED or the like, or an interrupt operation may be used to notify another CPU to analyze the failure.

Furthermore, the FIFO memory 16a is sent from another CPU.

There is also a configuration in which the logic for reading 16b is read from the own CPU 13. For example, when a failure occurs and a reset signal from the counter circuit 2o is input to the CPU 13, the CPU 13 performs failure analysis processing by using the FIFO
It is possible to read the fault information from the memories 16a and 16b and record it in a fault recording file, or to analyze the details of the fault and print out the diagnostic results on a printer.

In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As explained above, according to the present invention, it is possible to provide a microprocessor abnormality diagnosis device that can reliably maintain the state at the time of an abnormality and that can easily analyze the cause of the abnormality using another CPU or the like. .

[Brief explanation of the drawing]

FIGS. 1 and 2 are shown to explain the present invention in detail. FIG. 1 is a block diagram showing an embodiment of the device of the present invention, and FIG. 2 explains the operation of the device of the present invention. Timing chart FIG. 3 is a configuration diagram of a conventional device. 11... Clock oscillator, 13... CPU. 16a... FIFO memory for address, 16b...
FIFO memory for data and status, 18...I1
0 control line, 20... counter circuit, 21...
・Terminal signal bus, 22...abnormal state holding circuit,
23... Power-on reset signal, 24... Memory inhibit circuit, 25... Normal write instruction signal bus, 26...
...Storage instruction signal bus, 27...Abnormal state record reading 8
Line. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] A microprocessor abnormality diagnosis device having one or more microprocessors and diagnosing abnormal operations of these microprocessors, comprising an abnormality detection means for detecting abnormal operations of the microprocessors; a storage means for storing a bus state; an abnormality holding means for holding an abnormal state detected by the abnormality detecting means and outputting an abnormality holding signal; 1. An abnormality diagnosis device for a microprocessor, comprising: storage inhibiting means for suppressing a signal for periodically recording a bus state to maintain the storage state of the storage means.