JPH02245941A - Address inspection device - Google Patents

Abstract

PURPOSE:To improve the reliability of a microprocessor by adding a simple inspecting circuit outside the microprocessor and detecting the trouble of the address output of the microprocessor speedily. CONSTITUTION:The microprocessor 1 outputs an address which increases, one by one, from its address bus as long as its operation is normal except during the fetching of a jump instruction, an interruption acknowledge cycle, and resetting. An address comparison part 2 compares the address of a last cycle with a current address under conditions where a function code indicates a program fetch so that the address output is normal when the both match each other and abnormal when not. Thus, the trouble of the address output or address bus is securely detected to stop the operation of the microprocessor immediately. Consequently, the reliability of the operation of the microprocessor 1 can be improved.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an inspection device for inspecting a card equipped with a microprocessor for failure, and more specifically, for inspecting a failure in the address output or address bus of a microprocessor. The present invention relates to an address failure detection device.

<Conventional technology> A microprocessor uses a data bus to access memory and various types of data. 10 and handles various tasks such as control and calculation. In a processor card equipped with such a microprocessor, a parity bit or the like is often added and checked in order to detect failures in the memory or data bus.

As a result, not only memory failures but also failures in the data bus driver/receiver, registers, etc. can be detected. Furthermore, since a parity bit is not added to the data output section of the microprocessor, it is not possible to easily test the hardware, but it is possible to test the data by reading back the data written to a specific address and comparing and verifying it. It is.

On the other hand, regarding the address output of the microprocessor,
Unless program memory is included, the program execution itself will malfunction immediately in the event of a failure, resulting in bus errors when accessing unresponsive areas, watchdog timer time-ups, etc. Failures can be detected.

<Problems to be Solved by the Invention> However, a problem with a malfunction in the address output of a microprocessor is that there is a high risk of outputting erroneous data to the outside due to malfunction until the malfunction is detected.

The present invention has been made in view of these points, and
The purpose of this invention is to quickly detect failures in the address output of a microprocessor by adding a simple test circuit to the outside of the microprocessor, thereby increasing the reliability of the microprocessor.

Means for Solving the Problems> The present invention solves the above problems by using a microprocessor that does not include a program memory inside and outputs a code indicating at least the operating state of program fetch or something else.・This is a failure detection device for the address output in SOSA, and when the code indicating the operating status from the microprocessor indicates a program fetch, it compares the address of the previous cycle and the address of the current cycle, and detects if the address is incremented by one. There is an address comparator that outputs a signal that indicates normality when the error is present, and an error signal otherwise, and detects when the microprocessor is fetching a jump instruction, executing an interrupt acknowledge cycle, or resetting, and then masks the output of the address comparator for a certain period of time. It is configured by providing a mask function section to

Function> If the microprocessor is operating normally, except for fetching jump instructions, executing interrupt acknowledge cycles, and during reset, the microprocessor will sequentially receive one message from the address bus.
It outputs an address that increases by increments.

The address comparison unit compares the address of the previous cycle with the current address under the condition that the function code indicates program fetch, and if they match, the address output is determined to be normal, and if they do not match, it is determined to be abnormal.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a microprocessor that outputs at least a code (function code) FC that indicates the operating status of program fetch or something else, and it is assumed that no program memory is included inside. .

2 is a code indicating the operating status from microprocessor 1. When FC indicates a program fetch, the address of the previous cycle is compared with the address of the current cycle, and if it increases by one, it is normal, otherwise it is an error. This is an address comparator section that outputs a signal ADERR indicating the address.

3 is the fetch of the jump instruction of microprocessor 1,
This is a mask function section that detects execution of an interrupt acknowledge cycle and during reset, and then masks the output of the address comparison section 2 for a certain period of time.

Reference numeral 4 denotes a memory and memory access timing control unit coupled to the microprocessor 1 via an address bus AB and a data bus DB.

The address comparator 2 inputs the address signal A1 from the microprocessor 1 and the function code FC indicating the operating state of the microprocessor, and also inputs the address signal A1 from the microprocessor 1 to obtain the latch timing of the address signal.
The address strobe in the control signal CTLSIG is manually controlled. Further, the address error signal ADERR output from this is applied to the HALT terminal of the microprocessor 1 in this example, and the configuration is such that the operation of the microprocessor 1 is immediately stopped when an error occurs.

The mask function unit 3 uses the function code FC from the microprocessor 1, the data signal, and the data strobe DS, data trans acknowledge DTAC, and read in the control signals in order to obtain the timing to latch the data from the memory 4 when fetching the instruction. /write signal is input, and in addition to these, the signal IACK indicating the interrupt acknowledge cycle and the reset signal RESET are input, and the mask signal from this is input to the address comparator 2.
It is output to. This mask function unit 3 detects the fetching of a jump instruction, the execution of an interrupt acknowledge cycle, and the resetting in the microprocessor 1, and is configured to make the mask signal active (low level) for a certain period of time after detecting these. ing.

FIG. 2 is a block diagram showing an example of the internal configuration of the address comparator 2 in FIG. 1.

In this figure, 21 is an n-bit register that holds address signal A from microprocessor 1, 22 is an n-bit counter that adds 1 to the address signal held in n-bit register 21 and holds this, and 23 is register 2.
a coincidence determination means for determining coincidence between the current address signal from 1 and the address signal held in the counter 22;
24 is a flip-flop that holds the judgment result from the coincidence judgment means 23.

Note that 25 and 26 are delay circuits for delaying the address strobe AS for a certain period of time.

The operation of the circuit configured in this way will be explained as follows.

Address signal A from microprocessor 1 is applied to memory 4 and address comparator 2 via an address bus. In the address comparator 2, the register 21 latches the address signal A at the edge where the address strobe AS becomes active when the function code FC indicates an instruction fetch. Here, the address of the previous cycle latched last time is loaded into the counter 22 while the address strobe AS is inactive, and counts up at a constant timing from the time the address strobe becomes active.

The coincidence determining means 23 then compares the output of the counter 22 with the address latched in the register 21, and latches the result in the flip-flop 24 using the delay signal of the address strobe AS. Here, when a mismatch is detected, the flip-flop 24 is set and makes the address error signal ADERR active. The flip-flop 24 is reset when the mask signal (low active) output from the mask function section 3 becomes low level.

On the other hand, the mask function unit 3 monitors the status of each signal input thereto, and (a) intercepts the data read from the program memory when the function code FC indicates an instruction fetch and sends a data transfer acknowledge signal. At the edge where rigid DATCK becomes active, it is captured internally (data strobe DS is active).

(b) A signal indicating an interrupt acknowledge cycle from microprocessor 1. Detects that IACK becomes active (knows that it is an interrupt acknowledge cycle)
(C) When it is detected that the reset signal REST changes from active to inactive, the mask signal is set to low level (active) for a certain period of time.

Except for the cases (a) to (C) mentioned above, the microprocessor 1 outputs an address signal that increases by 1 during normal operation, and if the address output is normal, the address comparator 2 The two signals applied to the coincidence determining means 23 match.

On the other hand, if a failure occurs in the address output or the address bus, the regular operation will be disrupted, so the two signals applied to the coincidence determination means 23 will be different, and these failures will not be detected. Ru. As a result, an address error signal is applied to the microprocessor 1,
The operation of the microprocessor 1 can be stopped immediately.

<Effects of the Invention> If the address output or address bus fails, the operation of the microprocessor will be in a completely unpredictable and dangerous state.

According to the present invention, it is possible to reliably detect a failure in the address output or the address bus and immediately stop the operation of the microprocessor, thereby significantly improving the reliability of the operation of the microprocessor.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing one embodiment of the present invention, and FIG.
This figure is a block diagram showing an example of the internal configuration of the address comparison section in FIG. 1. 1...Microprocessor 2...Address comparison section 3...Mask function section 4.
・・Memory and timing control section diagram

Claims (1)

[Claims] A failure detection device for address output in a microprocessor that does not include a program memory and outputs a code indicating at least the operating status of program fetch or other operation, the device comprising: When the code indicating the operating status of indicates a program fetch,
An address comparison section that compares the address of the previous cycle with the address of the current cycle, and outputs a signal indicating that it is normal if it has increased by one, otherwise an error, and fetches the microprocessor's jump instruction and acknowledges the interrupt. An address inspection device comprising: a mask function section that detects when a cycle is being executed or during a reset, and then masks the output of the address comparison section for a certain period of time.