JP2016059792A - Control device for game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a fraudulent command from being executed in a memory chip supporting a serial interface without delaying the execution of a normal command in a control device for a game machine.SOLUTION: A fraudulent command detection circuit 38 is provided which is connected in parallel to a serial signal line 36c and monitors a command input to a memory chip 33. When a fraudulent command is input to the memory chip 33, a bit pattern included in the fraudulent command is detected by the fraudulent command detection circuit 38, and a prescribed terminal of the memory chip 33 is controlled by a latch circuit until a prescribed trigger occurs. Thus the memory chip is disabled so as to prevent an execution of the fraudulent command in the memory chip 33.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a technique for preventing information alteration of a memory chip provided in a control device for gaming machines.

  A control device used in a gaming machine such as a slot machine or a pachinko machine is provided with a nonvolatile memory chip in which information related to game control such as a program and a lottery table is stored. Such memory chips can be remodeled into gaming machines that are advantageous to the player by modifying the stored information. From the viewpoint of fraud prevention, mask ROM and OTP that cannot rewrite information, EPROM that cannot be electrically rewritten, etc. Has been used. However, in recent years, flash memories that can be electrically rewritten have been adopted for such memory chips (for example, Patent Document 1). Here, in the gaming machine control device adopting the flash memory, the input voltage level of the write protection terminal for switching the flash memory between the rewritable state and the non-rewritable state is changed to the non-rewritable state as in Patent Document 1. By constantly controlling the voltage level to a certain level, alteration of stored information in the flash memory is prevented.

  Further, in Patent Document 2, when an invalid command is input from a memory writer, which is arranged between the memory writer and the nonvolatile memory, the command is replaced with another command and transmitted to the nonvolatile memory. Thus, an unauthorized access restriction circuit that prevents the command from being transmitted to the nonvolatile memory has been proposed.

JP 2002-35361 A JP2002-11206

  Incidentally, in a conventional gaming machine control device, a parallel flash memory connected via a parallel interface is adopted as a memory chip, but a serial flash memory connected via a serial interface is not adopted. This is because the memory chip of the serial flash memory does not have a terminal corresponding to the above-mentioned write protection terminal, and the existing method cannot protect the stored information of the serial flash memory.

  As in Patent Document 2, by determining whether or not to pass an input command to the memory chip upstream of the memory chip, a command that modifies the storage information of the memory chip is prevented from being transmitted to the memory chip. However, when such a configuration is adopted for a serial interface, normal commands are also input to the memory chip only after the correctness is determined, so that normal command execution in the memory chip is delayed. End up. In addition, since the memory control device and the memory chip are difficult to synchronize, complicated timing control is required.

  The present invention has been made in view of the present situation, and it is possible to prevent an illegal command from being executed in a memory chip without delaying the execution of a normal command for a memory chip that supports a serial interface. An object is to provide a control device for a gaming machine.

  The present invention relates to a nonvolatile memory chip controlled by a command, a memory control device that outputs the command to the memory chip, and a serial signal that transmits the command from the memory control device to the memory chip by a serial transmission method. The memory chip can be switched to an inactive state in which the input of the command is invalidated by controlling a predetermined terminal, and is the same as the memory chip. The command is input in parallel to the serial signal line so that the command is input at a clock timing of the command, and the command input to the memory chip is monitored. The illegal command is input to the memory chip via the serial signal line. A first illegal command detection circuit that detects a bit pattern included in the illegal command and outputs a detection signal, and when the first illegal command detection circuit outputs a detection signal, the memory chip is A first memory state switching circuit for switching to the inactive state, and the first memory state switching circuit receives a predetermined trigger when the detection signal is input from the first illegal command detection circuit. Until now, there is provided a latch circuit for maintaining the inactive state of the memory chip.

In such a configuration, when an illegal command is detected, the memory chip becomes inactive and becomes inoperable until a predetermined trigger occurs, such as when a reset signal is input. It can be surely protected. On the other hand, in the present invention, since the first illegal command detection circuit is connected in parallel to the serial signal line and the input command of the memory chip is monitored, command transmission from the memory control device to the memory chip is not delayed. Therefore, according to the present invention, it is possible to reliably prevent an illegal command from being executed in the memory chip without delaying command execution in the memory chip.
Further, in this configuration, when an illegal command is input to the memory chip, the first illegal command detection circuit detects this before all the illegal command is input to the memory chip, and If one memory state switching circuit is configured to switch the memory chip to an inactive state, it is possible to more reliably prevent an illegal command from being executed in the memory chip.

  As another aspect of the present invention, a non-volatile memory chip controlled by a command, a memory control device that outputs the command to the memory chip, and a serial transmission method from the memory control device to the memory chip A serial interface including a serial signal line for transmitting a command, and the memory chip can be switched to an inexecutable state in which the command cannot be executed by controlling a predetermined terminal. The command input to the memory chip is monitored by being connected in parallel to the serial signal line so that the command is input at the same clock timing as the memory chip, and a predetermined type of command among the commands is monitored. As an illegal command, the illegal command is sent before the serial signal line. When input to the memory chip, a second illegal command detection circuit that detects a bit pattern included in the illegal command and outputs a detection signal; and when the second illegal command detection circuit outputs a detection signal, A second memory state switching circuit for switching the memory chip to the non-executable state, and the second memory state switching circuit is configured to receive a predetermined signal when the detection signal is input from the second illegal command detection circuit. There is also proposed a control device for a gaming machine comprising a latch circuit that maintains an inexecutable state of the memory chip until an opportunity arises.

In such a configuration, when an illegal command is detected, the memory chip becomes inoperable and inoperable until a predetermined trigger occurs, such as when a reset signal is input. It can be surely protected. Even in such a configuration, since the second illegal command detection circuit connected in parallel to the serial signal line monitors the input command of the memory chip, command transmission from the memory control device to the memory chip is not delayed.
In this configuration, when an illegal command is input to the memory chip, the second illegal command detection circuit detects this before the illegal command is executed on the memory chip, and the second If the memory state switching circuit is configured to switch the memory chip to an inexecutable state, it is possible to reliably prevent an illegal command from being executed in the memory chip. In particular, in such a configuration, even if the final bit of the illegal command is input, if the delay time is long after the last bit of the command is input to the memory chip until the memory chip executes the command, the Since it is possible to prevent the execution of an illegal command, there is an advantage that an illegal command and a normal command can be accurately distinguished by including the final bit of the illegal command in the bit pattern for detecting the illegal command.

  In the present invention, the first illegal command detection circuit or the second illegal command detection circuit is a bit that outputs the detection signal when a predetermined bit pattern is input via the serial signal line. A pattern detection circuit detects the timing at which the command is input to the memory chip, enables the bit pattern detection circuit at the timing at which a bit at a predetermined position of the command is input, and the bit at the predetermined position It is proposed to include a counter circuit that invalidates the bit pattern detection circuit other than the input timing.

  According to such a configuration, the target for the bit pattern detection circuit to detect the predetermined bit pattern can be limited to only a specific position of the command (for example, a predetermined 4-bit pattern of 1 to 7 bits). Commands can be more easily distinguished.

  Further, in the above configuration, the counter circuit is configured to detect a timing at which the command is input to the memory chip based on a chip select signal and a clock signal input to the memory chip. Is proposed. According to this configuration, the counter circuit can be realized with a simple circuit configuration.

  In the present invention, the bit pattern detection circuit includes a shift register that converts a serial signal input to the memory chip via the serial signal line into a parallel signal, and a parallel signal converted by the shift register. And a comparator that determines whether or not is a predetermined bit pattern, and outputs the detection signal when it is determined that the comparator has the predetermined bit pattern.

  With such a configuration, it is possible to detect a bit pattern of an illegal command transmitted via a serial signal line in a very short time with a simple circuit configuration. For this reason, regarding the first illegal command detection circuit, when a specific bit pattern included in the illegal command is input to the memory chip, the specific bit pattern is immediately detected and the next of the specific bit pattern is detected. It is possible to switch the memory chip to the inactive state by the first memory state switching circuit before the bits are input to the memory chip. With a simple circuit configuration, all bit patterns other than the last bit of the illegal command can be displayed. As a detection target of the first illegal command detection circuit, the first illegal command detection circuit can accurately distinguish an illegal command from a normal command. Further, regarding the second illegal command detection circuit, even if the delay time until the memory chip executes the input command is relatively short, the bit pattern including the final bit of the illegal command may be detected. It becomes possible.

  Further, in the present invention, a connector connectable to a gaming machine control device body, the memory chip, the first illegal command detection circuit, and the first memory state switching circuit are provided on a substrate. It is proposed to have a memory device arranged. Also, a memory comprising a connector that can be connected to the gaming machine control device body, the memory chip, the second illegal command detection circuit, and the second memory state switching circuit on a substrate. It is also proposed to have a device.

  In such a configuration, since the memory chip, the illegal command detection circuit, and the memory state switching circuit are realized as one memory device, only the memory device of the existing gaming machine control device is replaced with the memory device. Thus, the gaming machine control device of the present invention can be realized at low cost.

  Further, in the present invention, the memory device has a switching effective state in which the first memory state switching circuit can switch the memory chip to the inactive state according to an input voltage level of a predetermined write permission terminal. And the first memory state switching circuit is configured to change the memory chip to a switching invalid state in which the memory chip cannot be switched to the inactive state, and the write permission terminal connects the memory device to the game It is proposed that the memory device is controlled to a voltage level at which the switching is enabled in a state where the memory device is mounted on the machine control device body. The memory device has a switching valid state in which the second memory state switching circuit can switch the memory chip to the inexecutable state according to an input voltage level of a predetermined write permission terminal, and the second memory state switching circuit. The memory state switching circuit is configured to be able to change the memory chip to a switching invalid state in which the memory chip cannot be switched to the inexecutable state, and the write permission terminal connects the memory device to the gaming machine controller main body. It is also proposed that in the mounted state, the memory device is controlled to a voltage level at which the switching is enabled.

  In such a configuration, the storage information of the memory chip can be reliably protected in a state where the memory device is disposed in the control device for gaming machines. On the other hand, if the memory device is attached to the memory writer and the write permission terminal is controlled to a voltage level at which switching is disabled, the stored information can be written to the memory chip. Therefore, according to this configuration, by removing the memory device from the used gaming machine control device and writing new storage information to the memory chip with the memory writer, the memory device is connected to another gaming machine control device. Can be reused.

  As described above, according to the present invention, it is possible to reliably prevent the stored information of the memory chip from being altered by an illegal command without delaying the command transmitted from the memory control device to the memory chip.

FIG. 3 is a perspective view of the slot machine 1 according to the first embodiment. FIG. 3 is a perspective view of the slot machine 1 with a front door 3 opened. 3 is a block diagram showing a control circuit of the slot machine 1. FIG. 3 is a block diagram showing a configuration of a sub control device 21. FIG. 3 is a perspective view of a sub control device 21. FIG. 3 is a circuit diagram of a serial interface 36 and the like according to Embodiment 1. FIG. 4 is a chart showing commands of a control ROM chip 33. 4 is a timing chart showing a reading procedure and a writing procedure of stored information in a control ROM chip 33. 3 is a circuit diagram of an illegal command detection circuit according to the first embodiment. FIG. 3 is a circuit diagram of a memory state switching circuit 39 according to Embodiment 1. FIG. 6 is a timing chart illustrating an operation when a write permission command is input to the control ROM chip 33 according to the first embodiment. 6 is a timing chart illustrating an operation when a read command is input to the control ROM chip 33 according to the first embodiment. 6 is a circuit diagram of a serial interface 36 and the like according to Embodiment 2. FIG. 6 is a circuit diagram of an illegal command detection circuit 38a according to Embodiment 2. FIG. FIG. 6 is a circuit diagram of a memory state switching circuit 39a according to a second embodiment. 11 is a timing chart illustrating an operation when a write permission command is input to the control ROM chip 33 in the second embodiment.

An embodiment of the present invention will be described by way of an example in which the present invention is applied to a control device for a slot machine.
In the following embodiments, the gaming machine control device of the present invention corresponds to the sub-control device 21, and the gaming machine control device body corresponds to the sub-control device body 40. The memory chip according to the present invention corresponds to the control ROM chip 33, and the memory control device corresponds to the CPU 30. The serial signal line according to the present invention corresponds to the serial signal input line 36 c of the serial interface 36. The first illegal command detection circuit and the first memory state switching circuit according to the present invention correspond to the illegal command detection circuit 38 and the memory state switching circuit 39 according to the first embodiment, respectively. The second illegal command detection circuit and the second memory state switching circuit according to the present invention correspond to the illegal command detection circuit 38a and the memory state switching circuit 39a according to the second embodiment, respectively. The predetermined illegal command detected by the first illegal command detection circuit and the second illegal command detection circuit according to the present invention corresponds to a write permission command. The inactive state of the memory chip according to the present invention corresponds to the non-selected state of the control ROM chip 33, and the first memory state switching circuit according to the present invention causes the memory chip to be inactive. The predetermined terminal to be controlled corresponds to the / CS terminal of the control ROM chip 33. Further, the non-executable state of the memory chip according to the present invention corresponds to the power-off state of the control ROM chip 33, and the second memory state switching circuit according to the present invention makes the memory chip non-executable. The predetermined terminal to be controlled corresponds to the VCC terminal of the control ROM chip 33.

  As shown in FIGS. 1 and 2, the housing 2 of the slot machine 1 is opened forward and is covered by the front door 3 from the front. A visual recognition window 4 for visually recognizing three reels 9 disposed inside the housing 2 is provided at the center of the front door 3. On the front side of the front door 3, various switches such as bet switches 5 a and 5 b, a start switch 6, a stop switch 7, a settlement switch 8, and an effect button unit 13 are arranged below the viewing window 4. Established. Further, an image display 10 for displaying an effect image is disposed above the viewing window 4. The image display 10 is composed of a liquid crystal display device, and is fitted into the upper part of the front door 3. A plurality of effect lamps 12 are disposed on the front side of the front door 3.

  As shown in FIG. 2, on the back side of the front door 3, an image control device 22 that controls the image display 10 is disposed on the back side of the image display 10. Further, a speaker 11, a medal selector 16, and the like are disposed on the back side of the front door 3. As shown in FIG. 2, the casing 2 is installed above the reel 9 with the main control device 20 and the sub control device 21 housed in a case, and below the reel 9, A power supply box 18 and a hopper unit 19 are disposed.

  Next, the control circuit of the slot machine 1 will be described with reference to FIG.

As shown in FIG. 3, the slot machine 1 includes three control devices: a main control device 20, a sub control device 21, and an image control device 22.
The main control device 20 includes a CPU, a RAM, a ROM, and the like, and performs control related to the progress of the game. The power supply box 18, the bet switches 5 a and 5 b, the start switch 6, the stop switch 7, and the settlement switch 8 are connected to the input port of the main controller 20. Further, the reel 9, the hopper unit 19, and the sub control device 21 are connected to the output port of the main control device 20.

  The sub-control device 21 includes a CPU, a RAM, a ROM, and the like, and controls effects related to games. The ROM of the sub-control device 21 stores a control program, various lottery data, fixed data related to a wide variety of effect patterns, and the like. The main control device 20 and the effect button unit 13 are connected to the input port of the sub control device 21. The sub control device 21 is based on information input from the main control device 20, a signal from the effect button unit 13, or the like. In order to select an effect pattern, to execute the selected effect pattern, a control signal is transmitted to the effect lamp 12 and the speaker 11, and further, an image control device is used to display a required image on the image display 10. A control signal is transmitted to 22.

  The image control device 22 includes a CPU, a RAM, a ROM, and the like, and performs display control of the image display device 10. A large amount of data for generating an effect image to be displayed on the image display 10 is stored in the ROM of the image control device 22. When receiving the control signal from the sub-control device 21, the image control device 22 performs arithmetic processing in the CPU, writes the data for the effect image in the RAM and outputs it to the image display 10, and the effect selected by the sub-control device 21. The effect image according to the pattern is displayed on the display screen of the image display 10.

  The sub-control device 21 will be described in detail. As shown in FIG. 4, the sub-control device 21 includes a CPU 30, a RAM chip 32 that constitutes a RAM, and two ROM chips 33 and 34 that constitute a ROM. . Here, one of the two ROMs 33 and 34 is a control ROM chip 33 in which a control program and lottery data are stored, and the other is an effect ROM chip 34 in which an effect pattern using images and sounds is stored. It is. The CPU 30 is interconnected with the RAM chip 32 and the ROM chips 33 and 34 via the interfaces 35 and 36, and outputs a command to each of the chips 32 to 34, reads data, etc. Perform production control and the like. Here, the CPU 30 is a general-purpose product corresponding to each of the parallel interface 35 and the serial interface 36. The RAM chip 32 and the effect ROM chip 34 are connected to the CPU 30 via the parallel interface 35, and the control ROM chip 33 is The CPU 30 is connected via the serial interface 36. Further, as shown in FIG. 4, the sub-control device 21 is provided with an illegal command detection circuit 38 and a memory state switching circuit 39. Since this relates to the main part of the present invention, details will be described later.

  Here, as shown in FIGS. 4 and 5, the sub control device 21 includes a sub control device main body 40 and a memory device 41 that is detachably attached to the sub control device main body 40. The sub-control device main body 40 is configured by arranging a CPU 30, a RAM chip 32, an effect ROM chip 34 and the like on a substrate 43 for the main body. On the other hand, the memory device 41 is a device formed by disposing a control ROM chip 33, an illegal command detection circuit 38, and a memory state switching circuit 39 on a substrate 44 for a memory device. The main body 40 and the memory device 41 are provided with a pair of connectors 46a and 46b that are detachably connected to each other.

  The serial interface 36 is a serial peripheral interface, and as shown in FIG. 6, a clock signal line 36a for transmitting a clock signal from the CPU 30 (master) to the control ROM chip 33 (slave), and a control ROM chip from the CPU 30. 33, a chip select signal line 36b for transmitting a chip select signal to the CPU 33, a serial signal input line 36c for transmitting a command from the CPU 30 to the control ROM chip 33 by a serial transmission system, and a serial transmission system from the control ROM chip 33 to the CPU 30 by a serial transmission system. And a serial signal output line 36d for transmitting a signal.

  The control ROM chip 33 is a one-chip serial flash memory corresponding to the serial peripheral interface, and a general-purpose product is used. As shown in FIG. 6, the control ROM chip 33 is connected to the SCK terminal to which the clock signal line 36a is connected, the / CS terminal to which the chip select signal line 36b is connected, and the SI to which the serial signal input line 36c is connected. A terminal, a SO terminal to which the serial signal output line 36d is connected, a VCC terminal for power supply input, and a GND terminal for grounding. When the input voltage level of the / CS terminal becomes L level, the control ROM chip 33 enters a selection state in which command input to the SI terminal is enabled, and when the input voltage level of the / CS terminal becomes H level, the SI terminal The command input to is disabled, and the command is not executed.

  A command for controlling the control ROM chip 33 is input to the SI terminal of the control ROM chip 33 via the serial signal input line 36c in accordance with the serial peripheral interface standard. The signal output from the control ROM chip 33 is output from the SO terminal to the serial signal output line 36d. As shown in FIG. 7, commands that can be executed by the control ROM chip 33 include a read command, a write command, a chip erase command, a selective erase command, a write permission command, and the like. These commands include at least a one-byte instruction representing the instruction content at the head. Hereinafter, these commands will be described individually.

  The read command is a command for reading stored information in the control ROM chip 33. In the read command, 1-byte address information is added after the 1-byte instruction. When a read command is input in the selected state, the control ROM chip 33 outputs information from the address specified by the read command bit by bit until the information is not selected.

  The write command is a command for writing information to the control ROM chip 33. In the write command, 1-byte address information is added after a 1-byte instruction, and 1-256 bytes of write information is further added thereafter. When a write command is input in the selected state, the control ROM chip 33 writes information specified by the write command to the memory area, starting from the address specified by the write command.

  The chip erase command is a command consisting of only one byte instruction. When a chip erase command is input in the selected state, the control ROM chip 33 erases all stored information.

  The selective erasure command is a command for selectively erasing information stored in the control ROM chip 33. In the selective erase command, 1-byte address information is added after a 1-byte instruction. When the selective erase command is input in the selected state, the control ROM chip 33 erases the stored information at the address designated by the selective erase command.

  The write permission command is a command consisting of only 1-byte instructions. When a write permission command is input in the selected state, the control ROM chip 33 changes the write permission flag of the internal status register to “1” (write permission). The write permission flag is a flag that determines whether or not writing or erasure of storage information is permitted. When the write permission flag is “0” (write prohibition), a write command, a chip erase command, Even if a selective deletion command or the like is input, these commands are not executed and the stored information is maintained.

Next, a processing procedure for a general memory control device to read information stored in the control ROM chip 33 via the serial interface 36 will be described with reference to FIG.
(1) First, prior to outputting a read command to the control ROM chip 33, the memory control device outputs a chip select signal to the control ROM chip 33 at the H level at the timing t1 in FIG. To L level. As a result, the input voltage level of the / CS terminal becomes L level, and the control ROM chip 33 switches from the non-selected state to the selected state.
(2) Next, the memory control device outputs a read command to the serial signal input line 36c bit by bit at the timings t2 to t3 in FIG. The control ROM chip 33 takes in the read command input to the SI terminal bit by bit in accordance with the clock signal input to the SCK terminal.
(3) When the control ROM chip 33 receives all the 16-bit read commands at the timing t3 in FIG. 8A, it starts from the address specified by the read command from the next clock signal. The information stored in the control ROM chip 33 is output bit by bit to the serial signal output line 36d.
(4) Thereafter, when the memory control device receives a required amount of stored information from the control ROM chip 33 at the timing t4 in FIG. 8A, the memory control device switches the chip select signal to the H level. Accordingly, the control ROM chip 33 switches from the selected state to the non-selected state, stops outputting the stored information, and returns to the state before receiving the read command. Thus, a series of stored information reading procedures is completed.

Next, a processing procedure for a general memory control device to write stored information to the control ROM chip 33 via the serial interface 36 will be described with reference to FIG. In the normal state, the CPU 30 of the sub-control device 21 only executes a procedure for reading information stored in the control ROM chip 33, and the CPU 30 does not execute such a writing procedure.
(1) First, the memory control device switches the chip select signal to the control ROM chip 33 to the L level at the timing t1 in FIG. 8B, and the control ROM chip 33 is selected from the non-selected state. Change to
(2) Next, the memory control device outputs a write permission command to the serial signal input line 36c bit by bit in accordance with the clock signal at the timings t2 to t3 in FIG. The chip select signal is switched to the H level at the timing of t3 when all the write permission commands are output. Accordingly, the control ROM chip 33 receives the write permission command at the timings t2 to t3 in FIG. 8B, and sets the write permission flag of the status register to “1” at the timing t3. "(Write permission).
(3) Thereafter, the memory control device switches the chip select signal to the control ROM chip 33 to the L level again at the timing t4 in FIG. 8B, and selects the control ROM chip 33 from the non-selected state. Change to state.
(4) The memory control device outputs a write command to the serial signal input line 36c bit by bit in accordance with the clock signal at timings t5 to t6 in FIG. The chip select signal is switched to the H level at the output timing t6. Along with this, the control ROM chip 33 receives the write command at timings t5 to t6 in FIG. 8B, and starts from the address specified by the write command at timing t6. The data specified by the write command is written to the memory area. When the data writing is completed, the control ROM chip 33 changes the write permission flag of the status register to “0” (write prohibited), and further changes from the selected state to the non-selected state. It returns to the state before receiving the command to enable loading.

  The processing procedure for erasing the stored information in the control ROM chip 33 is the same as that described above except that after the write permission command is output, a chip erase command or a selective erase command is output instead of the write command. Therefore, detailed description of the stored information erasing procedure is omitted.

Below, the structure which concerns on the principal part of this invention is demonstrated.
As shown in FIG. 4, in addition to the control ROM chip 33, the serial interface 36 of the sub-control device 21 is connected with an illegal command detection circuit 38 according to the present invention. A memory state switching circuit 39 for disabling the control ROM chip 33 based on a detection signal from the command detection circuit 38 is provided.

  The illegal command detection circuit 38 monitors a command input to the control ROM chip 33 and detects the write permission command as an illegal command. As described above, the control ROM chip 33 requires a write permission command both when writing information and when erasing stored information. Therefore, if the execution of the write permission command is prevented, the control ROM The alteration of the stored information of the chip 33 can be prevented.

  Specifically, when a write permission command is input to the serial signal input line 36c, the illegal command detection circuit 38 detects the bit pattern “0011” included in the fourth to seventh bits of the write permission command. Thus, the detection signal is output before the eighth bit of the write permission command is input to the control ROM chip 33.

  As shown in FIGS. 6 and 9, the illegal command detection circuit 38 is connected in parallel to the clock signal line 36a, chip select signal line 36b, and serial signal input line 36c of the serial interface 36. An SCK terminal to be connected, a / CS terminal to which the chip select signal line 36b is connected, an SI terminal to which the serial signal input line 36c is connected, and an OUT terminal for outputting a detection signal are provided. As shown in FIG. 9, the illegal command detection circuit 38 detects the bit pattern “0011” and outputs a detection signal, and the timing at which the fourth to seventh bits of the command are input. And a counter circuit 51 for enabling the bit pattern detection circuit 50.

  As shown in FIG. 9, the bit pattern detection circuit 50 includes a shift register 52 that converts a serial signal input from the serial signal input line 36c into a parallel signal and outputs the parallel signal, and a parallel signal output from the shift register 52 is predetermined. And a comparator 53 for determining whether or not the bit pattern “0011” matches.

  The shift register 52 is a 4-bit shift register, and converts the latest 4-bit signal output to the serial signal input line 36c into a parallel signal based on inputs from the serial signal input line 36c and the clock signal line 36a. Then, the signals are output as parallel signals immediately from the four terminals QA, QB, QC, and QD (without a delay of one clock). Specifically, when up to the fourth bit of the command is input to the control ROM chip 33, the shift register 52 immediately outputs the first to fourth bits of the command as a parallel signal, and the fifth bit of the command. Are input, the second to fifth bits of the command are immediately output as a parallel signal.

  The comparator 53 is constituted by a combinational circuit, and immediately outputs a coincidence signal without a delay of one clock when the bit pattern of the parallel signal output from the shift register 52 is “0011”. As described above, this bit pattern is a bit pattern to be detected in order for the illegal command detection circuit 38 to detect a write permission command. The coincidence signal of the comparator 53 is input to the gate circuit 54, and the bit pattern detection circuit 50 outputs the coincidence signal of the comparator 53 as a detection signal from the OUT terminal only when the counter circuit 51 outputs an active signal. To do.

  As shown in FIG. 9, the counter circuit 51 receives a clock signal and a chip select signal. The counter circuit 51 does not operate when the chip select signal is at the H level, and counts clock pulses of the clock signal when the chip select signal falls. Then, the counter circuit 51 outputs an active signal (output voltage level H) at the rising timing of the fourth clock pulse from the start of counting and stops outputting the active signal (output) at the falling timing of the seventh clock pulse. Voltage level L). That is, the counter circuit 51 outputs an active signal at the timing when the fourth to seventh bits of the command are input to the serial signal input line 36c, and stops outputting the active signal at other timings.

  As described above, the active signal of the counter circuit 51 is input to the bit pattern detection circuit 50, so that the bit pattern detection circuit 50 compares only at the timing when the fourth to seventh bits of the command are input. The coincidence signal of the device 53 is validated, and a detection signal (output voltage level H) is output from the OUT terminal of the illegal command detection circuit 38. Here, at the timing when the fourth to seventh bits of the command are input, the shift register 52 reads the first to fourth bits, the second to fifth bits, the third to sixth bits, and the fourth to seventh bits of the command. Each group is sequentially output as a parallel signal, and the comparator 53 determines whether the parallel signal matches “0011”. Therefore, the illegal command detection circuit 38 outputs a detection signal only when the bit pattern of “0011” is included in the first to seventh bits of the command. As shown in FIG. 7, this bit pattern “0011” is included in the 4th to 7th bits of the write enable command, and is not included in the 1st to 7th bits of the other commands. It is. Therefore, the illegal command detection circuit 38 outputs a detection signal only when a write permission command is input to the serial signal input line 36c. Here, the illegal command detection circuit 38 is configured to immediately convert the command being output into a parallel signal by the shift register 52 and compare the bit pattern by the comparator 53 without a delay of one clock. When the seventh bit of the write enable command is input to the serial signal input line 36c, the illegal command detection circuit 38 detects the detection signal before the eighth bit of the write enable command is input to the serial signal input line 36c. Will be output.

  When the illegal command detection circuit 38 outputs a detection signal, the memory state switching circuit 39 controls the input voltage level of the / CS terminal of the control ROM chip 33 to H level to forcibly control the control ROM chip 33. It is to be in a non-selected state. Specifically, as shown in FIG. 10, the memory state switching circuit 39 includes an OR gate circuit 55 provided on the chip select signal line 36b, and a detection signal (voltage level) from the illegal command detection circuit 38 at the IN terminal. When H) is input, the OR gate circuit 55 controls the input voltage level of the / CS terminal of the control ROM chip 33 to be H level regardless of the chip select signal output from the CPU 30.

  More specifically, when a detection signal is input from the illegal command detection circuit 38 to the IN terminal, the memory state switching circuit 39 immediately controls the / CS terminal to the H level without a delay of one clock. At this time, the latch circuit 57 disposed in the memory state switching circuit 39 holds the output to the OR gate circuit 55, so that the memory state switching circuit 39 can control ROM even after the detection signal is stopped. The input voltage level of the / CS terminal of the chip 33 is maintained at the H level. As shown in FIG. 6, a reset signal line 60 for transmitting a reset signal is provided between the CPU 30 and the memory state switching circuit 39, and the memory state switching circuit 39 is connected to / CS of the control ROM chip 33. When a reset signal is input from the CPU 30 while the terminal is maintained at the H level, the output of the latch circuit 57 is inverted to return to the state before the detection signal is input, so that the chip select signal from the CPU 30 is controlled It becomes possible to input to the / CS terminal of the ROM chip 33 for use.

  Further, as shown in FIG. 6, the connector 46b of the memory device 41 has a switching effective state in which the memory state switching circuit 39 can switch the control ROM chip 33 to a non-selected state, and the memory state switching circuit 39 is for control. A write permission terminal 62 is provided for converting the ROM chip 33 to a switching invalid state in which the ROM chip 33 cannot be switched to a non-selected state. Specifically, as shown in FIGS. 6 and 10, the input to the write enable terminal 62 is input to the WE terminal of the memory state switching circuit 39, and the input voltage level of the write enable terminal 62 is H level. In the meantime, even if the memory state switching circuit 39 is in a switching invalid state and the illegal command detection circuit 38 outputs a detection signal, a chip select signal can be input to the control ROM chip 33.

  That is, the memory device 41 is attached to a memory writer or the like, and at this time, the control ROM chip 33 is caused to execute a write permission command by setting the input voltage level of the write permission terminal 62 to the H level. The information stored in the ROM chip 33 can be rewritten. On the other hand, the sub-control device 21 needs to protect the information stored in the control ROM chip 33. Therefore, as shown in FIG. 6, the input voltage level of the write permission terminal 62 is always controlled to the L level. As a result, the memory state switching circuit 39 is always in a switching valid state to prevent alteration of stored information in the control ROM chip 33.

  Hereinafter, the operations of the illegal command detection circuit 38 and the memory state switching circuit 39 will be specifically described with reference to the timing charts of FIGS.

FIG. 11 is a flowchart when a write permission command is input to the control ROM chip 33 by some unauthorized means. As described above, in the normal state, only commands necessary for reading stored information are input from the CPU 30 to the control ROM chip 33, and a write permission command is input to the control ROM chip 33. There is nothing.
(1) First, at time t1, the chip select signal input to the control ROM chip 33 is switched to the L level. As a result, the / CS terminal of the control ROM chip 33 switches from the non-selected state to the selected state. The counter circuit 51 of the illegal command detection circuit 38 starts counting the clock pulses of the clock signal line 36a when the chip select signal becomes L level.
(2) At time t2, input of a write permission command to the control ROM chip 33 is started. Here, each bit of the write permission command is input to the control ROM chip 33 and simultaneously to the shift register 52 of the illegal command detection circuit 38 connected in parallel.
(3) At the timing from t3 to t5 when the 4th to 7th bits of the write enable command are input, the counter circuit 51 outputs an active signal, and the bit pattern detection circuit 50 becomes valid. At the timing from t3 to t5, the bit pattern detection circuit 50 selects any one of the groups of the first to fourth bits, the second to fifth bits, the third to sixth bits, and the fourth to seventh bits of the write enable command. Each time a command is input to the shift register 52, it is determined in turn whether or not the bit pattern matches “0011”.
(4) When the seventh bit of the write enable command is input to the control ROM chip 33 and the shift register 52 at the timing of t4, the shift register 52 sets the bit pattern of the fourth to seventh bits of the write enable command. “0011” is output as a parallel signal, and the comparator 53 outputs a coincidence signal. At this time, since the counter circuit 51 outputs an active signal and the bit pattern detection circuit 50 is valid, the bit pattern detection circuit 50 outputs a detection signal from the OUT terminal of the illegal command detection circuit 38. Then, the detection signal of the illegal command detection circuit 38 is input to the memory state switching circuit 39, and the memory state switching circuit 39 controls the input voltage level of the / CS terminal of the control ROM chip 33 to the H level to control it. The ROM chip 33 is switched to a non-selected state. The memory state switching circuit 39 maintains the input voltage level at the / CS terminal of the control ROM chip 33 at the H level by switching the output of the internal latch circuit 57.
(5) The switching of the input voltage level at the / CS terminal of the control ROM chip 33 by the memory state switching circuit 39 is completed within one clock after the seventh bit of the write enable command is input. For this reason, even if the eighth bit (last bit) of the write enable command is input to the SI terminal of the control ROM chip 33 at the timing t5, the input signal is invalidated by the control ROM chip 33. The write permission command that has been input halfway is discarded without being executed.

  In this way, when the write permission command is input to the control ROM chip 33, the illegal command detection circuit 38 outputs a detection signal at the timing t4 when the seventh bit of the write permission command is input, When the memory state switching circuit 39 deselects the control ROM chip 33 within one clock, the 8th bit input of the write permission command is invalidated by the control ROM chip 33 and the write permission is enabled. The command is discarded without being executed. For this reason, in such a configuration, the write permission command is not executed in the control ROM chip 33, and the stored information in the control ROM chip 33 can be reliably protected.

FIG. 12 is a flowchart when a read command is input from the CPU 30 to the control ROM chip 33.
(1) First, at time t1, the CPU 30 switches the chip select signal input to the control ROM chip 33 to the L level. As a result, the / CS terminal of the control ROM chip 33 switches from the non-selected state to the selected state. The counter circuit 51 of the illegal command detection circuit 38 starts counting the clock pulses of the clock signal line 36a when the chip select signal becomes L level.
(2) Input of a read command from the CPU 30 to the control ROM chip 33 is started at timing t2. At this time, each bit of the read command is input to the control ROM chip 33 and simultaneously to the shift register 52 of the illegal command detection circuit 38.
(3) At the timing from t3 to t4 when the fourth to seventh bits of the read command are input, the counter circuit 51 outputs an active signal, and the bit pattern detection circuit 50 becomes valid. At the timing of t3 to t4, the bit pattern detection circuit 50 determines which one of the groups of the first to fourth bits, the second to fifth bits, the third to sixth bits, and the fourth to seventh bits of the read command. Whether or not it matches the bit pattern “0011” is sequentially determined every time a command is input to the shift register 52. However, since the bit pattern “0011” does not exist in the first to seventh bits of the read command, the illegal command detection circuit 38 does not output a detection signal.
(4) At the timing t5 when the 11th bit of the read command is input, the shift register 52 outputs the bit pattern “0011” included in the 8th to 11th bits of the read command, so that the comparator 53 matches. Output a signal. However, at the timing t5, the counter circuit 51 does not output an active signal, and the bit pattern detection circuit 50 is invalid. Therefore, even if the comparator 53 outputs a match signal, the illegal command detection circuit 38 Does not output detection signals.
(5) Thus, at the timing t3 to t4 when the counter circuit 51 outputs the active signal, the comparator 53 does not output the coincidence signal, and at the timing t5 when the comparator 53 outputs the coincidence signal, the counter circuit 51 is active. Since the signal is not output, the illegal command detection circuit 38 does not output the detection signal at the timing t2 to t6 when the read command is input, and the read command is input to the control ROM chip 33, and at the timing t6. When the entire read command is input, the control ROM chip 33 outputs data at an address specified by the read command from the SO terminal.

  In this way, the illegal command detection circuit 38 detects the presence or absence of the bit pattern of “0011” only up to the seventh bit of the command. Therefore, the bit of “0011” is added to the portion after the seventh bit of the read command. Even if the pattern is included, the illegal command detection circuit 38 does not detect the detection signal. Therefore, according to the illegal command detection circuit 38, a normal command output from the CPU 30 is input to the control ROM chip 33 without delay and executed by the control ROM chip 33.

  As described above, in this embodiment, when the write permission command necessary for writing or erasing the control ROM chip 33 is set as an illegal command and the write permission command is input to the control ROM chip 33. When the 7th bit of the write enable command is input, the illegal command detection circuit 38 detects the bit pattern included in the write enable command, and the 8th bit (last bit) of the write enable command is input. The memory state switching circuit 39 switches the control ROM chip 33 to the non-selected state before the write permission command is executed in the control ROM chip 33. Therefore, in this embodiment, the sub-control device 21 can reliably prevent the storage information of the control ROM chip 33 from being altered.

  In particular, in this embodiment, the illegal command detection circuit 38 is connected in parallel to the serial signal input line 36c and monitors the command output to the control ROM chip 33, so that the normal command is sent from the CPU 30 to the control ROM chip. 33 is input without delay. For this reason, in this embodiment, the CPU 30 can easily and quickly read out the stored information of the control ROM chip 33 while preventing an illegal command from being executed by the control ROM chip 33.

  In this embodiment, the counter circuit 51 detects the timing at which a command is input to the control ROM chip 33, and the bit pattern detection circuit 50 is enabled only at the timing at which the fourth to seventh bits of the command are input. Therefore, a portion where the bit pattern is common between a normal command and an illegal command or a portion where the bit pattern is not constant (address portion) is excluded from the detection target of the bit pattern detection circuit 50, and There is an advantage that an illegal command can be accurately distinguished by a relatively short bit pattern.

  Further, in this embodiment, the counter circuit 51 detects the head portion of the command input to the control ROM chip 33 based on the clock signal and chip select signal input to the control ROM chip 33. There is an advantage that the command detection circuit 38 can be realized by a simple circuit configuration.

  In this embodiment, the bit pattern detection circuit 50 is converted by the shift register 52 and the shift register 52 for converting the serial signal input to the control ROM chip 33 via the serial signal input line 36c into a parallel signal. The comparator 53 determines whether or not the parallel signal has a specific bit pattern, and outputs a detection signal when the comparator 53 determines that it has a specific bit pattern. When a bit pattern to be detected is input to the serial signal input line 36c, a detection signal can be output without a delay of one clock by a simple circuit configuration, and the control ROM chip 33 can be set in a non-selected state. There is an advantage that you can.

  In the present embodiment, when the detection signal is input from the illegal command detection circuit 38, the memory state switching circuit 39 receives the reset signal by the internal latch circuit 57 even if the detection signal is stopped. The illegal command detection circuit 38 detects a write permission command to keep the control ROM chip 33 in a non-selected state by continuing to control the / CS terminal of the control ROM chip 33 to the H level until Sometimes, there is an advantage that the information stored in the control ROM chip 33 can be reliably protected.

  In this embodiment, the control ROM chip 33, the illegal command detection circuit 38, the memory state switching circuit 39, and the connector 46b are arranged on the substrate 44 to constitute one memory device 41, and the memory Since the device 41 can be attached to and detached from the sub-control device main body 40, the memory device 41 is replaced with a memory device of an existing slot machine control device, so that it is difficult to modify stored information. A gaming machine control device including a chip can be easily realized at low cost.

  Further, in the memory device 41 according to the present embodiment, when the sub-control device 21 is mounted, the write permission terminal 62 is controlled to the L level, and modification of the stored information in the control ROM chip 33 is prohibited. However, if it is removed from the sub-control device 21 and the input voltage level of the write permission terminal 62 is controlled to H level by a memory writer or the like, the stored information can be written into the control ROM chip 33. For this reason, in this embodiment, when the slot machine 1 is discarded, the memory device 41 is removed from the sub-control device 21, and the storage information of the control ROM chip 33 is rewritten, so that the memory device of another game machine control device. 41 can be reused.

  In this embodiment, the configurations of the illegal command detection circuit and the memory state switching circuit are changed from those of the first embodiment. Since the configuration other than the illegal command detection circuit and the memory state switching circuit is the same as that of the first embodiment, the same reference numerals are used in the text and the drawings, and the description thereof is omitted.

  The difference between the present embodiment and the first embodiment will be described. In the first embodiment, the illegal command detection circuit 38 detects the bit pattern “0011” included in the fourth to seventh bits of the write permission command. In contrast to outputting the detection signal, the illegal command detection circuit 38a according to this embodiment detects the bit pattern “0110” included in the fifth to eighth bits of the write permission command and outputs the detection signal. Further, in the first embodiment, when the illegal command detection circuit 38 outputs a detection signal, the memory state switching circuit 39 controls the input voltage level of the / CS terminal of the control ROM chip 33 to the H level so that the control ROM The memory state switching circuit 39a according to the present embodiment controls the input voltage level at the VCC terminal of the control ROM chip 33 to the reference potential level (ground potential) while the chip 33 is brought into a non-selected state. By disconnecting the power input to the ROM chip 33, the control ROM chip 33 is turned off. In the power-off state, the control ROM chip 33 naturally cannot execute the command, and the command before execution or the command being input is discarded without being executed.

  As described above, when a write permission command is input, the control ROM chip 33 changes the write permission flag of the internal status register from “0” (write prohibition) to “1” (write permission). Is configured to change. Here, the control ROM chip 33 has a delay time of about one clock of the clock signal after the last bit of the write permission command is input and before the write permission flag is changed to “1”. In the present embodiment, the illegal command detection circuit 38a outputs a detection signal until the delay time elapses after the last bit (8th bit) of the write permission command is input, and the detection signal is The received memory state switching circuit 39a switches the control ROM chip 33 to the power-off state, thereby preventing the control ROM chip 33 from changing the write permission flag to “1”.

  As shown in FIGS. 13 and 14, the illegal command detection circuit 38a of this embodiment has the same basic circuit configuration as the illegal command detection circuit 38 (see FIGS. 6 and 9) of the first embodiment. Only the differences from the first embodiment will be described. In the bit pattern detection circuit 50a of the present embodiment, the bit pattern of the parallel signal output from the shift register 52 is “0110” (“0011” in the first embodiment). The comparator 53a immediately outputs a coincidence signal without a delay of one clock. The counter circuit 51a of this embodiment outputs an active signal at the timing when the fifth to eighth bits of the command (the fourth to seventh bits in the first embodiment) are input to the serial signal input line 36c. At the timing, the output of the active signal is stopped. According to such a configuration, the coincidence signal of the comparator 53a of the bit pattern detection circuit 50a is valid only at the timing when the fifth to eighth bits (fourth to seventh bits in the first embodiment) of the command are input. A detection signal (output voltage level H) can be output from the OUT terminal of the illegal command detection circuit 38a. When the write permission command is input to the serial signal input line 36c up to the 8th bit, the illegal command detection circuit 38a converts the bit pattern “0110” included in the 5th to 8th bits of the command to 1 clock. Detection is performed without delay, and a detection signal is output immediately.

  As shown in FIGS. 13 and 15, the memory state switching circuit 39a of this embodiment sets the input voltage level at the VCC terminal of the control ROM chip 33 to the reference potential level when the illegal command detection circuit 38a outputs a detection signal. By switching, the control ROM chip 33 is turned off. Although not shown in FIG. 13, the power supply line 37 connected to the VCC terminal of the control ROM chip 33 is connected to the connector 46 b and is normally connected to the VCC terminal of the control ROM chip 33. The power supply potential level is input from the power supply box 18 through the connector 46b and the power supply line 37.

  The difference from the memory state switching circuit 39 (see FIG. 10) of the first embodiment will be specifically described. The memory state switching circuit 39a of the present embodiment includes a NAND gate circuit 56 disposed on the power supply line 37. When the detection signal (voltage level H) from the illegal command detection circuit 38a is input to the IN terminal, the input voltage level of the VCC terminal of the control ROM chip 33 is changed to the power supply in the NAND gate circuit 56 portion. Control is performed from the potential level to the reference potential level. More specifically, when the detection signal is input from the illegal command detection circuit 38 to the IN terminal, the memory state switching circuit 39 immediately sets the input voltage level at the VCC terminal to the reference potential level without delay of one clock. Control. At this time, the latch circuit 57 disposed in the memory state switching circuit 39a holds the output to the NAND gate circuit 56, so that the memory state switching circuit 39a can control ROM even after the detection signal is stopped. The input voltage level at the VCC terminal of the chip 33 is maintained at the reference potential level. The reset signal line 60 for inverting the output of the latch circuit 57 is the same as in the first embodiment. In the present embodiment, as in the first embodiment, the input to the write permission terminal 62 of the memory device 41 is input to the WE terminal of the memory state switching circuit 39a, and the input voltage of the write permission terminal 62 is While the level is at the H level, even if the memory state switching circuit 39a is in a switching invalid state in which the control ROM chip 33 cannot be switched to the power-off state and the illegal command detection circuit 38a outputs a detection signal, the control is performed. The ROM chip 33 is configured to be supplied with power.

FIG. 16 is a flowchart in the case where a write permission command is input to the control ROM chip 33 by some unauthorized means. Based on the example of the timing chart, operations of the illegal command detection circuit 38a and the memory state switching circuit 39a according to the present embodiment will be specifically described.
(1) First, at time t1, the chip select signal input to the control ROM chip 33 is switched to the L level. As a result, the / CS terminal of the control ROM chip 33 switches from the non-selected state to the selected state. The counter circuit 51a of the illegal command detection circuit 38a starts counting clock pulses on the clock signal line 36a when the chip select signal becomes L level.
(2) At time t2, input of a write permission command to the control ROM chip 33 is started. Here, each bit of the write permission command is input to the control ROM chip 33 and simultaneously to the shift register 52 of the illegal command detection circuit 38a connected in parallel. The operation up to this timing is the same as in the first embodiment (see FIG. 11).
(3) In the present embodiment, the counter circuit 51a outputs an active signal at the timing from t3 to t5 when the fifth to eighth bits of the write permission command are input, and the bit pattern detection circuit 50a becomes valid. . At the timing from t3 to t5, the bit pattern detection circuit 50 determines which of the groups of the second to fifth bits, the third to sixth bits, the fourth to seventh bits, and the fifth to eighth bits of the write enable command. Each time a command is input to the shift register 52, it is determined in turn whether or not the bit pattern matches the bit pattern “0110”.
(4) When the 8th bit of the write enable command is input to the control ROM chip 33 and the shift register 52 at the timing of t4, the shift register 52 sets the bit pattern of the 5th to 8th bits of the write enable command. “0110” is output as a parallel signal, and the comparator 53a outputs a coincidence signal. At this time, since the counter circuit 51a outputs an active signal and the bit pattern detection circuit 50a is valid, the bit pattern detection circuit 50a outputs a detection signal from the OUT terminal of the illegal command detection circuit 38a. The detection signal of the illegal command detection circuit 38a is input to the memory state switching circuit 39a, and the memory state switching circuit 39a controls the input voltage level of the VCC terminal of the control ROM chip 33 to the reference potential level, thereby The ROM chip 33 is switched to the power off state. Further, the memory state switching circuit 39a maintains the input voltage level at the VCC terminal of the control ROM chip 33 at the reference potential level by switching the output of the internal latch circuit 57.
(5) The switching of the input voltage level at the VCC terminal of the control ROM chip 33 by the memory state switching circuit 39a is completed within one clock after the eighth bit of the write enable command is input. If the control ROM chip 33 does not switch to the power off state, the control ROM chip 33 executes the input write permission command at the timing t6 and sets the write permission flag to “1”. In this example, the write permission command is executed by switching the power-off state after the write permission command is input and before the control ROM chip 33 executes the write permission command. Is blocked.

  As described above, in this embodiment, when the write permission command is input to the control ROM chip 33, the illegal command detection circuit 38a is activated when the eighth bit of the write permission command is input (t4). The detection signal is output immediately, and the memory state switching circuit 39a switches the control ROM chip 33 to the power-off state without delay of one clock, so that the control ROM chip 33 executes a write permission command. Can be surely prevented. Therefore, even in the present embodiment, alteration of the storage information of the control ROM chip 33 can be reliably prevented without delaying the reading of the storage information of the control ROM chip 33.

  Note that the gaming machine of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, the present invention is applied to a slot machine sub-control device, but the gaming machine control device of the present invention can also be applied to other control devices such as a slot machine main control device. It is also applicable to control devices for other gaming machines such as pachinko machines.

  Further, the memory chip according to the present invention is not limited to the flash memory chip (control ROM chip 33) of the above-described embodiment, and adopts a whole nonvolatile memory corresponding to a serial interface and capable of electrically writing stored information. Is possible.

  In addition, the memory control device according to the present invention is not limited to the CPU 30 of the above-described embodiment, but may be configured by a GPU, a memory controller, or the like.

  Further, the serial interface according to the present invention is not limited to the serial peripheral interface of the above-described embodiment, and a serial interface of other standards (I2C, etc.) can also be adopted.

  In the above embodiment, the CPU 30 (memory control means) and the control ROM chip 33 (memory chip) are connected one-to-one via the serial interface 36. However, the serial interface according to the present invention includes a memory Multiple chips or other devices can be connected. When a plurality of memory chips are connected to the serial interface, the illegal command detection circuit may detect an illegal command input to all the memory chips, or input only to a part of the memory chips. An illegal command may be detected.

  In the above embodiment, the write permission command is set as an illegal command. However, the illegal command according to the present invention is not limited to the write permission command and can be set as appropriate according to the specifications of the memory chip. For example, a plurality of commands may be set as illegal commands, or in the gaming machine control device, all commands that are unnecessary for controlling the memory chip may be set as illegal commands.

  In the above embodiment, since the write permission command consisting only of the 8-bit instruction part is set as an illegal command, in the first embodiment, the control ROM chip is input before the 8th bit of the instruction part is input. 33 (memory chip) is in a non-selected state (inactive state), but if the command to which an address is added after the instruction part (such as a write command) is set as an illegal command, the address part is input During the process, the control ROM chip 33 (memory chip) may be in a non-selected state (inactive state).

  In the first embodiment, the non-selected state of the control ROM chip 33 (memory chip) corresponds to the inactive state according to the present invention. Not only the selected state, but any state where command input to the memory chip is invalid may be used. As another form of the inactive state, for example, there is a state where power supply to the memory chip is cut off. Such a configuration is realized by the memory state switching circuit controlling the input of the power supply input terminal of the memory chip when the detection signal is input. Further, a state in which a clock signal is not input to the memory chip can be inactivated. Such a configuration is realized by the memory state switching circuit controlling the input voltage of the clock signal input terminal of the memory chip or setting the clock signal input terminal to high impedance when the detection signal is input. In addition, a state where a terminal to which a command is input is in a high impedance state can be inactivated. Such a configuration is realized by the memory state switching circuit controlling the command input terminal of the memory chip to high impedance when the detection signal is input. As described above, various forms of the inactive state of the memory chip according to the present invention can be adopted, and an appropriate state may be selected as the inactive state in accordance with the specifications of the memory chip to be used.

  In the second embodiment, the power-off state of the control ROM chip 33 (memory chip) corresponds to the inexecutable state according to the present invention. It is not limited to the off state, and any state is acceptable as long as the memory chip cannot execute the command, and the inexecutable state can be appropriately set according to the memory chip to be used and the possible state. In the second embodiment, after the last bit of the illegal command (write permission command) is input to the memory chip (control ROM chip 33), the memory chip is switched to an inexecutable state (power off state). However, the present invention is not limited to this configuration, and it is also possible to detect the bit pattern of the illegal command before the final bit of the illegal command is input, and to switch the memory chip to an inexecutable state.

  In the above embodiment, when the reset signal is input from the CPU 30, the latch circuit 57 disposed in the memory state switching circuit 39 inverts the output of the latch circuit 57 and returns to the state before the detection signal is input. However, the output inversion of the latch circuit 57 is not limited to the reset signal input from the CPU 30. For example, when the detection signal is input, the inactive state may be maintained for a certain period of time, and then the output of the latch circuit 57 may be automatically reversed to return to the state before the detection signal is input. The latch circuit 57 may be enabled for a certain period of time triggered by the fall of the chip select signal input to the switching circuit 39.

1 slot machine 20 main control device 21 sub control device (control device for gaming machine)
22 Image control device 30 CPU (memory control device)
32 RAM chip 33 ROM chip for control (memory chip)
34 ROM chip for production 35 Parallel interface 36 Serial interface 36a Clock signal line 36b Chip select signal line 36c Serial signal input line (serial signal line)
36d Serial signal output line 38 Invalid command detection circuit (first illegal command detection circuit)
38a Illegal command detection circuit (second illegal command detection circuit)
39 Memory state switching circuit (first memory state switching circuit)
39a Memory state switching circuit (second memory state switching circuit)
40 Sub-control device body 41 Memory device 43, 44 Substrate 46a, 46b Connector 50, 50a Bit pattern detection circuit 51, 51a Counter circuit 52 Shift register 53, 53a Comparator 54 Gate circuit 55 OR gate circuit 56 NAND gate circuit 57 Latch circuit 60 Reset signal line 62 Write enable terminal

Claims (11)

A non-volatile memory chip controlled by a command;
A memory control device for outputting the command to the memory chip;
A serial interface having a serial signal line for transmitting the command from the memory control device to the memory chip by a serial transmission method;
The memory chip can be switched to an inactive state that disables the input of the command by controlling a predetermined terminal,
Further, the command is input in parallel to the serial signal line so that the command is input at the same clock timing as the memory chip, and the command input to the memory chip is monitored. A first illegal command that detects a bit pattern included in the illegal command and outputs a detection signal when the illegal command is input to the memory chip via the serial signal line. A detection circuit;
A first memory state switching circuit that switches the memory chip to the inactive state when the first illegal command detection circuit outputs a detection signal;
The first memory state switching circuit includes a latch circuit that maintains the inactive state of the memory chip until a predetermined trigger occurs when the detection signal is input from the first illegal command detection circuit. A control device for a gaming machine. The first illegal command detection circuit includes:
A bit pattern detection circuit that outputs the detection signal when a predetermined bit pattern is input via the serial signal line;
The timing at which the command is input to the memory chip is detected, the bit pattern detection circuit is enabled at the timing at which the bit at the predetermined position of the command is input, and the timing at which the bit at the predetermined position is input The game machine control device according to claim 1, further comprising: a counter circuit that invalidates the bit pattern detection circuit. The first illegal command detection circuit includes a bit pattern detection circuit,
The bit pattern detection circuit includes:
A shift register that converts a serial signal input to the memory chip via the serial signal line into a parallel signal;
A comparator that determines whether or not the parallel signal converted by the shift register has a predetermined bit pattern;
3. The gaming machine control device according to claim 1, wherein the detection signal is output when the comparator determines that the bit pattern is the predetermined bit pattern. 4.   A memory device comprising: a connector connectable to a gaming machine control device body; the memory chip; the first illegal command detection circuit; and the first memory state switching circuit. The game machine control device according to any one of claims 1 to 3, further comprising: The memory device includes a switching valid state in which the first memory state switching circuit can switch the memory chip to the inactive state according to an input voltage level of a predetermined write permission terminal, and the first memory state. The switching circuit is configured to change the memory chip to a switching invalid state in which the memory chip cannot be switched to the inactive state.
5. The write permission terminal is controlled to a voltage level at which the memory device is in the switching valid state in a state in which the memory device is mounted on the gaming machine controller main body. Control device for gaming machines. A non-volatile memory chip controlled by a command;
A memory control device for outputting the command to the memory chip;
A serial interface having a serial signal line for transmitting the command from the memory control device to the memory chip by a serial transmission method;
The memory chip can be switched to an inexecutable state in which the command cannot be executed by controlling a predetermined terminal,
Further, the command is input in parallel to the serial signal line so that the command is input at the same clock timing as the memory chip, and the command input to the memory chip is monitored. A second illegal command for detecting a bit pattern included in the illegal command and outputting a detection signal when the illegal command is input to the memory chip via the serial signal line. A detection circuit;
A second memory state switching circuit that switches the memory chip to the inexecutable state when the second illegal command detection circuit outputs a detection signal;
The second memory state switching circuit includes a latch circuit that maintains an inexecutable state of the memory chip until a predetermined trigger occurs when the detection signal is input from the second illegal command detection circuit. A control device for a gaming machine. The second illegal command detection circuit includes:
A bit pattern detection circuit that outputs the detection signal when a predetermined bit pattern is input via the serial signal line;
The timing at which the command is input to the memory chip is detected, the bit pattern detection circuit is enabled at the timing at which the bit at the predetermined position of the command is input, and the timing at which the bit at the predetermined position is input The game machine control device according to claim 6, further comprising: a counter circuit that invalidates the bit pattern detection circuit. The second illegal command detection circuit includes a bit pattern detection circuit,
The bit pattern detection circuit includes:
A shift register that converts a serial signal input to the memory chip via the serial signal line into a parallel signal;
A comparator that determines whether or not the parallel signal converted by the shift register has a predetermined bit pattern;
8. The gaming machine control device according to claim 6, wherein the detection signal is output when the comparator determines that the bit pattern is the predetermined bit pattern.   A memory device comprising: a connector connectable to a gaming machine control device body; the memory chip; the second illegal command detection circuit; and the second memory state switching circuit. The game machine control device according to any one of claims 6 to 8, wherein the game machine control device is provided. The memory device includes a switching valid state in which the second memory state switching circuit can switch the memory chip to the inactive state according to an input voltage level of a predetermined write permission terminal, and the second memory state. The switching circuit is configured to change the memory chip to a switching invalid state in which the memory chip cannot be switched to the inactive state.
10. The write permission terminal is controlled to a voltage level at which the memory device is in the switching valid state when the memory device is mounted on the gaming machine control device body. Control device for gaming machines.   3. The counter circuit according to claim 2, wherein the counter circuit is configured to detect a timing at which the command is input to the memory chip based on a chip select signal and a clock signal input to the memory chip. The control device for gaming machines according to claim 7.

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