JP5741724B2 - Game machine - Google Patents

Description

The present invention relates to a gaming machine represented by a pachinko gaming machine or the like.

For example, a pachinko gaming machine includes a display device that can display various types of symbols in a variable manner, and is configured to start variable display when a ball that has been driven into the game area passes through the symbol operating port. . When the variation display stops matches the symbol combination predetermined become those Tari, predetermined game value Ru is provided to the player.

Occurrence of such skilled enough, the sphere is determined by the timing of passing through the pattern actuation port. That is, it is provided with a random number counter that is periodically updated in a certain range by 1 count (for example, by 1 count every 2 ms, in the range of 0 to 346). the value of the random number counter (i.e., the random number value) read out, the read random number value, for example, when matching the predetermined value such as "7", and generates an equivalent or.

Recently, however, there have been reports of fraudulent acts using illegal boards called “hanging boards”. This fraud, hanging unauthorized substrate (attach the incorrect "hanging board"), is intended to unduly generate those or. Specifically, the false random number counter for the same function and a random number counter for determining a person or provided pachinko machine described above (1 count by periodically counter which is updated in a certain range) "hanging provided in the substrate "by resetting (0 cleared) and the combined value of the false random number counter power up or the like of the pachinko gaming machine, to grasp the timing of generation of those have enough in" hanging board ". Then, in accordance with the generation timing of those have enough grasped, the symbol actuation port passing signals of a sphere incorrectly generated in the "hanging board" which was output to the main control board of the pachinko gaming machine, unduly Tari those Is to generate. Amusement halls and the like have suffered a great deal of damage due to fraudulent acts using this “hanging board”.

The present invention has been made to solve the above illustrated problem or the like, and aims to provide a game machine capable of preventing abuse by "hanging board" or the like.

Gaming machine of claim 1, wherein in order to achieve this purpose, a random number counter for repeatedly updating the random number in a predetermined range, and against the random number value is updated with the random number counter, predetermined game to the player One byte of data including a predetermined bit indicating whether or not to add value is stored in an address related to the random number value, and an address related to the random number value indicated by the random number counter is constantly input from the random number counter, The storage means for always outputting the 1-byte data for the random number value indicated by the random number counter and the determination of whether or not to give a predetermined game value to the player, the 1-byte data is Granting and obtaining means for obtaining from the output of the memory means, examine the state of the predetermined bits of the data acquired by the acquiring means, a predetermined game value to the player Luke and a determination means for determining whether further detects a coming of determining whether or not a trigger for applying the predetermined game value, a detection means for outputting a detection signal to said acquisition means The acquisition unit is configured by a latch unit that latches 1-byte data constantly output from the storage unit at an input timing of a detection signal output from the detection unit .

According to the gaming machine of the present invention can and child to prevent fraud due to "hanging board", and the like.

It is a front view of the game board of the pachinko game machine which is one Example of this invention. It is the block diagram which showed the electrical structure of the pachinko gaming machine. (A) is the figure which showed the structure of 1 byte of comparison ROM for every bit, (b) is the figure which showed judgment results, such as jackpot by the state of a jackpot bit and a high probability jackpot bit. It is a figure explaining the acquisition (reading) system of the data with respect to the random value based on the random value updated by the random number counter. It is the flowchart which showed the reset interruption process.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the first embodiment, description will be made using a pachinko gaming machine as an example of a gaming machine, in particular, a first type pachinko gaming machine. Note that it is naturally possible to use the present invention for the third kind pachinko gaming machine and other gaming machines.

  FIG. 1 is a front view of the game board of the pachinko gaming machine P. Around the game board 1, there are provided a plurality of winning holes 2 through which 5 to 15 prize balls are paid out by winning a ball. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying symbols as a plurality of types of identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction, and in each of the three divided display areas, symbols are displayed in a variable manner.

  Below the LCD display 3, a symbol operation port (first type start port) 4 is provided. When the sphere passes through the symbol operating port 4, the above-described variation display on the LCD display 3 is started. Below the symbol operating port 4, a specific winning port (large winning port) 5 is provided. The specific winning opening 5 is a predetermined time (for example, 30 seconds) so that the ball is a big hit and the ball is easy to win when the display result after the fluctuation of the LCD display 3 matches one of the predetermined symbol combinations. It is a winning opening that is opened (until the second elapses or 10 balls are won). A V zone 5a is provided in the specific winning opening 5, and when the ball passes through the V zone 5a while the specific winning opening 5 is opened, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of balls win the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (special game state). is there.

  FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine P. As shown in FIG. The main control board C of the pachinko gaming machine P includes an MPU 11 that operates based on an operation clock 11a of 8.192 MHz, a ROM 12 that stores various control programs and fixed value data executed by the MPU 11, and an execution of the control program A RAM 13 which is a memory for temporarily storing various data sometimes, a 16-bit random number counter 14 which counts up at every falling edge of a clock pulse output from a 7.15909 MHz clock 14a, and its random number Comparison ROM 17 that stores predetermined data for the random value counted by the counter 14, that is, whether or not the random value is a big hit, and data output from the comparison ROM 17 (predetermined data for the random value) 8-bit latch register 19 for latching And an input and output port 16. The program shown in the flowchart of FIG. 5 is stored in the ROM 12 as a part of the control program.

  The random number counter 14 is a 16-bit counter that counts up one count at each falling edge of the clock pulse output from the 7.15909 MHz clock 14a. By this random number counter 14, the random number value is constantly updated in a range of “0 to 65535” at a high speed that can hardly be followed by software control. The updated random number value is always used as address data. It is output to the comparison ROM 17. Since the random number counter 14 is not arranged in the address space of the MPU 11, the count value of the random number counter 14 cannot be read from the MPU 11. In addition, the count value (random number value) of the random number counter 14 is not initialized when the power is turned on, and starts counting up from an indefinite value when the power is turned on. Therefore, the “hanging board” cannot grasp the indefinite initial value of the random number counter 14, and therefore cannot grasp the count value of the random number counter 14, that is, the random number value.

  Here, the relationship between the operation clock 11a of the MPU 11 and the clock 14a of the random number counter 14 will be described. Since the operation clock 11a of the MPU 11 has a frequency of 8.192 MHz, it is possible to obtain an interval of 2 ms for the reset interrupt processing executed by the main control board C with 16,384 clocks. On the other hand, since the clock 14a of the random number counter 14 has a frequency of 7.15909 MHz, an interval of 2 ms for the reset interrupt process cannot be obtained. Specifically, at 14,318 clocks, 1.99997485714 ms, which is less than 2 ms, and at 14,319 clocks, which is one clock higher than that, 2.000114539697 ms, exceeding 2 ms.

  While the game control of the pachinko gaming machine P is performed every 2 ms by the main control board C, the update of the random number value by the random number counter 14 that determines the jackpot cannot obtain the 2 ms interval 7.15909 MHz clock 14a, when the “hanging board” that acts illegally operates in synchronization with the main control board C, the count value (random number value) of the random number counter 14 cannot be grasped. When operating in synchronization with the random number counter 14, it cannot operate in synchronization with the main control board C. Therefore, since the passing signal of the symbol operating port 4 cannot be output from the “hanging board” to the main control board C of the pachinko gaming machine P in accordance with the occurrence timing of the jackpot, illegal acts using the “hanging board” are prevented. can do.

  The comparison ROM 17 is a memory that stores predetermined data for the random number value updated by the random number counter 14, that is, data such as whether or not the random number value is a big hit, for each random value, and the update range of the random number counter 14. It has a size of 64K bytes per minute. The data for the random value is provided for each random value by one byte and is stored at the address of the comparison ROM indicated by the random value. Therefore, the comparison ROM 17 occupies a large address space of “0000h to 0FFFFh”, but is arranged in an address space different from the address space (memory address space and I / O address space) accessible by the MPU 11. Even if the comparison ROM 17 has a large size of 64K bytes, the comparison ROM 17 does not occupy the 64K byte address space of the MPU 11, and the MPU 11 address space can be used effectively.

  The comparison ROM 17 is always in a lead state (active) with its lead terminal RD bar grounded. As described above, the count value (random number value) of the random number counter 14 is always output to the comparison ROM 17 as address data. Therefore, the comparison ROM 17 always provides data for the count value (random number value) of the random number counter 14. Is output.

  The latch register 19 is for latching data corresponding to an 8-bit random value output from the comparison ROM 17 (data indicating whether or not the random value is a big hit) at a predetermined timing. The latch register 19 is disposed in a memory address space accessible by the MPU 11, and shares a bus line 15 including an address bus and a data bus with the MPU 11, the ROM 12, and the RAM 13. In this embodiment, the predetermined timing for latching is the timing at which the MPU 11 reads the value of the latch register 19, but instead, for example, a ball is the first type starting port (design operating port). It is also possible to set the timing of passing through 4. In this case, an output signal of a switch for detecting whether or not the ball has passed through the first type start port 4 is input to the latch register 19 and is latched according to the signal.

  FIG. 3A is a diagram showing the configuration of 1-byte data in the comparison ROM 17 for each bit. As shown in FIG. 3A, the 0th bit of the comparison ROM 17 is assigned to the jackpot bit x (17a), and the first bit is assigned to the high probability jackpot bit y (17b). Depending on the state of each of these bits 17a and 17b, the big hit is determined as shown in FIG. That is, when the jackpot bit x (17a) is “0”, it is a loss (17d) regardless of the state of the high probability jackpot bit y (17b). When the jackpot bit x (17a) is “0”, there is no setting that the high probability jackpot bit y (17b) is “1” (17e). On the other hand, when the jackpot bit x (17a) is “1”, if the high probability jackpot bit y (17b) is “0”, it is a jackpot (17f), and the high probability jackpot bit y (17b) is “ If it is “1”, it is a high probability jackpot (17 g).

  Here, with reference to FIG. 4, a method for acquiring (reading) predetermined data for a random number value stored in the comparison ROM 17, that is, data for determining whether or not the random value is a jackpot will be described.

  A clock pulse of 7.15909 MHz is continuously output from the clock 14a to the random number counter 14 (41). In the random number counter 14, a random number value of “0 to 65535” is counted by one count every time the falling pulse is input. Update with a range. The updated 16-bit random number value is output as address data from the random number counter 14 to the comparison ROM 17 (42). Since the lead terminal RD bar of the comparison ROM 17 is grounded (43), the comparison ROM 17 is always in a read state (active). Therefore, every time a random value is output as address data from the random number counter 14 to the comparison ROM 17, data stored at the address indicated by the random value, that is, data corresponding to the random value (see FIG. 3) is transferred from the comparison ROM 17. It is output to the latch register 19 (44).

  When the ball passes through the first type start port 4, the value of the latch register 19 is read by the MPU 11 in order to determine the jackpot. In response to this read command (45), the data for the random number value output from the comparison ROM 17 is latched in the latch register 19 and read into the MPU 11 (46). Thereby, the data for the random value is acquired (read) by the MPU 11.

  As shown in FIG. 2, the MPU 11, ROM 12, RAM 13, and latch register 19 are connected to each other via a bus line 15, and the bus line 15 is also connected to an input / output port 16. The input / output port 16 is connected to the display control board D and other input / output devices 20. The main control board C transmits various commands to the display control board D and other input / output devices 20 through the input / output port 16 to control these devices. The main control board C and the display control board D are connected via two buffers (inverter gates) 18 and 28 with fixed inputs and outputs. Therefore, transmission / reception of commands between the main control board C and the display control board D is performed only in one direction from the main control board C to the display control board D, and from the display control board D to the main control board C. You cannot send commands to

  The display control board D includes an MPU 21, a program ROM 22, a work RAM 23, a video RAM 24, a character ROM 25, an image controller 26, an input port 29, and an output port 27. The output of the inverter gate 28 is connected to the input of the input port 29, and the output of the input port 29 is connected to a bus line connecting the MPU 21, the program ROM 22, and the work RAM 23. An image controller 26 is connected to the input of the output port 27, and the LCD display 3 is connected to the output of the output port 27.

  The MPU 21 of the display control board D is for controlling the (variation) display of the LCD display 3 based on the control command transmitted from the main control board C. The program ROM 22 is executed by the MPU 21. Various control programs to be executed are stored. The work RAM 23 is a memory in which work data used when the MPU 21 executes a program is stored.

  The video RAM 24 is a memory for storing data to be displayed on the LCD display 3, and the display content of the LCD display 3 is changed by rewriting the content of the video RAM 24. That is, the variable display of the symbols in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 adjusts the timing of each of the MPU 21, the video RAM 24, and the output port 27, intervenes in reading and writing data, and displays the display data stored in the video RAM 24 at a predetermined timing with reference to the character ROM 25. This is displayed on the display 3.

  Next, with reference to FIG. 5, the reset interrupt process performed on the main control board C will be described. FIG. 5 is a flowchart of a reset interrupt process executed every 2 ms on the main control board C. In this reset interrupt process, first, it is checked whether or not the process is the first process executed after power-on (S1). If it is the first process executed (S1: Yes), the RAM 13 Initialization processing such as setting the initial value after the content is once cleared to “0” is executed (S2). After execution of the process of S2, the execution of the process waits until the next reset interrupt process occurs.

  If it is determined in the process of S1 that the reset interrupt process is executed for the second time and after the power is turned on (S1: No), the game of the pachinko gaming machine P is controlled by each process of S3 to S9. Is called. In the control of the game, first, it is checked whether or not the ball has passed the first type starting port (symbol operating port) 4 (S3), and the ball has passed the first type starting port (symbol operating port) 4. If it is (S3: Yes), each process of S4-S8 is performed in order to determine whether it is a big hit.

  First, the value of the latch register 19 is read by the MPU 11 (45 in FIG. 4), and the read value is written to the B register which is an internal register of the MPU 11 (S4). As described with reference to FIG. 4, when the MPU 11 reads the value of the latch register 19, the data for the random number counted by the random number counter 14, that is, the data indicating whether or not the random number is a big hit is latched. The data is latched by the register 19 (44 in FIG. 4), and the data is read to the MPU 11 (46 in FIG. 4). Therefore, by reading the value of the latch register 19 by the MPU 11 and writing the read value to the B register, the data for the random value can be read into the B register.

  After the data for the random value is read into the B register, the state of the jackpot bit x (17a) of the B register is checked (S5). If the jackpot bit x (17a) is “1” (S5: Yes), it is a jackpot occurrence. In this case, the state of the high probability jackpot bit y (17b) is further examined (S6), It is determined whether or not the jackpot is a high probability jackpot. That is, if the high-probability jackpot bit y (17b) is “1” (S6: Yes), the high-probability jackpot processing is executed because the high-probability jackpot is generated (S7). If (17b) is “0” (S6: No), the jackpot processing is executed (S8) because it is a normal jackpot occurrence. In the process of S5, if the jackpot bit x (17a) is “0” (S5: No), it is not a jackpot, so the processes of S6 to S8 are skipped and the process proceeds to S9. .

  In the process of S9, each process (S9) for controlling the progress of the game is executed on the main control board C, and after the execution of each process (S9), until the next reset interrupt process occurs. Wait for processing to execute.

  As described above, according to the pachinko gaming machine P of the present embodiment, when a determination trigger such as a jackpot arrives, the value is simply updated by the random number counter 14 simply by reading the value of the latch register 19. Predetermined data for a random number value, that is, data indicating whether or not the random value is a big hit can be read into the MPU 11. Since the determination such as the big hit can be performed based on such data, the determination can be performed in a short time regardless of the size of the update range of the random number value. Therefore, the update range of the random number value can be expanded in order to prevent fraud using the “hanging board” or the like without hindering the game control of the pachinko gaming machine P.

  In the present embodiment, the determination means described in claim 1 corresponds to the processes of S5 to S8.

  The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be easily made without departing from the spirit of the present invention. It can be guessed.

  For example, in this embodiment, the random number counter 14, the comparison ROM 17, and the latch register 19 are configured separately from the MPU 11, but may be configured integrally with the MPU 11, that is, built in the MPU 11. If these are built in the MPU 11, the comparison ROM 17 and the latch register 19 cannot be exchanged for illegal ones, so that the effect of preventing illegal acts can be further improved.

  Further, although the latch register 19 is arranged on the memory address of the MPU 11, it may be arranged on the I / O address of the MPU 11. In such a case, access to the latch register 19 is performed via the input / output port 16. In such a case, as a matter of course, the latch register 19 may be built in the input / output port 16.

  Further, the frequency of the clock 14a of the random number counter 14 and the frequency of the clock 11a of the MPU 11 may be synchronized. In such a case, although the effect as a countermeasure against the “hanging board” is slightly diminished, the timing adjustment when the MPU 11 reads the latch register 19 can be simplified, so that the circuit cost can be reduced accordingly.

  The modification of this invention is shown below. 2. The gaming machine control device according to claim 1, further comprising an MPU that controls the game, wherein the random number counter, the storage unit, and the latch unit are built in the MPU. Control device 1. By incorporating these into the MPU and making them into one chip, it is possible to prevent the act of exchanging the storage means and the latch means with unauthorized ones in order to illegally generate a predetermined game value (for example, jackpot) . For example, some illegal storage means store only jackpot data, and some illegal latch means output only jackpot data.

  2. The gaming machine control device according to claim 1, or the gaming machine control device 1, comprising an MPU for controlling a game, wherein the random number counter and the storage means are spaces other than an address space accessible by the MPU. A control device 2 for a gaming machine, which is arranged in Therefore, the address space (including the memory address space and the I / O address space) accessible by the MPU can be used effectively.

  2. The gaming machine control device according to claim 1, or the gaming machine control device 1 or 2, wherein the random number counter constantly outputs an address related to the random number value to the storage unit, and the storage unit includes the random number counter. 2. A control device 3 for a gaming machine, wherein an address related to the random number is always input and the predetermined data for the random value is always output.

  4. The gaming machine control device according to claim 1, or the gaming machine control devices 1 to 3, wherein the data of the storage means read by the reading means includes a jackpot bit indicating whether or not a jackpot has occurred. A control device 4 for a gaming machine, which is provided. The presence or absence of a jackpot is determined based on the status of the jackpot bit.

  2. The gaming machine control device according to claim 1, or the gaming machine control devices 1 to 4, wherein the random number counter is updated by a high-speed pulse that cannot be updated by a software control. A game machine control device 5 as a feature. Therefore, in the software control using the “hanging board” or the like, the count value cannot be updated by following the random number counter, so that it is impossible to grasp the random value using the “hanging board” or the like.

  2. The gaming machine control device according to claim 1, or the gaming machine control device 1 to 5, further comprising an MPU that controls the game, and updating the count value by the random number counter is an operation clock of the MPU. A game machine control device 6, which is performed by an asynchronous clock. Therefore, in the software control using the “hanging board” or the like, the count value cannot be updated in synchronization with the update of the random number counter, so that it is impossible to grasp the random number value using the “hanging board” or the like. In addition, if the clock for updating the count value of the random number counter is a clock that is too fast to follow the update of the count value by software control, it will be possible to further grasp the random number value by software control such as “hanging board”. Can be difficult.

  2. The gaming machine control device according to claim 1, or the gaming machine control devices 1 to 6, wherein the random number counter is counted by a signal that is continuously output at non-uniform intervals according to a game control state. The game machine control device 7 is characterized in that the update is performed. Therefore, since the random number counter is constantly updated at non-uniform intervals, it is possible to make it impossible to grasp the random number value by the “hanging board” or the like.

  2. The gaming machine control device according to claim 1, or the gaming machine control devices 1 to 7, further comprising an MPU for controlling a game, wherein the random number counter includes an M1 signal output from the MPU, a memory Request signal, IO request signal, read signal, write signal, refresh signal, wait signal, bus request signal, bus acknowledge signal, at least one address bus signal, or at least one data bus signal A gaming machine control device 8 that updates a count value based on any one of the signals. Since these signals are constantly output at non-uniform intervals according to the control state of the game, it is not necessary to provide a separate circuit for generating the signals, and the circuit cost can be reduced. In addition, you may use combining several signals among the above-mentioned signals.

  2. The gaming machine control device according to claim 1, wherein the random number value is updated by the random number counter from an indefinite value. . For example, when the power is turned on, the random number that is the count value of the random number counter is not initialized, and the random number is updated from the indeterminate value at the time of turning on the power. Can be difficult.

14 Random number counter 17 Comparison ROM (storage means)
17a jackpot bit 17b high probability jackpot bit 19 latch register (latch means , acquisition means)
P Pachinko machine (game machine)
S5 determination means

Claims (1)

A random number counter that repeatedly updates a random value within a predetermined range;
And against the random number value is updated with the random number counter, a 1-byte data including a predetermined bit which indicates whether to assign a predetermined game value to the player, stores the address for the random number value, Storage means for constantly inputting an address relating to a random value indicated by the random number counter from the random number counter, and constantly outputting the 1-byte data for the random value indicated by the random number counter ;
An acquisition means for acquiring the 1-byte data from the output of the storage means when an opportunity to determine whether or not to give a predetermined game value to the player has arrived;
A determination unit that examines a state of the predetermined bit of the data acquired by the acquisition unit and determines whether or not to give a predetermined game value to the player ;
Furthermore,
The detection means for detecting the arrival of the determination timing of whether to give the predetermined game value, and outputting the detection signal to the acquisition means,
The game machine according to claim 1, wherein the acquisition means is constituted by a latch means for latching 1-byte data constantly output from the storage means at an input timing of a detection signal output from the detection means .

Images