JP4507020B2 - Bullet ball machine - Google Patents

Description

  The present invention relates to a ball game machine represented by a pachinko game machine, and more particularly to a ball game machine that generates an interrupt at a constant interval and performs control by the interrupt process.

  In this type of pachinko gaming machine, an external circuit that generates a reset signal at a constant interval (for example, a 2 ms cycle) is provided separately from the CPU that executes the calculation. A reset signal generated by the external circuit is input to the reset terminal of the CPU, causing the CPU to generate a reset interrupt at regular intervals. Since the CPU controls the pachinko gaming machine by this periodically generated reset interrupt, even if some abnormality occurs due to noise or the like during the execution of the game, the game can be continued without interruption. It can be done.

  However, this method requires an external circuit that generates a reset signal at regular intervals, resulting in an increase in circuit cost.

  By the way, some CPUs that have a built-in ROM and RAM and are made more resistant to noise to some extent are available. Many of these CPUs have a built-in timer interrupt circuit or the like, and therefore, by using such an internal interrupt circuit, the external circuit can be deleted and the circuit cost can be reduced.

  However, the interrupt by the internal interrupt circuit takes a long time from the occurrence of the interrupt until the interrupt processing is executed compared to the reset interrupt. There was a problem that could not be executed. That is, in the case of a reset interrupt, if the next reset interrupt occurs during the reset interrupt process, the next reset interrupt process is immediately executed regardless of the execution state of the CPU. However, in the interrupt by the internal interrupt circuit, even if an interrupt by the next internal interrupt circuit occurs during the interrupt processing by the internal interrupt circuit, the CPU terminates the instruction being executed, and Unless the stack pointer is returned by executing a RETI (RETurn Interrupt) instruction having a long execution time, interrupt processing by the next internal interrupt circuit cannot be executed. For this reason, in the interrupt by the internal interrupt circuit, it takes a longer time from the generation of the interrupt to the execution of the interrupt process than in the case of the reset interrupt.

  The present invention has been made to solve the above-described problems and the like, and an external circuit for generating a reset interrupt by controlling a ball game machine by an interrupt circuit incorporated in a CPU. An object of the present invention is to provide a ball game machine that can be deleted to reduce the circuit cost.

In order to achieve this object, the ball game machine according to claim 1 includes an interrupt means for generating an interrupt at a predetermined interval, and an interrupt process executed by an interrupt by the interrupt means, The interrupt processing is used to play a game by hitting a ball into the game area, and the jump destination address of the interrupt generated by the interrupt means is the jump destination address of the reset interrupt executed when the power is turned on. The interrupt means is composed of an interrupt circuit built in the CPU, and the interrupt processing returns the stack pointer value to the value before the occurrence of the interrupt processing. Return means, interrupt permission means for allowing the occurrence of multiple interrupts by the interrupt means, control means for executing control of the ball game machine, stack return means, interrupt permission means and control means After execution Until the next interrupt processing is executed, and a loop means for repeating a predetermined process.
According to the ball game machine of claim 1, in the interrupt process by the interrupt circuit built in the CPU, the value of the stack pointer is returned to the value before the occurrence of the interrupt process by the stack return means, Generation of multiple interrupts by the interrupt circuit is permitted by the interrupt permission means. Thereafter, the control of the ball game machine is executed by the control means, and when such control is completed, a predetermined process is repeated by the loop means until a multiple interrupt is generated by the permitted interrupt circuit. Therefore, when the next interrupt is generated by the interrupt circuit during the interrupt processing, the CPU immediately terminates the currently executing instruction and immediately executes the next interrupt without executing the long execution RETI instruction. Process is executed. Therefore, it is possible to shorten the time from the generation of the interrupt until the interrupt process is started.

  According to the ball game machine of the present invention, it is possible to shorten the time from the generation of an interrupt to the start of the interrupt process by the interrupt process using the interrupt circuit built in the CPU. Therefore, there is an effect that the circuit cost can be reduced by deleting the external circuit for generating the reset interrupt.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In this embodiment, a pachinko game machine will be described as an example of a ball game machine.

  FIG. 1 is a front view of the game board of the pachinko gaming machine P. Around the game board 1, there are provided a plurality of winning holes 2 through which 5 to 15 game balls are paid out by winning a hit ball. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying symbols as a plurality of types of identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction, and in each of the three divided display areas, symbols are displayed in a variable manner.

  Below the LCD display 3, a symbol operating gate 4 is provided. When the hit ball passes through the symbol operating gate 4, variation display on the LCD display 3 is started. Below the symbol operation gate 4, a specific winning opening (large winning opening) 5 is provided. The specific winning opening 5 is a big hit when the display result after the fluctuation of the LCD display 3 coincides with one of the predetermined symbol combinations, so that the hitting ball is easy to win for a predetermined time (for example, 30 It is a winning opening that is opened (until the second elapses or 10 hitting balls are won). A V zone 5a is provided in the specific winning opening 5, and when the hit ball passes through the V zone 5a while the specific winning opening 5 is opened, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of hit balls win the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (special game state). is there.

  FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine P. As shown in FIG. The control unit C of the pachinko gaming machine P includes a CPU 11 that is an arithmetic device, an EEPROM 16 that is a nonvolatile and electrically rewritable memory, and an input / output port 17 that are connected to each other via a bus line 18. Yes.

  The CPU 11 functions as various work areas including the arithmetic circuit 12, the timer interrupt circuit 13, the ROM 14 storing the programs and various data shown in the flowcharts of FIGS. 5 and 6, and the storage memory 15a. A RAM 15 and the like are provided. The arithmetic circuit 12 is a circuit having an ALU, various registers, a program counter, and the like, and is a circuit that executes an operation, that is, a program according to a program stored in the ROM 14. The timer interrupt circuit 13 is a circuit for generating an interrupt (outputting interrupt requests 13g1 to 13g5) when the set time has elapsed and causing the CPU 11 to perform an interrupt process. 5 circuits of 1 to timer 5 are provided.

  FIG. 3 is a block diagram of the timer interrupt circuit 13. As shown in FIG. 3, the timer interrupt circuit 13 includes a free running counter 13a, five compare registers 13b1 to 13b5, an interrupt flag register 13c, an interrupt mask register 13d, and ten AND circuits 13e1. To 13e5, 13f1 to 13f5. The free-running counter 13a is a 16-bit counter that is incremented by 1 every time the clock signal 13h is input. When the count value becomes FFFFh by counting up, the free running counter 13a is returned to 0000h by the next clock signal 13h. .

  The compare registers 13b1 to 13b5 have a comparator function to be compared with the value of the free running counter 13a. A total of five compare registers 13b1 to 13b5 are provided for each of the timers 1 to 5. A count value corresponding to the timing at which an interrupt is generated is written in each of the compare registers 13b1 to 13b5. When the count value of the free running counter 13a matches the count value written to the compare registers 13b1 to 13b5, The corresponding interrupt flags 13c1 to 13c5 of the interrupt flag register 13c are turned on.

  The interrupt flag register 13c is a flag that is turned on when the count value of the free-running counter 13a matches the count value of the compare registers 13b1 to 13b5, and indicates an interrupt generation state. Interrupt flags 13c1 to 13c5 of the interrupt flag register 13c are provided for the respective timers 1 to 5, and correspond to the respective compare registers 13b1 to 13b5.

  The interrupt mask register 13d is for setting permission or prohibition of interrupt for each timer 1 to 5, and is provided for each timer 1 to 5, respectively. When the corresponding timer mask registers 13d1 to 13d5 of the interrupt mask register 13d are turned on, the interrupts of the timers 1 to 5 are enabled, and conversely, when the timer mask registers 13d1 to 13d5 are turned off, Interrupts are prohibited.

  Of the ten AND circuits 13e1 to 13e5 and 13f1 to 13f5, the preceding AND circuits 13e1 to 13e5 input the timer interrupt flags 13c1 to 13c5 and the timer mask registers 13d1 to 13d5 for each timer 1 to 5, respectively. When both are turned on, an on signal is output to the subsequent AND circuits 13f1 to 13f5. The subsequent AND circuits 13f1 to 13f5 receive the interrupt enable / disable signal for the entire CPU 11 in addition to the output signals of the preceding AND circuits 13e1 to 13e5. Request 13g1 to 13g5.

  That is, in the state where the interrupt of the entire CPU 11 is permitted, the count value of the free running counter 13a and the count value of the compare registers 13b1 to 13b5 for the timers 1 to 5 whose interrupt is permitted by the interrupt mask register 13d Are matched, the corresponding timer interrupt flags 13c1 to 13c5 of the interrupt flag register 13c are turned on, and the corresponding interrupt requests 13g1 to 13g5 are output from the subsequent AND circuits 13f1 to 13f5.

  Here, the interrupt jump table will be described with reference to FIG. The interrupt jump table is a table that stores an address that is a jump destination of a program when there is an interrupt request 13g1 to 13g5. When the interrupt request 13g1 to 13g5 is output, the CPU 11 refers to the address of the interrupt jump table corresponding to the interrupt request 13g1 to 13g5, sets the value of the program counter to that address, and performs interrupt processing. Is executed. Therefore, a corresponding interrupt processing program is stored in the jump address (jump destination address) of the interrupt jump table.

  In this embodiment, the control of the pachinko gaming machine P is performed by a timer 1 interrupt. The jump address is set to the same RESET address as the jump address of the reset interrupt, illegal opcode trap interrupt, and clock monitor abnormal interrupt. The reset interrupt is an interrupt that is executed when the pachinko gaming machine P is powered on, and the illegal opcode trap interrupt is an interrupt that is executed when the CPU 11 fetches an undefined opcode. The clock monitor abnormality interrupt is an interrupt that is executed when an abnormality occurs in the clock monitor provided in the CPU 11. In other words, these reset interrupts, illegal opcode trap interrupts, and clock monitor abnormal interrupts are often generated by noise abnormalities such as electrostatic noise and AC line noise. Therefore, jump addresses of these interrupts are assigned to pachinko games. By making it the same as the jump address of the timer 1 interrupt for controlling the machine P, even if such noise occurs, the control can be continued without causing the pachinko gaming machine P to malfunction.

  Returning to FIG. A storage memory 15a provided in the RAM 15 is a memory for storing a count value written in the timer 1 compare register 13b1. The timer 1 interrupt of this embodiment is executed every 2 ms. Therefore, for each interrupt process executed by the timer 1 interrupt (every time the process of the flowchart of FIG. 5 is executed), a count value corresponding to 2 ms is added to the value of the storage memory 15a, and the count value after the addition Is stored in the storage memory 15a and written to the timer 1 compare register 13b1. Therefore, even if the timer 1 interrupt is a timer interrupt circuit using the free running counter 13a, the timer 1 interrupt is not accumulated without accumulating the error time from the occurrence of the interrupt until the actual interrupt processing is started. Can be executed periodically.

  In this embodiment, the compare registers 13b1 to 13b5 are all configured to be readable and writable. Therefore, without providing the storage memory 15a, the value of the timer 1 compare register 13b1 is directly read out, a count value corresponding to 2 ms is added to the value, and the addition result is written to the timer 1 compare register 13b1 again. It is conceivable to configure. However, the contents of the compare registers 13b1 to 13b5 are initialized to FFFFh by a system reset or a user reset. Therefore, when such a configuration is used, if noise or the like that generates a reset interrupt occurs, the interrupt interval (cycle) of the timer 1 interrupt is disturbed, and normal control cannot be continued. It is. Therefore, in this embodiment, in order to avoid such a problem due to noise or the like, a storage memory 15a is provided in the RAM 15, and the count value of the timer 1 compare register 13b1 is stored in the storage memory 15a.

  The input / output port 17 is connected to the display device D, another input / output device 19 and the like in addition to the CPU 11 and the EEPROM 16 connected via the bus line 18. The control unit C sends various operation commands to the display device D and other input / output devices 19 through the input / output port 17 to control these devices. That is, the fluctuation display of the LCD display 3 and the opening / closing operation of the specific winning opening 5 are also controlled based on this operation command.

  The display device D includes a CPU 21, a program ROM 22, a work RAM 23, a video RAM 24, a character ROM 25, an image controller 26, an input / output port 27, and the LCD display 3. The CPU 21 of the display device D performs display control (variable display) of the LCD display 3 in accordance with an operation command output from the control unit C. The program executed by the CPU 21 is stored in the program ROM 22. Has been. The work RAM 23 is a memory that stores work data used when the CPU 21 executes a program.

  The video RAM 24 is a memory for storing data to be displayed on the LCD display 3, and the display content of the LCD display 3 is changed by rewriting the content of the video RAM 24. That is, the variable display of the symbols in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 adjusts the timings of the CPU 21, the video RAM 24, and the input / output port 27, intervenes in reading and writing data, and displays display data stored in the video RAM 24 at a predetermined timing with reference to the character ROM 25. It is displayed on the LCD display 3.

  Next, each process executed by the control unit C of the pachinko gaming machine P configured as described above will be described with reference to the flowcharts of FIGS. 5 and 6. FIG. 5 is a flowchart of interrupt processing executed every 2 ms by timer 1 interrupt. As shown in the interrupt jump table of FIG. 4, the reset interrupt jump address is also the same RESET address as the timer 1 interrupt jump address. Therefore, this interrupt process is similarly executed in the reset interrupt process when the power is turned on. This interrupt process is executed in the same manner when an illegal opcode trap interrupt or a clock monitor abnormal interrupt occurs.

  In this interrupt process, first, interrupts for the entire CPU 11 are prohibited (S1), then the timer 1 interrupt flag 13c1 is cleared to cancel the interrupt request 13g1 of the timer 1 (S2), and the value of the stack pointer Is initialized (S3). Next, a pattern (for example, a keyword) written in a predetermined area of the RAM 15 is checked to check whether it is written correctly, that is, whether there is an abnormality in the pattern (S4). If there is an abnormality in the pattern (S4: Yes), the process is executed by the reset interrupt process after turning on the power. In this case, the RAM is initialized (S5), and the free running counter The value 13a is written into the storage memory 15a (S6). Note that the predetermined pattern checked in the process of S4 is written in the initialization process of the RAM.

  After the process of S6 or when no abnormality is found in the pattern check of S4 (S4: No), the process proceeds to S7. In the process of S7, a count value corresponding to 2 ms that is an interrupt interval (cycle) is added to the count value stored in the storage memory 15a (S7). Then, the value of the storage memory 15a after the addition is written into the timer 1 compare register 13b1 (S8), and the next timer 1 interrupt generation time is set. After that, the timer 1 mask register 13d1 is turned on (S9), and after interrupting the entire CPU 11 is permitted (S10), the main process, which is a control process of the pachinko gaming machine P, is executed (S11).

  After execution of the main process (S11), the remaining time process is repeated until the next timer 1 interrupt occurs (S12). FIG. 6 is a flowchart of the remaining time process. In the remaining time process, a predetermined process is performed (S13). The predetermined process (S13) includes, for example, an update process of a symbol pattern displayed on the LCD display 3 and an update process of a random number used in the main process (S11).

  During execution of the remaining time processing (S12), when the count value of the free running counter 13a matches the count value of the timer 1 compare register 13b1, the timer 1 interrupt flag 13c1 is turned on, and the timer 1 interrupt occurs, Since the timer 1 mask register 13d1 is already turned on by the process of S9 and the interrupt of the entire CPU 11 is permitted by the process of S10, the AND circuit 13f1 outputs the interrupt request 13g1 of the timer 1. Then, the CPU 11 saves the value of the program counter in the stack pointer after the instruction being executed is completed, and starts the interrupt process in the flowchart of FIG.

  As described above, in this interrupt process, the stack pointer is initialized by the process of S3. Therefore, when executing this interrupt process, the RETI (RETurn Interrupt) instruction having a long execution time is executed to obtain the value of the stack pointer. There is no need to return. In addition, since the timer 1 multiple interrupts are permitted by the processing of S9 and S10, when the timer 1 interrupt flag 13c1 is turned on, the timer 1 interrupt request 13g1 is immediately output. Therefore, this interrupt process can be executed within a short time after the occurrence of the timer 1 interrupt. Thus, the pachinko gaming machine P can be controlled even by using a timer interrupt built in the CPU 11.

  In this embodiment, the interrupt process described in claim 1 corresponds to the process of the flowchart of FIG. 5, and the process of S9 and S10 is the interrupt permission means (the process of S3 is the stack return means). However, the process of S11 corresponds to the control means, and the process of S12 corresponds to the loop means.

  The present invention has been described above based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be easily made without departing from the spirit of the present invention. It can be guessed.

  For example, in this embodiment, the interrupt process of FIG. 5 is shared with the interrupt process of the reset interrupt in addition to the interrupt process of the timer 1, so that the value of the stack pointer is returned in the process of S3. Instead, it is configured to initialize. However, when this interrupt process is not shared with the interrupt process of the reset interrupt and is dedicated to the interrupt process of timer 1, the stack pointer is not initialized in the process of S3, for example, popping A stack pointer value may be returned by executing an instruction or the like. In this case, execution of a pop instruction, addition or subtraction processing of a stack pointer value, and the like correspond to stack returning means.

  Of course, even when the interrupt process is shared by the timer 1 interrupt and the reset interrupt, the process of operating the stack pointer corresponding to S3 is the reset interrupt interrupt process and the timer. If it is divided by 1 interrupt processing, the stack pointer operation processing executed in the timer 1 interrupt processing is returned by, for example, execution of a pop instruction instead of initialization of the stack pointer. It may be configured.

  The modification of this invention is shown below. 2. The control apparatus for a ball game machine according to claim 1, wherein said stack return means initializes a stack pointer, and a jump destination address when an interrupt is generated by said interrupt circuit is executed when power is turned on. A control device 2 for a ball game machine characterized by being made the same as a jump destination address of a reset interrupt to be executed. Therefore, even if an abnormality that causes a reset interrupt occurs due to noise or the like, the jump destination address of the reset interrupt is the same as the jump destination address when the interrupt is generated by the interrupt circuit. When the reset interrupt is generated, the interrupt process is executed. Therefore, it is possible to control the ball game machine without malfunctioning.

  In the control device 2 of the ball game machine, the jump destination address when the interrupt is generated by the interrupt circuit is the same as the jump destination address of the trap interrupt that is generated when an undefined opcode is fetched. A control device 3 for a ball game machine characterized by the following. Therefore, even if an abnormality that causes a trap interrupt occurs due to noise or the like, the jump destination address of the trap interrupt is the same as the jump destination address when the interrupt is generated by the interrupt circuit. The interrupt process is executed by occurrence of a trap interrupt. Therefore, it is possible to control the ball game machine without malfunctioning.

  4. The ball game machine control device 2 or 3, or the ball ball game machine control device according to claim 1, wherein the interrupt circuit is constituted by a timer interrupt circuit and is updated every predetermined clock. A counter and a compare register to be compared with the value of the free-running counter, and generates an interrupt when the value of the free-running counter matches the value of the compare register. A set value storage means for storing a value set in the timer, an addition means for adding a time corresponding to an interrupt interval to the contents of the set value storage means when an interrupt is generated by the timer interrupt circuit, and the addition And a writing means for writing the addition result by the means into the compare register and the set value storage means. Control device 4. Therefore, even if it is a timer interruption using a free running counter, an interruption can be generated at a desired interval without accumulating error time from the occurrence of interruption until the interruption processing is started.

It is a front view of the game board of the pachinko game machine which is one Example of this invention. It is the block diagram which showed the electrical structure of the pachinko gaming machine. It is the block diagram which showed the structure of the timer interruption circuit. It is the figure which represented the interruption jump table typically. It is the flowchart which showed the interruption process. It is the flowchart which showed the remaining time process.

Explanation of symbols

11 CPU
13 Timer interrupt circuit (interrupt means, interrupt circuit)
14 ROM
15 RAM
15a Storage memory C Control unit D Display device P Pachinko machine (bullet game machine)

Claims (1)

A bullet ball that has an interrupt means for generating an interrupt at a predetermined interval and an interrupt process executed by the interrupt means, and that hits the hit ball into the game area by the interrupt process. In a ball game machine that controls a gaming machine,
The jump destination address of the interrupt generated by the interrupt means is different from the jump destination address of the reset interrupt executed when the power is turned on.
The interrupt means is composed of an interrupt circuit built in the CPU,
The interrupt process is
Stack return means for returning the value of the stack pointer to the value before the occurrence of the interrupt processing;
Interrupt permitting means for permitting the generation of multiple interrupts by the interrupt means;
Control means for executing control of the ball game machine;
A bullet ball game machine comprising loop means for repeating predetermined processing until execution of the next interrupt processing after execution of the stack return means, interrupt permission means and control means.

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