JP4399890B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention is a gaming machine represented by a pachinko gaming machine or the like.InIt is related.
[0002]
[Prior art]
  For exampleThe pachinko gaming machine is provided with a display device capable of variably displaying a plurality of types of symbols, and is configured to start variably displaying when a hit ball that has been driven into the game area passes through the symbol operating gate. When this variable display stops in accordance with a predetermined combination of symbols, it becomes a big hit and a predetermined game value is given to the player.Ru.
[0003]
  Whether or not the jackpot is generated is determined at the timing when the hit ball passes the symbol operating gate. That is, it is provided with a random number counter that is periodically updated by 1 count in a certain range (for example, 1 count every 2 ms, in the range of 0 to 630), and when the hit ball passes the symbol operation gate, When the value of the random number counter is read and the read value of the random number counter matches a predetermined value such as “7”, a big hit is generated..
[0004]
  However, recently, fraudulent activity using an illegal substrate called “hanging substrate” has been reported. This fraud isBadThe right board is hung (attached with an illegal “hanging board”) to unreasonably generate a big hit. Specifically, a counter (counter that is regularly updated within a certain range in increments of 1 count) within the “hanging board” functioning similarly to the random number counter for determining the jackpot provided in the pachinko gaming machine described above. Set the counter value to power on the pachinko machineetcBy resetting (clearing to 0) at the same time, the occurrence timing of the jackpot in the “hanging board” is grasped. And, in accordance with the grasping timing of the big jackpot, illegally generate the symbol action gate passing signal of the hitting ball in the “hanging board” and output it to the control board of the pachinko machine to generate an unfair jackpot It is to let you. In game halls and the like, a great deal of damage has been caused by fraudulent acts using this "hanging board".
[0005]
[0006]
[0007]
[Problems to be solved by the invention]
[0008]
[0009]
[0010]
  The present inventionExample aboveProblemsetcIt was made to solveTo prevent fraud by "hanging board" etc.It aims to provide a game machine that can be used.
[0011]
[Means for Solving the Problems]
  In order to achieve this object, the gaming machine according to claim 1,Random number storage means, first update means for updating the value of the random value storage means within a predetermined range, and reading means for reading the value of the random value storage means based on a predetermined trigger, Control means for giving a predetermined game value to the player when the value of the random value storage means read by the reading means matches a predetermined value;,The value of the random value storage means makes a round by being updated a predetermined number of times by the first update means, and the first update means makes the predetermined range when the value of the random value storage means makes a round. One of the values is updated as an initial value for updating, and the control means is updated in the same range as the predetermined range, and the initial value of the random number value storage means is updated. An initial value storage means used for the change, a second update means for reading the value of the initial value storage means, updating the value, and writing the updated value to the initial value storage means, and a periodic signal Output means for outputting a periodic signal, and performing periodic processing based on the periodic signal output by the output means, and after completion of the periodic processing, periodic processing based on the next periodic signal is performed. Predetermined processing repeatedly until In the predetermined process, read, update, and write processes are performed by the second update unit, and the random value storage unit is updated by the first update unit in the regular process. The control means determines whether or not the data in the storage means including the random value storage means and the initial value storage means is valid after power-on, and if the determination means determines that the data is valid A game executing means for executing a game using the data in the storage means, an initialization means for initializing the data in the storage means if determined by the determining means, and the second update When a periodic signal is output from the output means during execution of the writing process by the means, the execution of the periodic process based on the periodic signal is delayed, and the writing process Even when the execution of the predetermined periodic process is delayed by the periodic process execution delay means, the execution unit has a periodic process execution delay means for executing the periodic process whose execution is delayed after the execution is completed. The output of the periodic signal output from the output means for executing the next periodic processing is not delayed..
[0012]
  Claim2Listed gaming machinesIn the gaming machine according to claim 1,,The gaming machine is a pachinko gaming machine.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the present embodiment, description will be made using a pachinko gaming machine as an example of a gaming machine, in particular, a first type pachinko gaming machine. Note that it is naturally possible to use the present invention for other gaming machines such as a third type pachinko gaming machine and a slot machine.
[0014]
  FIG. 1 is a front view of a game board of a pachinko gaming machine P in the first embodiment. Around the game board 1, there are provided a plurality of winning holes 2 through which 5 to 15 game balls are paid out by winning a hit ball. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying symbols as a plurality of types of identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction, and in each of the three divided display areas, symbols are displayed in a variable manner.
[0015]
  Below the LCD display 3 is provided a symbol operating gate (first type starting port) 4, and when the hit ball passes through the symbol operating gate 4, the above-described variation display of the LCD display 3 is started. Below the symbol operation gate 4, a specific winning opening (large winning opening) 5 is provided. The specific winning opening 5 is a big hit when the display result after the fluctuation of the LCD display 3 coincides with one of the predetermined symbol combinations, so that the hitting ball is easy to win for a predetermined time (for example, 30 It is a winning opening that is opened (until the second elapses or 10 hitting balls are won). A V zone 5a is provided in the specific winning opening 5, and when the hit ball passes through the V zone 5a while the specific winning opening 5 is opened, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of hit balls win the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (special game state). is there.
[0016]
  FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine P. As shown in FIG. The control unit C of the pachinko gaming machine P includes a CPU 11 that is an arithmetic device, a ROM 12 that stores various control programs executed by the CPU 11 and fixed value data, and a memory that temporarily stores various data and the like. The RAM 13 is provided. The programs of the flowcharts shown in FIGS. 5 to 7 are stored in the ROM 12 as a part of the control program.
[0017]
  The CPU 11 includes an ALU that performs arithmetic operations, an accumulator (hereinafter referred to as “Acc”) 11a, a plurality of internal registers 11b, and a flag register 11c. The value of the counter or the like provided in the RAM 13 is once loaded (read) into the internal register 11b of the CPU 11, updated in the internal register 11b, and then saved (written) into the original counter of the RAM 13. Updated).
[0018]
  The 68-system 8-bit CPU 11 saves (writes) the value of the paired 2-byte (16-bit) internal register 11b to the 2-byte memory (in the RAM 13) of consecutive addresses with one instruction. be able to. Since the data bus of the bus line 14 is composed of 8 bits, writing in this case is performed in the order of the upper byte and the lower byte. On the other hand, in the 80 system 8-bit CPU, in contrast to the 68 system CPU 11, the paired 2-byte (16-bit) internal register value is transferred to the 2-byte memory at the continuous address. It can be saved with one instruction in the order of bytes.
[0019]
  The RAM 13 includes a random number counter 13a, an initial value counter 13b, and an initial value memory 13c. The random number counter 13a is a counter for determining the occurrence of a jackpot, and is updated by 1 count every 2 ms in the range of “0 to 630 (0 to 276h)” by the random number update process (S6) of FIG. The Therefore, the random number counter 13a is composed of 2 bytes. If the value of the random number counter 13a acquired when the hit ball passes the symbol operating gate 4 is, for example, “7”, a big hit occurs. When the jackpot occurs, a jackpot command is sent from the control unit C to the display device D described later. The display device D controls the variable display on the LCD display 3 to the jackpot state based on the jackpot command.
[0020]
  The initial value counter 13b is a counter for counting the initial value of the update of the random number counter 13a, and is composed of 2 bytes like the random number counter 13a. The value of the initial value counter 13b is updated by one count in the range of “0 to 630 (276h)” that is the same as the update range of the random number counter 13a by the initial value counter update process (S21) of FIG.
[0021]
  The initial value counter update process of FIG. 7 is repeated during the remaining time in the reset interrupt process of FIG. 5, that is, after the end of the sound effect process (S19) until the next reset interrupt process occurs. It is executed (S21). The reset interrupt process is executed every 2 ms, but the processing time of each process from S1 to S19 executed in one reset interrupt process changes depending on the game situation. The remaining time is not a fixed time but an indefinite time that changes according to the game situation. Since the “hanging board” cannot grasp the indefinite time, the value of the initial value counter 13b that is repeatedly updated within the indefinite time is used as the initial value for updating the random number counter 13a. It is impossible to grasp the timing of jackpot occurrence by “substrate”.
[0022]
  The initial value memory 13c is a memory for storing an initial value of update of the random number counter 13a, and is composed of 2 bytes like the random number counter 13a. In this embodiment, the initial value of the update of the random number counter 13a is changed every time the random number counter is updated once. Therefore, when the updated value of the random number counter 13a matches the value of the initial value memory 13c, one round of updating of the random number counter 13a is completed, so that when the two values 13a and 13c match, The initial value counter 13b is written into the random number counter 13a and the initial value memory 13c, and the initial value of the update of the random number counter 13a is changed. Therefore, even if the initial value of the update of the random number counter 13a is changed, the randomness is uniform (the same value is not obtained when continuously acquired, and all values can be extracted with the same probability). A random value can be obtained.
[0023]
  The CPU 11, ROM 12, and RAM 13 are connected to each other via a bus line 14, and the bus line 14 is also connected to an input / output port 15. The input / output port 15 is connected to the display device D and other input / output devices 16. The control unit C sends operation commands to the display device D and other input / output devices 16 via the input / output port 15 and controls these devices. The fluctuation display on the LCD display 3 and the opening / closing operation of the specific winning opening 5 are also controlled based on this operation command.
[0024]
  The display device D includes a CPU 21, a program ROM 22, a work RAM 23, a video RAM 24, a character ROM 25, an image controller 26, an input / output port 27, and the LCD display 3. The CPU 21 of the display device D performs display control (variable display) of the LCD display 3 in accordance with an operation command output from the control unit C. The program executed by the CPU 21 is stored in the program ROM 22. Has been. The work RAM 23 is a memory that stores work data used when the CPU 21 executes a program.
[0025]
  The video RAM 24 is a memory for storing data to be displayed on the LCD display 3, and the display content of the LCD display 3 is changed by rewriting the content of the video RAM 24. That is, the variable display of the symbols in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 adjusts the timings of the CPU 21, the video RAM 24, and the input / output port 27, intervenes in reading and writing data, and displays display data stored in the video RAM 24 at a predetermined timing with reference to the character ROM 25. It is displayed on the LCD display 3.
[0026]
  Next, with reference to FIG. 3 and FIG. 4, the occurrence timing of the user reset interrupt that triggers the execution of the reset interrupt process of FIG. 5 will be described. This user reset interrupt is generated every 2 ms and at the timing when the opcode fetch signal is output by the CPU 11, that is, at the timing when the output of the LIR terminal of the CPU 11 changes from Hi to Low. .
[0027]
  While the operation code fetch signal is being output, the operation code is read from the ROM 12 by the CPU 11, so that writing to the RAM 13 is not performed. Therefore, by generating a user reset interrupt in synchronization with the opcode fetch signal, even if the value of the initial value counter 13b is repeatedly updated during the remaining time of the reset interrupt process, the next reset interrupt process is performed. When it occurs, the value of the initial value counter 13b is not rewritten, and the value is not outside the original update range.
[0028]
  A reset IC 31 is connected to the reset terminal RES of the CPU 11. The output (A) of the reset IC 31 rises from Low to Hi when a predetermined time elapses after the pachinko gaming machine P is turned on, and thereafter maintains Hi until the power of the pachinko gaming machine P is turned off. The CPU 11 continues the operation while the input to the reset terminal RES rises from Low to Hi and maintains Hi.
[0029]
  In addition, a 8.1920 MHz oscillator (clock) 32 is connected to the CPU 11. The output of the clock 32 is divided by 4 in the CPU 11, and a rectangular oscillation wave having a period of 488.3 ns is output from the E clock terminal (B). Further, from the ICLK terminal, a rectangular wave having a 2 ms period obtained by dividing the E clock by 4096 is output (C).
[0030]
  The output terminal of the reset IC 31 is also connected to the CLR terminal of the D flip-flop 33 composed of HC74. Since the CK terminal of the D flip-flop 33 is connected to the ICLK terminal of the CPU 11 and the PR terminal and the D terminal are connected to Vcc (+5 V), the D flip-flop is kept until the output of the ICLK terminal of the CPU 11 rises. The Q output of 33 maintains Low (G), and the Q bar output maintains Hi (D). Once the output of the ICLK terminal of the CPU 11 rises from Low to Hi (C), the Q output of the D flip-flop 33 becomes Hi (G), the Q bar output becomes Low (D), and the D flip-flop 33 is a pachinko machine. This output is maintained until P is turned off.
[0031]
  The Q bar output terminal of the D flip-flop 33 is connected to one input terminal of the two-input OR circuit 34. The other input terminal of the OR circuit 34 is connected to the ICLK terminal of the CPU 11. Therefore, from the output end of the OR circuit 34, after the Q bar output of the D flip-flop 33 becomes Low (D), a rectangular wave having the same 2 ms cycle as the output (C) of the ICLK terminal is output (E ).
[0032]
  On the other hand, the E clock terminal of the CPU 11 is connected to the input terminal of the inverter 35, and the output terminal of the inverter 35 is connected to the CK terminal of the D flip-flop 36 composed of HC 74 and one input terminal of the two-input OR circuit 37. Has been. The D terminal of the D flip-flop 36 is at Vcc, the CLR terminal is at the Q output terminal of the D flip-flop 33, the D terminal is at the Q7 output terminal of the binary counter 38 composed of HC4020, and the Q output terminal is the OR circuit 37. Are respectively connected to the input terminals of. Further, the output terminal of the OR circuit 37 is connected to the CK terminal of the counter 38.
[0033]
  The Q output of the D flip-flop 33 input to the CLR terminal of the D flip-flop 36 maintains Hi (G) after the output of the ICLK terminal of the CPU 11 once rises from Low to Hi (C). Since Vcc is input to the PR terminal of the D flip-flop 36, thereafter, the output is input to the D terminal at every rise of the output (F) of the inverter 35 in which the output (B) of the E clock terminal of the CPU 11 is inverted. The state of the Q7 output (I) of the counter 38 is output from the Q terminal of the D flip-flop 36 (J). Therefore, the OR circuit 37 outputs the inverted output (F) of the E clock (H) while the output of the Q terminal of the D flip-flop 36 is Low (J) (H), and the output of the Q terminal of the D flip-flop 36 is During Hi, (J) and Hi are output (H).
[0034]
  In addition to being connected to the D terminal of the D flip-flop 36, the Q7 terminal of the counter 38 is connected to one input terminal of the 2-input OR circuit 39. The output terminal of the OR circuit 34 is connected to the other input terminal of the OR circuit 39. The Q7 output of the counter 38 remains low (I) while the output to the CLR terminal is Hi (E). When the output to the CLR terminal is Low (E) and the falling clock is input 64 times to the CK terminal (H), it becomes Hi (I), and the Hi output of the Q7 terminal is CLR. This is maintained until Hi is input to the terminal (E, I).
[0035]
  The OR circuit 39 outputs Low (K) when both the output of the OR circuit 34 and the Q7 output of the counter 38 are Low (E, I). Therefore, the output of the OR circuit 39 is maintained at the Low output until the falling clock is input 64 times to the CK terminal of the counter 38 (H) after the output of the OR circuit 34 becomes Low (E) (H). K). That is, the OR circuit 39 outputs Low every 2 ms (C, E) until the falling clock is input 64 times to the CK terminal of the counter 38 (H).
[0036]
  In the prior art, the output terminal of the OR circuit 39 is connected to the URES terminal of the CPU 11 so that a user reset interrupt is generated at the timing when the OR circuit 39 outputs Low. Therefore, the period during which the output of the OR circuit 39 is kept low (K) is a period for determining the occurrence of the user reset interrupt.
[0037]
  The output terminal of the OR circuit 39 is connected to the input terminal of the inverter 41 of the timing circuit 40 and the D terminal of the D flip-flop 42 formed by the HC 74. The timing circuit 40 is a circuit for generating a user reset interrupt at a timing synchronized with the operation code fetch. Since Low is output from the OR circuit 39 every 2 ms (K), the timing circuit 40 outputs Low to the URES terminal of the CPU 11 at the timing of the first opcode fetch after inputting the Low output (N ) And generate a user reset interrupt.
[0038]
  As described above, the input terminal of the inverter 41 of the timing circuit 40 is connected to the output terminal of the OR circuit 39, and the output terminal of the inverter 41 is connected to the PR terminal of the D flip-flop 42. Since the CLR terminal of the D flip-flop 42 is connected to Vcc, while the Hi terminal 39 outputs Hi from the Q terminal of the D flip-flop 42 connected to the URES terminal of the CPU 11 (Hi), Is output (N) and no user reset interrupt occurs.
[0039]
  The LIR terminal of the CPU 11 is connected to the input terminal of the inverter 43, and the output terminal of the inverter 43 is connected to the CK terminal of the D flip-flop 42. Since the output of the LIR terminal falls from Hi to Low when there is an operation code fetch, a rising signal from Low to Hi is output from the inverter 43 to the CK terminal of the D flip-flop 42 every time the operation code fetch is performed (M). .
[0040]
  Here, when Low is output from the OR circuit 39 (K), Hi is input to the PR terminal of the D flip-flop 42 (L). Since Vcc is input to the CLR terminal, when the operation code fetch signal is output from the CPU 11 and the output of the LIR terminal falls from Hi to Low, the input to the CK terminal of the D flip-flop 42 rises from Low to Hi ( M), the Low output inputted to the D terminal at that time is (K), outputted from the Q terminal of the D flip-flop 42 (N), and inputted to the URES terminal of the CPU 11. As a result, a user reset interrupt occurs at the opcode fetch timing.
[0041]
  Even if the user reset interrupt generation timing is delayed until the first opcode fetch timing in this way, the OR circuit 39 reliably outputs a Low signal every 2 ms (K), so that delay. Minutes do not accumulate. Therefore, a user reset interrupt can be executed every 2 ms.
[0042]
  Next, each process executed by the pachinko gaming machine P configured as described above will be described with reference to the flowcharts of FIGS. FIG. 5 is a flowchart of reset interrupt processing executed every 2 ms in the control unit C of the pachinko gaming machine P. The main control of the pachinko gaming machine P is executed by this reset interrupt process. This reset interrupt process is executed when a reset interrupt occurs when the power is turned on and when the above-described user reset interrupt occurs.
[0043]
  In the reset interrupt process, first, a stack pointer is set (S1), and a pattern written in a predetermined area of the RAM 13 is checked (S2). If the predetermined pattern is written in the predetermined area as a result of the check, the RAM 13 is normal and normal (S2: normal), and the process proceeds to S3. On the other hand, if the predetermined pattern is not written in the predetermined area as a result of the check in S2, it is the reset interrupt process executed first by the reset interrupt after power-on, or there is an abnormality in the RAM 13. (S2: Abnormal) In this case, the process proceeds to S22, and once the contents of the RAM 13 are cleared, the initial value is written into the RAM 13 (S22), and the next reset interrupt process is awaited. To do.
[0044]
  In the process of S3, a timer interrupt is set (S3). The timer interrupt set here includes a timer interrupt that generates a strobe signal for transmitting a command for controlling the display of the LCD display 3 to the display device D. After setting the timer interrupt, each interrupt is permitted (S4). After the permission of the interrupt, the output data updated in the previous reset interrupt process by the special symbol variation process (S15), the display data creation process (S17), the ramp / information processing (S18), etc. A port output process for outputting to the port is executed (S5). After the port output process is executed, a random number update process (S6) described later is executed to update the value of the random number counter 13a by "+1", and a storage timer subtraction process is executed (S7). The storage timer subtraction process shortens the symbol variation display time when there is a predetermined number or more of reserved balls for jackpot determination and when the symbol display is being displayed on the LCD display 3.
[0045]
  In the switch reading process (S8), the value of each switch is read to win the winning ball 2 and the big winning hole 5 (including the V zone 5a) of the ball that has been driven into the game area 1, This is a process for detecting passing, and also winning balls and rental balls. The count abnormality monitoring process (S9) is a process for monitoring whether there is an abnormality in the switch data read by the switch reading process of S8. For example, even though the big winning opening 5 is opened and a hit ball is detected by the V count switch that detects the passing of the hit ball through the V zone 5a, the winning in the big winning openings 5 other than the V zone 5a is detected 10 When a single shot cannot be detected by the count switch, some abnormality has occurred in the 10 count switch, such as the 10 count switch being pulled out or broken. Further, when a single prize ball is not paid out even though the motor for paying out a prize ball is driven, some abnormality has occurred in the prize ball payout device. As described above, in the count abnormality monitoring process (S9), the presence / absence of the abnormality as described above is monitored based on the switch data read by the switch reading process (S8).
[0046]
  In the symbol counter update process (S10), a counter update process for determining a symbol to be stopped and displayed as a result of the variable display performed on the LCD display 3 is performed. In the symbol check process (S11), based on the counter value updated in the symbol counter update process (S10), the jackpot symbol, the off symbol, and the reach symbol used in the special symbol variation process (S15). Etc. are determined.
[0047]
  If no error has occurred in the processing from S3 to S11 (S12: normal), the normal symbol variation processing (S13) displays the variation of the 7-segment LED, and the variation display results in a win. In this case, a hit process for releasing a normal electric accessory (not shown) for a predetermined time is executed. Thereafter, the state flag is checked (S14), and if the change of the symbol on the LCD display 3 is being displayed (S14: changing the symbol), the timing at which the hit ball passes the symbol operation gate 4 by the special symbol change process (S15). On the basis of the value of the random number counter 13a read in step (b), it is determined whether or not a big hit is made, and a display symbol variation process on the LCD display 3 is executed. On the other hand, if the result of checking the status flag is a big hit (S14: big hit), a big hit process (S16) such as opening the big prize opening 5 is executed. Further, as a result of checking the status flag, if the symbol is not changing or big hit (S14: Other), the processing of S15 and S16 is skipped and the process proceeds to the display data creation processing of S17. If an error is confirmed in the process of S12 (S12: error), each process of S13 to S16 is skipped and the process proceeds to a display data creation process of S17.
[0048]
  In the display data creation process (S17), demo data displayed on the LCD display 3, display data of the 7 segment LED, and the like are created in addition to the symbol variation display. In the lamp / information processing (S18), the lamp of the holding ball is displayed. Various lamp data including data are created. In the sound effect process (S19), sound effect data corresponding to the game situation is created. These display data and sound effect data are output to each device by the port output process (S5) and the timer interrupt process described above.
[0049]
  After the sound effect process (S19) ends, during the remaining time until the next reset interrupt process occurs, the symbol counter update process (S20), which is the same process as S10, and the initial value counter update process (S21) ) And repeatedly. Since the execution time of each process of S1-S19 changes according to the state of the game, the remaining time until the next reset interrupt process (next user reset interrupt) occurs is not a fixed time, but a game It changes according to the state. Therefore, by repeatedly executing the symbol counter update process (S20) using the remaining time, the stop symbol can be changed at random. Further, by repeatedly executing the initial value counter update process (S21) using the remaining time, the value of the initial value counter 13b that is the initial value of the update of the random number counter 13a cannot be grasped by the “hanging board”. can do.
[0050]
  FIG. 6 is a flowchart of random number update processing. In the random number updating process (S6), the value of the random number counter 13a is updated by “+1” within the range of “0 to 630 (0 to 276h)” via the internal register 11b of the CPU 11 and used by the control unit C. There are other random number updates.
[0051]
  First, the value of the random number counter 13a composed of 2 bytes is written to the 2-byte internal register 11b (S31). The value of the internal register 11b is incremented by 1 (S32), and it is checked whether or not the value of the internal register 11b after the addition is “631” or more, that is, whether or not the update range value of the random number counter 13a is exceeded. (S33). If the value of the internal register 11b after the addition is “631” or more (S33: Yes), the value of the internal register 11b is cleared to “0” because it exceeds the update range value (S34). On the other hand, if the value of the internal register 11b after addition is “630” or less (S33: No), the value is within the update range, so the process of S34 is skipped and the process proceeds to S35.
[0052]
  In the process of S35, the updated value of the internal register 11b is compared with the value of the initial value memory 13c. Since the initial value of the update of the random number counter 13a is stored in the initial value memory 13c, when both values are equal (S35: Yes), the update of the random number counter 13a is completed once. Therefore, in such a case, the value of the 2-byte initial value counter 13b is written to the internal register 11b (S36), and the value of the internal register 11b is written to the initial value memory 13c and the random number counter 13a (S37, S38). The initial value for updating the random number counter 13a is changed.
[0053]
  On the other hand, when the updated value of the internal register 11b is not equal to the value of the initial value memory 13c (S35: No), the update of the random number counter 13a has not been completed yet, so the processes of S36 and S37 are performed. Is skipped, the value of the internal register 11b updated in the processing from S32 to S34 is written to the random number counter 13a (S38), and the random number counter 13a is updated. Thereafter, another random number update process used in the control unit C is performed (S39), and this random number update process is terminated.
[0054]
  FIG. 7 is a flowchart of the initial value counter update process that is repeatedly executed during the remaining time of the reset interrupt process. In the initial value counter update process (S21), the value of the initial value counter 13b that counts the initial value of the update of the random number counter 13a is set via the internal register 11b of the CPU 11 to "0 to 630 ( 0 + 1 ”within the range of“ 0 to 276h) ”.
[0055]
  First, the value of the initial value counter 13b composed of 2 bytes is written to the 2-byte internal register 11b (S41). The value of the internal register 11b is incremented by 1 (S42), and it is checked whether or not the value of the internal register 11b after the addition is “631” or more, that is, whether or not the update range of the random number counter 13a is exceeded. (S43). If the value of the internal register 11b after the addition is “631” or more (S43: Yes), it exceeds the update range value of the random number counter 13a, so the value of the internal register 11b is cleared to “0” (S44). . On the other hand, if the value of the internal register 11b after addition is “630” or less (S43: No), the value is within the update range of the random number counter 13a, so the process of S44 is skipped and the process proceeds to S45. To do. In the process of S45, the updated value of the internal register 11b is written to the initial value counter 13b in order of the upper byte and the lower byte by the 2-byte write command of the 68-system CPU 11.
[0056]
  As described above, the initial value counter update process is repeatedly executed during the remaining time until the next reset interrupt occurs in the reset interrupt process (S21). For this reason, after the upper byte of the internal register 11b is written to the initial value counter 13b by the process of S45 and 2 ms elapses before the lower byte is written, the next user reset interrupt occurs. There is a case. The user reset interrupt is a non-maskable interrupt that has the highest interrupt priority and cannot prohibit the start of interrupt processing. However, as described above, the occurrence of the user reset interrupt is delayed by the timing circuit 40 until the timing of the first opcode fetch after the elapse of 2 ms. Therefore, during the execution of the write instruction by the CPU 11, the user reset interrupt is generated. Will not occur and the reset interrupt process will not be executed. Therefore, even if the value of the initial value counter 13b is repeatedly updated during the remaining time of the reset interrupt process, the value of the initial value counter 13b is “0 to 630 (0 to 276h) that is a value within the original update range. ) ".
[0057]
  Next, the timing circuit 50 of the second embodiment will be described with reference to FIGS. Although the timing circuit 40 of the first embodiment is configured to generate a user reset interrupt using the operation code fetch signal (output of the LIR terminal), the timing circuit 50 of the second embodiment is configured to read the signal (R / R User reset interrupt is generated using the Hi output of the W bar terminal.
[0058]
  Here, the read signal is a signal output when data stored in a memory such as the ROM 12 or the RAM 13 is read by the CPU 11 and is output as a Hi signal from the R / W bar terminal. On the other hand, the write signal is a signal that is output when data is written to the memory such as the RAM 13 by the CPU 11 and is output as a Low signal from the R / W bar terminal. Specifically, the read signal and the write signal are valid when the output of the E clock terminal is at the Hi level. For this reason, in this embodiment, the AND circuit 53 takes the AND logic of the outputs of the E clock terminal and the R / W bar terminal and inputs the AND logic to the CK terminal of the D flip-flop 54 (see FIG. 8). ).
[0059]
  Therefore, while the read signal is output (while the Hi signal is output from the AND circuit 53), the data in the ROM 12, RAM 13, etc. is read by the CPU 11, and the writing to the RAM 13 is not performed. . Therefore, by generating a user reset interrupt in synchronization with the read signal, even if the value of the initial value counter 13b is repeatedly updated during the remaining time of the reset interrupt process (S21 in FIG. 5), the next When the reset interrupt process occurs, the value of the initial value counter 13b is not rewritten, and the value is not outside the original update range. In addition, the same code | symbol is attached | subjected to the same part as above-mentioned 1st Example, the description is abbreviate | omitted, and only a different part is demonstrated.
[0060]
  The output terminal of the OR circuit 39 is connected to the input terminal of the inverter 51 of the timing circuit 50 and the D terminal of the D flip-flop 52 composed of HC74. The timing circuit 50 is a circuit for generating a user reset interrupt while a read signal is being output. In other words, the timing circuit 50 is also a circuit for prohibiting the occurrence of a user reset interrupt while the write signal is being output.
[0061]
  As described above, the input terminal of the inverter 51 of the timing circuit 50 is connected to the output terminal of the OR circuit 39, and the output terminal of the inverter 51 is connected to the PR terminal of the D flip-flop 52. Since the CLR terminal of the D flip-flop 52 is connected to Vcc, while the Hi terminal 39 outputs Hi from the Q terminal of the D flip-flop 52 connected to the URES terminal of the CPU 11 (Hi), Is output (Q) and no user reset interrupt occurs.
[0062]
  The R / W bar terminal of the CPU 11 is connected to one input terminal of the 2-input AND circuit 53, and the other input terminal of the AND circuit 53 is connected to the E clock terminal of the CPU 11. Further, the output terminal of the AND circuit 53 is connected to the CK terminal of the D flip-flop 52. When the read signal is output from the CPU 11 and the output of the R / W bar terminal is Hi, when the output of the E clock rises from Low to Hi (B), the AND circuit 53 goes Low to the CK terminal of the D flip-flop 52. A rising signal from P to Hi is output (P).
[0063]
  Here, when Low is output from the OR circuit 39 (K), Hi is input to the PR terminal of the D flip-flop 52 (L). Since Vcc is input to the CLR terminal, when the output of the E clock rises from Low to Hi while Hi is output from the R / W bar terminal (B), the input to the CK terminal of the D flip-flop 52 Rises from Low to Hi (P), and the Low output input to the D terminal at that time (K) is output from the Q terminal of the D flip-flop 52 to the URES terminal of the CPU 11 (Q). As a result, a user reset interrupt occurs at the timing when the read signal is output. Therefore, the execution of the next reset interrupt process is not started during the writing to the initial value counter 13b.
[0064]
  In this way, the occurrence timing of the user reset interrupt is delayed until the first read signal is output and the output of the E clock terminal rises after the output of the OR circuit 39 becomes Low. Even in this configuration, the OR circuit 39 reliably outputs a Low signal every 2 ms (K), so that the delay amount does not accumulate. Therefore, also in the second embodiment, a user reset interrupt can be generated every 2 ms, and the reset interrupt process can be executed every 2 ms.
[0065]
  In each of the embodiments described above,The first update means corresponds to the process of S6 of the reset interrupt process (FIG. 5), the second update means corresponds to the process of S21 of the reset interrupt process (FIG. 5), and the periodic process includes the reset interrupt process. 5 corresponds to the processes of S1 to S19 of the interrupt process (FIG. 5), the processes of S20 and S21 of the reset interrupt process (FIG. 5) correspond to the predetermined process, and the reset interrupt process (FIG. 5). ) Of S2 corresponds to the initialization process, and the process of S22 of the reset interrupt process (FIG. 5) is used as initialization means.Is applicable.
[0066]
  The present invention has been described above based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be easily made without departing from the spirit of the present invention. It can be guessed.
[0067]
  The modification of this invention is shown below. 2. The gaming machine control device according to claim 1, further comprising: a CPU that is a game controlling entity, and the prohibiting means prohibits new generation of the interrupt process while a write signal is output from the CPU. A control device 1 of a gaming machine characterized by the above.
[0068]
  2. The gaming machine control device according to claim 1, further comprising: a CPU that is a game controlling entity, and the prohibiting means permits a new generation of the interrupt process while a read signal is output from the CPU. A control device 2 of a gaming machine characterized by the above. While the read signal is output, the CPU reads the memory and does not write to the memory. Therefore, when the write process is executed in the interrupt process, new generation of the interrupt process can be prohibited.
[0069]
  2. The gaming machine control device according to claim 1, further comprising a CPU which is a game controlling entity, and the prohibiting means allows a new generation of the interrupt process while an opcode fetch signal is output from the CPU. A game machine control device 3. While the opcode fetch signal is being output, the opcode is read by the CPU and is not written to the memory. Therefore, when the write process is executed in the interrupt process, new generation of the interrupt process can be prohibited.
[0070]
  2. The gaming machine control device according to claim 1, or the gaming machine control devices 1 to 3, wherein the interrupt process is configured by a non-maskable reset interrupt process or a non-maskable user reset interrupt process. A control device 4 for the gaming machine.
[0071]
  2. The gaming machine control device according to claim 1, or the gaming machine control devices 1 to 4, wherein a random number counter, first update means for updating the value of the random number counter by the interrupt processing, and a predetermined trigger Reading means for reading the value of the random number counter, and when the value of the random number counter read by the reading means matches one of the predetermined values, the player is given a predetermined game under predetermined conditions. An initial value memory for storing an initial value of the random number counter being updated, and a value written to the initial value memory and the random number counter, and an initial value for the next update of the random number counter. An initial value counter composed of at least 2 bytes to be counted, and the value of the initial value counter is read and updated within the update range of the random number counter. A second updating means for writing to the initial value counter; and a repeating means for repeatedly executing the second updating means during the remaining time until the next interruption processing is generated by the interruption processing. A control device 5 of a gaming machine characterized by the above.
[0072]
  In the gaming machine control device 5, the value of the initial value counter is written in the random number counter and the initial value memory when the value of the random number counter matches the value of the initial value memory. Control device 6 of the machine.
[0073]
【The invention's effect】
  According to the gaming machine of the present invention,Can prevent fraudulent acts such as "hanging board".
[Brief description of the drawings]
FIG. 1 is a front view of a game board of a pachinko gaming machine according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing an electrical configuration of a pachinko gaming machine.
FIG. 3 is a block diagram of a circuit for generating a user reset interrupt at intervals of 2 ms.
4 is a timing chart of the circuit of FIG.
FIG. 5 is a flowchart showing reset interrupt processing;
FIG. 6 is a flowchart showing random number update processing.
FIG. 7 is a flowchart showing an initial value counter update process.
FIG. 8 is a block diagram of a circuit for generating a user reset interrupt at an interval of 2 ms in the second embodiment.
FIG. 9 is a timing chart of the circuit of FIG.
[Explanation of symbols]
11 CPU of control unit(Part of control means, output means, game execution means)
13a random number counter(Random value storage means)
13b Initial value counter(Initial value storage means)
40, 50 Timing circuit (Periodic processing execution delaymeans)
C control unit(Control means)
P Pachinko machine (game machine)

Claims (2)

Random number storage means, first update means for updating the value of the random value storage means within a predetermined range, and reading means for reading the value of the random value storage means based on a predetermined trigger, In a gaming machine comprising control means for giving a predetermined game value to a player when the value of the random number storage means read by the reading means matches a predetermined value ,
The value of the random value storage means is rotated once by being updated a predetermined number of times by the first update means,
When the value of the random number storage means goes around once, the first update means updates the next round using any value within the predetermined range as an initial value of the update,
The control means includes
An initial value storage means that is updated in the same range as the predetermined range and is used to change the initial value of the update of the random value storage means;
A second updating means for reading the value of the initial value storage means, updating the value, and writing the updated value to the initial value storage means;
Output means for outputting a periodic signal that is a periodic signal;
The periodic processing is performed based on the periodic signal output by the output means, and the predetermined processing is repeatedly performed during the period until the periodic processing based on the next periodic signal is performed after the termination of the periodic processing,
In the predetermined process, read, update, and write processes are performed by the second update unit,
The update of the random value storage means by the first update means is performed in the regular processing,
The control means includes
Determining means for determining whether or not the data in the storage means including the random value storage means and the initial value storage means is valid after power-on;
A game execution means for executing a game using the data of the storage means when determined to be valid by the determination means;
An initialization means for initializing data in the storage means when it is determined that the determination means is not valid;
When a periodic signal is output from the output means during execution of the writing process by the second update means, the execution of the periodic process based on the periodic signal is delayed, and after the execution of the writing process is completed, Periodic processing execution delay means for executing periodic processing whose execution is delayed,
Even when the execution of a predetermined periodic process is delayed by the periodic process execution delay means, the output of the periodic signal output from the output means for executing the next periodic process is not delayed. A gaming machine characterized by The gaming machine according to claim 1, wherein the gaming machine is a pachinko gaming machine.

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