JP4375475B2 - Bullet ball machine - Google Patents

Description

The present invention relates to a pinball game machine typified pachinko machines, in particular, to a ball-shooting game machine which can prevent abuse by "hanging board" or the like.

  This type of pachinko gaming machine is equipped with a display device capable of variably displaying a plurality of types of symbols, and is configured to start variably displaying when a hit ball that has been driven into the game area passes through the symbol operating gate. . When this variable display stops in accordance with a predetermined combination of symbols, a big hit is made, a predetermined game value is given to the player, and a large amount of game balls can be paid out.

  Whether or not the jackpot is generated is determined at the timing when the hit ball passes the symbol operating gate. That is, a counter that is periodically updated in a certain range by one count (for example, by 1 count every 2 ms, in a range of 0 to 630) is provided when the hit ball passes the symbol operation gate. When the read counter value matches a predetermined value such as “7”, a jackpot is generated.

  Recently, however, there have been reports of fraudulent acts using illegal boards called “hanging boards”. This fraudulent act is that an illegal substrate is hung between the control substrate and the display substrate of the display device (an illegal “hanging substrate” is attached), and an unreasonable jackpot is generated. Specifically, a counter (counter that is periodically updated within a certain range) in the “hanging board” is operated in the same manner as the counter for determining the jackpot provided in the pachinko gaming machine. The counter is reset (cleared to 0) when the pachinko gaming machine is powered on, etc., and the occurrence timing of the jackpot in the “hanging board” is grasped. And, in accordance with the grasping timing of the jackpot, illegally generate a signal operation gate passing signal of the hit ball in the “hanging board”, and output this to the control board of the pachinko machine to generate an unreasonable jackpot It is to let you. In game halls and the like, there has been a problem that a large amount of damage has been caused by fraudulent acts using this "hanging board".

The present invention has been made to solve the above illustrated problem like bullets can be impossible to grasp the generation timing of the jackpot, etc., to prevent fraud with "hanging board" or the like It aims to provide a ball game machine.

In order to achieve this object, the ball game machine according to claim 1, wherein the random number counter, first updating means for updating the value of the random number counter within a predetermined range, and the random number counter based on a predetermined trigger are provided. Read out means for reading out the value of the random number counter, and control means for giving a predetermined game value to the player when the value of the random number counter read out by the read out means matches a predetermined value. The value of the random number counter makes a round by being updated a predetermined number of times by the first updating means, and the first updating means has a value within the predetermined range when the value of the random number counter makes a round. Any one of the values is used as an initial value of the update, and the next round is updated. The control means changes the initial value of the update of the first update means every time the value of the random number counter makes a round. Change means, and And an initial value counter used by the changing means for changing the initial value, and a second updating means for updating the value of the initial value counter, and based on a periodic interrupt signal. A predetermined process is repeatedly performed during a period until the next periodic process is performed after the end of the periodic process. In the predetermined process and the periodic process, the second update is performed. Update by the means, the update of the random number counter by the first update means is performed in the periodic processing, before the first update of the random number counter by the first update means after the power is turned on, The first update after the initial value counter is updated by the second update means and the initial value counter is updated by the second update means in the predetermined processing. Even if the random number counter is updated by the stage, the initial value counter is updated by the second update unit before the random number counter is updated by the first update unit in the periodic process. Is done.

Ball-shooting game machine according to claim 2, wherein, in the ball-shooting game machine according to claim 1, wherein the bullet ball game machine is a pachinko machine.

According to the ball game machine of the present invention, the value of the random number counter is updated by the first updating unit and is read by the reading unit based on a predetermined trigger. When the read value of the random number counter matches a predetermined value, a predetermined game value is given to the player.

  The initial value for updating the random number counter is changed based on the value of the initial value counter. Thus, since the initial value of the update of the random number counter is not a fixed value but a value that is periodically changed, it is possible to prevent the “hanging board” or the like from grasping the occurrence timing of the jackpot or the like. It is.

According to the ball game machine of the present invention, the initial value for updating the random number counter for determining the jackpot etc. is not a fixed value but a value that is periodically changed. This makes it impossible to grasp the occurrence timing of the above and prevents illegal acts caused by the “hanging board” or the like.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the present embodiment, description will be made using a pachinko gaming machine as an example of a ball game machine, in particular, a first type pachinko gaming machine. Of course, it is possible to use the present invention for the third type pachinko gaming machine and other ball game machines.

  FIG. 1 is a front view of a game board of a pachinko gaming machine P in the first embodiment. Around the game board 1, there are provided a plurality of winning holes 2 through which 5 to 15 game balls are paid out by winning a hit ball. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying symbols as a plurality of types of identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction, and in each of the three divided display areas, symbols are displayed in a variable manner.

  Below the LCD display 3 is provided a symbol operating gate (first type starting port) 4, and when the hit ball passes through the symbol operating gate 4, the above-described variation display of the LCD display 3 is started. Below the symbol operation gate 4, a specific winning opening (large winning opening) 5 is provided. The specific winning opening 5 is a big hit when the display result after the fluctuation of the LCD display 3 coincides with one of the predetermined symbol combinations, so that the hitting ball is easy to win for a predetermined time (for example, 30 It is a winning opening that is opened (until the second elapses or 10 hitting balls are won). A V zone 5a is provided in the specific winning opening 5, and when the hit ball passes through the V zone 5a while the specific winning opening 5 is opened, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of hit balls win the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (special game state). is there.

  FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine P. As shown in FIG. The control unit C of the pachinko gaming machine P includes a CPU 11 that is an arithmetic device, a ROM 12 that stores various control programs executed by the CPU 11 and fixed value data, and a memory that temporarily stores various data and the like. The RAM 13 is provided. The programs of the flowcharts shown in FIGS. 3 to 5 are stored in the ROM 12 as a part of the control program.

  The CPU 11 includes an ALU that performs arithmetic operations, an accumulator (hereinafter referred to as “Acc”) 11a, a plurality of internal registers 11b, and a flag register 11c. The values of the counter and the like provided in the RAM 13 are once loaded (written) into the internal register 11b of the CPU 11, updated in the internal register 11b, and then saved (written) into the original counter of the RAM 13. Updated).

  The 68-system 8-bit CPU 11 saves (writes) the value of the paired 2-byte (16-bit) internal register 11b to the 2-byte memory (in the RAM 13) of consecutive addresses with one instruction. be able to. Writing in this case is performed in the order of the upper byte and the lower byte since the data bus of the bus line 14 is composed of 8 bits. On the other hand, in the 80 system 8-bit CPU, in contrast to the 68 system CPU 11, the paired 2-byte (16-bit) internal register value is transferred to the 2-byte memory at the continuous address. It can be saved with one instruction in the order of bytes.

  The RAM 13 includes a random number counter 13a, an initial value counter 13b, and an initial value memory 13c. The random number counter 13a is a counter for determining the occurrence of a jackpot, and is updated by 1 count every 2 ms in the range of “0 to 630 (0 to 276h)” by the random number update process (S7) of FIG. The Therefore, the random number counter 13a is composed of 2 bytes. If the value of the random number counter 13a acquired when the hit ball passes the symbol operating gate 4 is, for example, “7”, a big hit occurs. When the jackpot occurs, a jackpot command is sent from the control unit C to the display device D described later. The display device D controls the variable display on the LCD display 3 to the jackpot state based on the jackpot command.

  The initial value counter 13b is a counter for counting the initial value of the update of the random number counter 13a, and is composed of 2 bytes like the random number counter 13a. The value of the initial value counter 13b is updated by one count in the range of “0 to 630 (276h)” that is the same as the update range of the random number counter 13a by the initial value counter update processing (S6, S22) of FIG. .

  The initial value counter update process of FIG. 5 is repeated during the remaining time in the reset interrupt process of FIG. 3, that is, after the end of the sound effect process (S20) until the next reset interrupt process occurs. It is executed (S22). The reset interrupt process is executed every 2 ms, but the processing time of each process from S1 to S20 executed in one reset interrupt process changes depending on the game situation, so the rest of the reset interrupt process The time is not a fixed time but an indefinite time that changes according to the game situation. Since the “hanging board” cannot grasp the indefinite time, the value of the initial value counter 13b that is repeatedly updated within the indefinite time is used as the initial value for updating the random number counter 13a. It is impossible to grasp the timing of jackpot occurrence by “substrate”.

  As will be described later with reference to FIG. 5, the value of the initial value counter 13b is updated via the internal register 11b of the CPU 11. Writing from the internal register 11b to the initial value counter 13b is performed in the order of upper byte and lower byte by one instruction of the 68-system CPU 11. Therefore, for example, when the value of the initial value counter 13b before the update is “1FFh”, the value after the update is updated to “200h” in the internal register 11b, and then the updated value is transferred to the initial value counter 13b in the order of the upper byte and the lower byte. It is written (S45). That is, the value of the initial value counter 13b is temporarily changed to "2FFh" when the upper byte of the internal register 11b is written from the state of "1FFh", and then the lower byte of the internal register 11b is written and updated to "200h". It is done.

  However, since the initial value counter update process of FIG. 5 is repeatedly executed during the remaining time of the reset interrupt process, the upper byte of the updated internal register 11b is written to the initial value counter 13b and the internal register Before the lower byte of 11b is written (during the process of S45), the next reset interrupt process may occur. A reset interrupt is a non-maskable interrupt that cannot inhibit the generation of an interrupt, and has the highest interrupt priority, and is forcibly started even during the execution of an instruction of the CPU 11 It is. Therefore, when a reset interrupt occurs at this timing (after writing the upper byte of the updated internal register 11b to the initial value counter 13b and before writing the lower byte of the internal register 11b), the initial value counter 13b The value of may become “767 (2FFh)” exceeding the range of “0 to 630 (0 to 276h)” which is the original update range.

  Since the update range of the value of the random number counter 13a is also “0 to 630 (0 to 276h)”, if the value (767 (2FFh)) of the initial value counter 13b is set as the initial value of the random number counter 13a, the update cycle of the random number counter 13a Fluctuates and the probability of jackpot occurrence becomes a probability different from the set value, or the initial value of update of the random number counter 13a cannot be changed thereafter. In the random number update process (S7) of FIG. 4, since the value of the random number counter 13a cannot exceed “631 (277h)” (S33: Yes, S34), the value is once out of the range of updating of the random number counter 13a. When a value equal to or greater than “631 (277h)” is written to the initial value memory 13c as an initial value for updating the random number counter 13a (S36, S37), the branch of Yes cannot occur thereafter in the processing of S35. Because.

  Here, the value of the initial value counter 13b is written as an initial value to the random number counter 13a in the random number update process (S36 to S38 of S7). On the other hand, the value of the initial value counter 13b that is outside the original update range is returned to a value within the original update range by performing the initial value counter update process in FIG. 5 again. This is because the value of the initial value counter 13b equal to or greater than “631 (277h)” is cleared to “0” (S43: Yes, S44, S45). Therefore, in this embodiment, in order to avoid the occurrence of the above problem, the initial value counter update process of FIG. 5 is not only repeatedly executed during the remaining time of the reset interrupt process (S22), but also the random number update process. It is executed at least once before the execution of (S7) (S6).

  The initial value memory 13c is a memory for storing an initial value of update of the random number counter 13a, and is composed of 2 bytes like the random number counter 13a. In this embodiment, the initial value of the update of the random number counter 13a is changed every time the random number counter is updated once. Therefore, when the updated value of the random number counter 13a matches the value of the initial value memory 13c, one round of updating of the random number counter 13a is completed, so that when the two values 13a and 13c match, The initial value counter 13b is written into the random number counter 13a and the initial value memory 13c, and the initial value of the update of the random number counter 13a is changed. Therefore, even if the initial value of the update of the random number counter 13a is changed, the randomness is uniform (the same value is not obtained when continuously acquired, and all values can be extracted with the same probability). A random value can be obtained.

  The CPU 11, ROM 12, and RAM 13 are connected to each other via a bus line 14, and the bus line 14 is also connected to an input / output port 15. The input / output port 15 is connected to the display device D and other input / output devices 16. The control unit C sends operation commands to the display device D and other input / output devices 16 via the input / output port 15 and controls these devices. The fluctuation display of the LCD display 3 and the opening / closing operation of the specific winning opening 5 are also controlled based on this operation command.

  The display device D includes a CPU 21, a program ROM 22, a work RAM 23, a video RAM 24, a character ROM 25, an image controller 26, an input / output port 27, and the LCD display 3. The CPU 21 of the display device D performs display control (variable display) of the LCD display 3 in accordance with an operation command output from the control unit C. The program executed by the CPU 21 is stored in the program ROM 22. Has been. The work RAM 23 is a memory that stores work data used when the CPU 21 executes a program.

  The video RAM 24 is a memory for storing data to be displayed on the LCD display 3, and the display content of the LCD display 3 is changed by rewriting the content of the video RAM 24. That is, the variable display of the symbols in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 adjusts the timings of the CPU 21, the video RAM 24, and the input / output port 27, intervenes in reading and writing data, and displays display data stored in the video RAM 24 at a predetermined timing with reference to the character ROM 25. It is displayed on the LCD display 3.

  Next, each process executed by the pachinko gaming machine P configured as described above will be described with reference to the flowcharts of FIGS. FIG. 3 is a flowchart of reset interrupt processing executed every 2 ms in the control unit C of the pachinko gaming machine P. The main control of the pachinko gaming machine P is executed by this reset interrupt process.

  In the reset interrupt process, first, a stack pointer is set (S1), and a pattern written in a predetermined area of the RAM 13 is checked (S2). If the predetermined pattern is written in the predetermined area as a result of the check, the RAM 13 is normal and normal (S2: normal), and the process proceeds to S3. On the other hand, if the predetermined pattern is not written in the predetermined area as a result of the check in S2, it is the reset interrupt process executed first after the power is turned on, or there is an abnormality in the RAM 13 (S2: abnormal) In this case, the process proceeds to S23, the contents of the RAM 13 are once cleared, the initial value is written into the RAM 13 (S23), and the next reset interrupt process is awaited.

  In the process of S3, a timer interrupt is set (S3). The timer interrupt set here includes a timer interrupt that generates a strobe signal for transmitting a command for controlling the display of the LCD display 3 to the display device D. After setting the timer interrupt, each interrupt is permitted (S4). After the interruption is permitted, the output data updated in the previous reset interruption process is processed at a time by the special symbol variation process (S16), the display data creation process (S18), the ramp / information processing (S19), etc. A port output process for outputting to the port is executed (S5). Thereafter, an initial value counter update process (S6) described later is executed to update the initial value counter 13b by "+1" in the addition direction, and a random number update process (S7) is executed to set the value of the random number counter 13a to " +1 "is updated, and storage timer subtraction processing is executed (S8). The storage timer subtraction process shortens the symbol variation display time when there is a predetermined number or more of reserved balls for jackpot determination and when the symbol display is being displayed on the LCD display 3.

  In the switch reading process (S9), the value of each switch is read to win the winning ball 2 and the big winning port 5 (including the V zone 5a) of the ball that has been driven into the game area 1, This is a process for detecting passing, and also winning balls and rental balls. The count abnormality monitoring process (S10) is a process for monitoring whether or not there is an abnormality in the switch data read by the switch reading process of S9. For example, even though the big winning opening 5 is opened and a hit ball is detected by the V count switch that detects the passing of the hit ball through the V zone 5a, the winning in the big winning openings 5 other than the V zone 5a is detected 10 If a single shot cannot be detected by the count switch, some abnormality has occurred in the 10 count switch, for example, by removing the 10 count switch. Further, when a single prize ball is not paid out even though the motor for paying out a prize ball is driven, some abnormality has occurred in the prize ball payout device. Thus, in the count abnormality monitoring process (S10), the presence or absence of the abnormality as described above is monitored based on the switch data read by the switch reading process (S9).

  In the symbol counter update process (S11), a counter update process for determining a symbol to be stopped and displayed as a result of the variable display performed on the LCD display 3 is performed. Further, in the symbol check process (S12), based on the counter value updated in the symbol counter update process (S11), the jackpot symbol, the off symbol, and the reach symbol used in the special symbol variation process (S16). Etc. are determined.

  If no error has occurred in the processing from S3 to S12 (S13: normal), the normal symbol variation processing (S14) displays the variation of the 7-segment LED, and the variation display results in a win. In this case, a hit process for releasing a normal electric accessory (not shown) for a predetermined time is executed. Thereafter, the state flag is checked (S15), and if the symbol variation display on the LCD display 3 is being displayed (S15: symbol variation), the timing at which the hit ball passes the symbol operating gate 4 by the special symbol variation processing (S16). On the basis of the value of the random number counter 13a read in step (b), it is determined whether or not a big hit is made, and a display symbol variation process on the LCD display 3 is executed. On the other hand, if the result of checking the status flag is a big hit (S15: big hit), a big hit process (S17) such as opening the big prize opening 5 is executed. Further, as a result of checking the status flag, if the pattern is neither fluctuating nor big hit (S15: Other), the process of S16 and S17 is skipped and the process proceeds to the display data creation process of S18. If an error is confirmed in the process of S13 (S13: error), each process of S14 to S17 is skipped and the process proceeds to a display data creation process of S18.

  In the display data creation process (S18), demo data displayed on the LCD display 3, display data of the 7 segment LED, and the like are created in addition to the symbol variation display. In the lamp / information processing (S19), the lamp of the holding ball is displayed. Various lamp data including data are created. In the sound effect process (S20), sound effect data corresponding to the game situation is created. These display data and sound effect data are output to each device by the port output process (S5) and the timer interrupt process described above.

  After the sound effect processing (S20) ends, during the remaining time until the next reset interrupt processing occurs, the symbol counter update processing (S21), which is the same processing as S11, is the same processing as S6. The initial value counter update process (S22) is repeatedly executed. Since the execution time of each process of S1-S20 changes according to the state of the game, the remaining time until the next reset interrupt process occurs is not a fixed time but changes according to the state of the game. Therefore, by repeatedly executing the symbol counter update process (S21) using the remaining time, the stop symbol can be changed at random. Further, by repeatedly executing the initial value counter updating process (S22) using the remaining time, the value of the initial value counter 13b serving as the initial value of the update of the random number counter 13a cannot be grasped by the “hanging board”. can do.

  FIG. 4 is a flowchart of random number update processing. In the random number update process (S7), the value of the random number counter 13a is updated by “+1” within the range of “0 to 630 (0 to 276h)” via the internal register 11b of the CPU 11 and used by the control unit C. There are other random number updates.

  First, the value of the random number counter 13a composed of 2 bytes is written to the 2-byte internal register 11b (S31). The value of the internal register 11b is incremented by 1 (S32), and it is checked whether or not the value of the internal register 11b after the addition is “631” or more, that is, whether or not the update range value of the random number counter 13a is exceeded. (S33). If the value of the internal register 11b after the addition is “631” or more (S33: Yes), the value of the internal register 11b is cleared to “0” because it exceeds the update range value (S34). On the other hand, if the value of the internal register 11b after addition is “630” or less (S33: No), the value is within the update range, so the process of S34 is skipped and the process proceeds to S35.

  In the process of S35, the updated value of the internal register 11b is compared with the value of the initial value memory 13c. Since the initial value of the update of the random number counter 13a is stored in the initial value memory 13c, when both values are equal (S35: Yes), the update of the random number counter 13a is completed once. Therefore, in such a case, the value of the 2-byte initial value counter 13b is written to the internal register 11b (S36), and the value of the internal register 11b is written to the initial value memory 13c and the random number counter 13a (S37, S38). The initial value for updating the random number counter 13a is changed.

  On the other hand, when the updated value of the internal register 11b is not equal to the value of the initial value memory 13c (S35: No), the update of the random number counter 13a has not been completed yet, so the processes of S36 and S37 are performed. Is skipped, the value of the internal register 11b updated in the processing from S32 to S34 is written to the random number counter 13a (S38), and the random number counter 13a is updated. Thereafter, another random number update process used in the control unit C is performed (S39), and this random number update process is terminated.

  FIG. 5 is a flowchart of the initial value counter update process. In the initial value counter update processing (S6, S22), the value of the initial value counter 13b that counts the initial value of the update of the random number counter 13a is set via the internal register 11b of the CPU 11 to "0 to" 0 of the update range of the random number counter 13a. "+1" in the range of "630 (0 to 276h)".

  First, the value of the initial value counter 13b composed of 2 bytes is written to the 2-byte internal register 11b (S41). The value of the internal register 11b is incremented by 1 (S42), and it is checked whether or not the value of the internal register 11b after the addition is “631” or more, that is, whether or not the update range of the random number counter 13a is exceeded. (S43). If the value of the internal register 11b after the addition is “631” or more (S43: Yes), it exceeds the update range value of the random number counter 13a, so the value of the internal register 11b is cleared to “0” (S44). . On the other hand, if the value of the internal register 11b after addition is “630” or less (S43: No), the value is within the update range of the random number counter 13a, so the process of S44 is skipped and the process proceeds to S45. To do.

  In the process of S45, the 2-byte write instruction of the 68-system CPU 11 writes the value of the 2-byte internal register 11b to the initial value counter 13b in the order of the upper byte and the lower byte with one instruction (S45). The counter 13b is updated. In the 80-series CPU, the updated 2-byte internal register value is written to the initial value counter 13b by 2 instructions in order of the upper byte and the lower byte, one byte at a time.

  As described above, the initial value counter update process is repeatedly executed during the remaining time until the next reset interrupt occurs in the reset interrupt process (S22). Therefore, in the process of S45, when the next reset interrupt occurs after the upper byte of the internal register 11b is written to the initial value counter 13b and before the lower byte is written, the value of the lower byte of the internal register 11b 3 is executed without writing to the initial value counter 13b.

  For example, if the value of the initial value counter 13b is “1FFh”, the value of the internal register 11b is set to “200h” by the processing of S41 to S44. When the upper byte of the internal register 11b is written to the initial value counter 13b by the processing of S45, the value of the initial value counter 13b once becomes “2FFh”, which is outside the update range of the random number counter 13a. Originally, immediately after that, the lower byte of the internal register 11b is written to the initial value counter 13b, and the value of the initial value counter 13b becomes "200h". As described above, before the lower byte is written. When the next reset interrupt occurs, writing of the lower byte is stopped, and the value of the initial value counter 13b remains “2FFh”.

  If the value of the initial value counter 13b is used in the process of S36 of the random number update process (S7), the initial value of the update of the random number counter 13a is set to a value outside the update range. However, in this embodiment, since the initial value counter update process is executed before the random number update process (S7) (S6), the value of the initial value counter 13b is outside the update range of the random number counter 13a. Even when the value is reached, the value can be returned to a value within the update range of the random number counter 13a before the random number update process (S7). This is because in the initial value counter update process, the value “631” or more is cleared to “0” (S43: Yes, S44). Therefore, the value of the random number counter 13a can always be updated within a predetermined update range.

  Further, as in this embodiment, the initial value counter update process is executed not only in the remaining time (S22) but also before the random number update process (S7) (S6), so that the remaining time is insufficient. However, the initial value counter 13b can be reliably updated.

  FIG. 6 is a flowchart of the initial value counter update process in the second embodiment. The initial value counter updating process of the first embodiment updates the value of the initial value counter 13b by “+1” in the addition direction, and writes the updated values to the initial value counter 13b in the order of the upper byte and the lower byte. On the other hand, in the initial value counter update process of the second embodiment, the value of the initial value counter 13b is updated by “−1” in the subtraction direction, and the updated values are transferred to the initial value counter 13b in the order of lower byte and higher byte. I am writing. In addition, the same code | symbol is attached | subjected to the part same as the above-mentioned 1st Example, and the description is abbreviate | omitted.

  First, the value of the initial value counter 13b composed of 2 bytes is written to the 2-byte internal register 11b (S51). The value of the internal register 11b is decremented by 1 (S52), and it is checked whether or not the value of the internal register 11b after the subtraction is “631 (277h)” or more (S53). If the value of the internal register 11b before subtraction is “0”, the value becomes “0FFFFh” by subtraction. Therefore, if the value of the internal register 11b after the subtraction is equal to or greater than “631 (277h)” including “0FFFFh” (S53: Yes), “630 (276h)” which is the maximum value of the update range of the random number counter 13a. Is written to the internal register 11b (S54). On the other hand, if the value of the internal register 11b after the subtraction is equal to or less than “630 (276h)” (S53: No), the process of S54 is skipped and the process proceeds to S55.

  In the process of S55, the lower byte value of the 2-byte internal register 11b updated in the subtraction direction is written to the lower byte of the 2-byte initial value counter 13b (S55), and then the upper byte of the 2-byte internal register 11b. The byte value is written into the upper byte of the 2-byte initial value counter 13b (S56). That is, the updated value of the 2-byte internal register 11b is written to the initial value counter 13b by two instructions in order of the lower byte and the upper byte, one byte at a time. In the 80-series CPU, a 2-byte write instruction can be used to write a 2-byte internal register value to the initial value counter 13b in the order of lower byte and upper byte.

  As described above, the initial value counter update process is repeatedly executed during the remaining time until the next reset interrupt occurs in the reset interrupt process (S22). For this reason, the next reset interrupt may occur after the lower byte of the internal register 11b is written to the initial value counter 13b by the process of S55 and before the upper byte is written by the process of S56. Since the reset interrupt has the highest interrupt priority and is a non-maskable interrupt that cannot inhibit the start of the interrupt process, in this case, the initial value counter update process is performed without performing the process of S56. The process is forcibly terminated, and the process of S1 in FIG. 3 is executed. As a result, the value during writing becomes the updated value of the initial value counter 13b.

  For example, when the value of the initial value counter 13b is “200h”, the value of the internal register 11b of the CPU 11 is updated to “1FFh” by the processing from S51 to S53. Since the updated value is written from the internal register 11b to the initial value counter 13b in the order of the lower byte upper byte, the value of the initial value counter 13b once becomes “2FFh” by writing the lower byte (S55), and then the upper byte. Is set to “1FFh” (S56), and the update of the initial value counter 13b is completed. Therefore, if the next reset interrupt occurs after writing to the lower byte of the initial value counter 13b and before writing to the upper byte, the value of the initial value counter 13b becomes “2FFh”, and the original update range The value is out of the range of “0 to 630 (0 to 276h)”.

  If the value of the initial value counter 13b is used in the process of S36 of the random number update process (S7), the initial value of the update of the random number counter 13a is set to a value outside the update range. However, in this embodiment, since the initial value counter update process is executed before the random number update process (S7) (S6), the value of the initial value counter 13b is outside the update range of the random number counter 13a. Even when the value is reached, the value can be returned to a value within the update range of the random number counter 13a before the random number update process (S7). This is because in the initial value counter update process, a value greater than “631 (277h)” is returned to “630 (276h)”, which is the maximum value of the update range of the random number counter 13a (S53: Yes, S54). Therefore, the value of the random number counter 13a can always be updated within a predetermined update range.

  In each of the above embodiments, the regular processing according to claim 1 corresponds to the processing from S1 to S20 in the non-maskable reset interrupt processing, and the predetermined processing corresponds to the processing from S21 and S22. The first update means corresponds to the processes from S31 to S34 and S38 of the random number update process (S7) in FIG. Also, the second update means corresponds to the initial value counter update process of S6 and S22, and the change means corresponds to the processes of S35 to S38.

  The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be easily made without departing from the spirit of the present invention. It can be guessed.

  For example, in this embodiment, the initial value counter update process (S6) is executed before the random number update process (S7) for updating the random number counter 13a, and the value of the initial value counter 13b is changed to the update range of the random number counter 13a. It was reset to the value in. However, the method is not necessarily limited to such a method. For example, before writing the value of the initial value counter 13b into the random number counter 13a and the initial value memory 13c (before the processing of S36), the value of the initial value counter 13b is changed. If the value is “631” or more outside the update range of the random number counter 13a, “0” or “630” is written to the initial value counter 13b, and the value of the initial value counter 13b is set to the random number counter 13a. It is also possible to restore the value within the update range and write the restored value to the random number counter 13a and the initial value memory 13c.

  The value of the initial value counter 13b is updated after it is once read into the internal register 11b of the CPU 11. However, the initial value counter 13b is read and updated directly into the ALU in the CPU 11 without going through the internal register 11b. May be.

  The modification of this invention is shown below. 3. The bullet ball game machine according to claim 1, wherein the return means includes third update means for updating the value of the initial value counter with a value within the range of update of the random number counter, The bullet ball game machine 1 is characterized in that the three update means are executed at least once before the execution of the first update means.

  2. The ball game machine or the ball game machine 1 according to claim 1, wherein writing of the updated value by the second updating means to the initial value counter is performed by writing two bytes in order of the upper byte and the lower byte. 1. A bullet ball game machine 2 which is executed by a write command executed in

  3. The ball game machine or the ball game machine 1 or 2 according to claim 1 or 2, wherein the value of the initial value counter is the random number when the value of the random number counter matches the value of the initial value memory. A bullet ball game machine 3 which is written in a counter and an initial value memory.

1 is a front view of a gaming board of a pachinko gaming machine that is a first embodiment of the present invention. It is the block diagram which showed the electrical structure of the pachinko gaming machine. It is the flowchart which showed the reset interruption process. It is the flowchart which showed the random number update process. It is the flowchart which showed the initial value counter update process. It is the flowchart which showed the initial value counter update process of 2nd Example.

11 CPU of control unit
11b Internal register of CPU of control unit 13 RAM of control unit
13a Random number counter 13b Initial value counter 13c Initial value memory C Control unit (control means)
P Pachinko machine ( bullet ball machine)

Claims (2)

A random number counter; first update means for updating the value of the random number counter within a predetermined range; and reading means for reading the value of the random number counter based on a predetermined trigger. In the ball game machine provided with a control means for giving a predetermined game value to the player when the value of the random number counter matches a predetermined value,
The value of the random number counter goes around by being updated a predetermined number of times by the first updating means,
When the value of the random number counter makes a round, the first update unit updates the next round using any value within the predetermined range as an initial value of the update,
The control means includes
Change means for changing the initial value of the update of the first update means each time the value of the random number counter goes around,
An initial value counter that is updated in the same range as the predetermined range and used by the changing means to change an initial value;
Second updating means for updating the value of the initial value counter,
Perform periodic processing based on a periodic interrupt signal, and repeatedly perform predetermined processing in the period until the next periodic processing is performed after the end of the periodic processing,
In the predetermined process and the regular process, the update by the second update unit is performed,
The update of the random number counter by the first update means is performed in the regular processing,
The initial value counter is updated by the second update means before the random number counter is updated by the first update means for the first time after power-on,
Even when the random number counter is updated by the first updating unit after the initial value counter is updated by the second updating unit in the predetermined process, The bullet ball game machine, wherein the initial value counter is updated by the second updating means before the random number counter is updated by one updating means. The bullet ball gaming machine, pinball game machine according to claim 1, characterized in that it is a pachinko machine.

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