JP4626639B2 - Bullet ball machine - Google Patents

Description

The present invention is related to shall in pinball game machine typified pachinko machines.

For example, a pachinko gaming machine is provided with a display device capable of variably displaying a plurality of types of symbols, and is configured to start variably displaying when a hit ball that has been driven into the game area passes through a symbol operating gate. When the variation display stops matches the symbol combination predetermined become jackpot, predetermined game value Ru is provided to the player.

Whether or not the jackpot is generated is determined at the timing when the hit ball passes the symbol operating gate. That is, a counter that is periodically updated in a certain range by one count (for example, by 1 count every 2 ms, in a range of 0 to 630) is provided when the hit ball passes the symbol operation gate. When the value of the read counter matches a predetermined value such as “7”, a jackpot is generated .

However, recently, fraudulent activity using an illegal substrate called “hanging substrate” has been reported. This fraud, unauthorized hanging board (attach the incorrect "hanging board"), is that to generate unduly jackpot. Specifically, a counter (counter that is periodically updated within a certain range) in the “hanging board” is operated in the same manner as the counter for determining the jackpot provided in the pachinko gaming machine. The counter is reset (cleared to 0) when the pachinko gaming machine is powered on, etc., and the occurrence timing of the jackpot in the “hanging board” is grasped. And, in accordance with the grasping timing of the big jackpot, illegally generate the symbol action gate passing signal of the hitting ball in the “hanging board” and output it to the control board of the pachinko machine to generate an unfair jackpot It is to let you .

The present invention has been made to solve the above illustrated problem or the like, and aims to provide a ball-shooting game machine capable of preventing fraud with "hanging board" or the like.

Ball-shooting game machine according to claim 1, wherein in order to achieve this purpose, the random number based and random number counter, a first updating means for updating the value of the random number counter within a predetermined range, the predetermined trigger and a reading means for reading the value of the counter, the control means for imparting to Yu technique's the game value Jo Tokoro when the value of the random number counter read by the reading means coincides with a predetermined value The value of the random number counter is updated once by the first updating unit, and the first updating unit is within the predetermined range when the value of the random number counter is rotated once. Any one of the above values is used as an initial value for updating, and the next round is updated, and the control means is updated in the same range as the predetermined range and used to change the initial value for updating the random number counter. Initial value counter and A second updating means for updating the value of the initial value counter; and a determining means for determining whether or not the data in the storage means including the random number counter and the initial value counter is valid after the ball game machine is powered on; A game executing means for executing a game using the data of the storage means when determined to be valid by the determining means, and an initial data of the storage means when determined not effective by the determining means Initialization processing means for performing periodic processing based on a periodic interrupt signal, and performing predetermined processing repeatedly during the period until the next periodic processing is performed after the end of the periodic processing In the predetermined process, updating by the second updating unit is performed, and the second updating unit is configured such that even when the value of the initial value counter is a value outside the predetermined range, And updates the correction can the value of the initial value counter to a value within the range of the constant.

The bullet ball game machine according to claim 2 is the ball ball game machine according to claim 1, wherein the ball ball game machine is a pachinko game machine.

According to the bullet ball game machine of the present invention, there is an effect that it is possible to prevent an illegal act caused by a “hanging board” or the like.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the present embodiment, description will be made using a pachinko gaming machine as an example of a ball game machine, in particular, a first type pachinko gaming machine. Of course, it is possible to use the present invention for the third type pachinko gaming machine and other ball game machines.

  FIG. 1 is a front view of a game board of a pachinko gaming machine P in the first embodiment. Around the game board 1, there are provided a plurality of winning holes 2 through which 5 to 15 game balls are paid out by winning a hit ball. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying symbols as a plurality of types of identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction, and in each of the three divided display areas, symbols are displayed in a variable manner.

  Below the LCD display 3 is provided a symbol operating gate (first type starting port) 4, and when the hit ball passes through the symbol operating gate 4, the above-described variation display of the LCD display 3 is started. Below the symbol operation gate 4, a specific winning opening (large winning opening) 5 is provided. The specific winning opening 5 is a big hit when the display result after the fluctuation of the LCD display 3 coincides with one of the predetermined symbol combinations, so that the hitting ball is easy to win for a predetermined time (for example, 30 It is a winning opening that is opened (until the second elapses or 10 hitting balls are won). A V zone 5a is provided in the specific winning opening 5, and when the hit ball passes through the V zone 5a while the specific winning opening 5 is opened, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of hit balls win the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (special game state). is there.

  FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine P. As shown in FIG. The control unit C of the pachinko gaming machine P includes a CPU 11 that is an arithmetic device, a ROM 12 that stores various control programs executed by the CPU 11 and fixed value data, and a memory that temporarily stores various data and the like. The RAM 13 is provided. The programs of the flowcharts shown in FIGS. 3 to 5 are stored in the ROM 12 as a part of the control program.

  The CPU 11 includes an ALU that performs arithmetic operations, an accumulator (hereinafter referred to as “Acc”) 11a, a plurality of internal registers 11b, and a flag register 11c. The values of the counter and the like provided in the RAM 13 are once loaded (written) into the internal register 11b of the CPU 11, updated in the internal register 11b, and then saved (written) into the original counter of the RAM 13. Updated).

  The 68-system 8-bit CPU 11 saves (writes) the value of the paired 2-byte (16-bit) internal register 11b to the 2-byte memory (in the RAM 13) of consecutive addresses with one instruction. be able to. Writing in this case is performed in the order of the upper byte and the lower byte since the data bus of the bus line 14 is composed of 8 bits. On the other hand, in the 80 system 8-bit CPU, in contrast to the 68 system CPU 11, the paired 2-byte (16-bit) internal register value is transferred to the 2-byte memory at the continuous address. It can be saved with one instruction in the order of bytes.

  The RAM 13 includes a random number counter 13a, an initial value counter 13b, and an initial value memory 13c. The random number counter 13a is a counter for determining the occurrence of a jackpot, and is updated by 1 count every 2 ms in the range of “0 to 630 (0 to 276h)” by the random number update process (S6) of FIG. The Therefore, the random number counter 13a is composed of 2 bytes. If the value of the random number counter 13a acquired when the hit ball passes the symbol operating gate 4 is, for example, “7”, a big hit occurs. When the jackpot occurs, a jackpot command is sent from the control unit C to the display device D described later. The display device D controls the variable display on the LCD display 3 to the jackpot state based on the jackpot command.

  The initial value counter 13b is a counter for counting the initial value of the update of the random number counter 13a, and is composed of 2 bytes like the random number counter 13a. The value of the initial value counter 13b is updated one count at a time in the range of “0 to 630 (276h)” that is the same as the update range of the random number counter 13a by the initial value counter update process (S21) of FIG.

  The initial value counter update process of FIG. 5 is repeated during the remaining time in the reset interrupt process of FIG. 3, that is, after the sound effect process (S19) ends and until the next reset interrupt process occurs. It is executed (S21). The reset interrupt process is executed every 2 ms, but the processing time of each process from S1 to S19 executed in one reset interrupt process changes depending on the game situation, so the rest of the reset interrupt process The time is not a fixed time but an indefinite time that changes according to the game situation. Since the “hanging board” cannot grasp the indefinite time, the value of the initial value counter 13b that is repeatedly updated within the indefinite time is used as the initial value for updating the random number counter 13a. It is impossible to grasp the timing of jackpot occurrence by “substrate”.

  As will be described in detail with reference to FIG. 5, the value of the initial value counter 13b is updated by the initial value counter updating process (S21) as follows. That is, the value of the initial value counter 13b is once read into the internal register 11b of the CPU 11, and 1 is added and updated in the internal register 11b. The updated value is written from the internal register 11b to the initial value counter 13b in the order of the lower byte and the upper byte, whereby the value of the initial value counter 13b is updated.

  This initial value counter update process (S21) is repeatedly executed during the remaining time in the reset interrupt process of FIG. A reset interrupt is a non-maskable interrupt that cannot inhibit the generation of an interrupt, and has the highest interrupt priority, and is forcibly started even during the execution of an instruction of the CPU 11 It is. Therefore, the next reset interrupt may occur while the value updated in the internal register 11b is being written to the initial value counter 13b. In such a case, the initial value counter in which the value being written is updated. It becomes the value of 13b.

  However, since the value updated by the internal register 11b is written to the initial value counter 13b in the order of the lower byte and the upper byte, the next reset interrupt occurs after the lower byte is written and before the upper byte is written. Even if it occurs and the value in the middle of writing becomes the value of the updated initial value counter 13b, the value of the initial value counter 13b is "0 to 630 (0 to 276h)" which is a value within the original update range. Can be maintained within the range.

  For example, the update when the value of the initial value counter 13b is “1FFh” is performed as follows. First, “1FFh”, which is the value of the initial value counter 13b, is written to the internal register 11b of the CPU 11, and 1 is added in the internal register 11b to be updated to “200h”. Since the updated value is written from the internal register 11b to the initial value counter 13b in the order of the lower byte and the upper byte, the value of the initial value counter 13b once becomes “100h” by writing the lower byte, and then the upper byte. By writing, it becomes “200h” and the update is completed. Therefore, even if the next reset interrupt occurs after writing to the lower byte of the initial value counter 13b and before writing to the upper byte, the value of the initial value counter 13b is only updated to “100h”. Therefore, the value is not outside the range of “0 to 630 (0 to 276h)” that is the value of the original update range.

  The initial value memory 13c is a memory for storing an initial value of update of the random number counter 13a, and is composed of 2 bytes like the random number counter 13a. In this embodiment, the initial value of the update of the random number counter 13a is changed every time the random number counter is updated once. Therefore, when the updated value of the random number counter 13a matches the value of the initial value memory 13c, one round of updating of the random number counter 13a is completed, so that when the two values 13a and 13c match, The initial value counter 13b is written into the random number counter 13a and the initial value memory 13c, and the initial value of the update of the random number counter 13a is changed. Therefore, even if the initial value of the update of the random number counter 13a is changed, the randomness is uniform (the same value is not obtained when continuously acquired, and all values can be extracted with the same probability). A random value can be obtained.

  The CPU 11, ROM 12, and RAM 13 are connected to each other via a bus line 14, and the bus line 14 is also connected to an input / output port 15. The input / output port 15 is connected to the display device D and other input / output devices 16. The control unit C sends operation commands to the display device D and other input / output devices 16 via the input / output port 15 and controls these devices. The fluctuation display on the LCD display 3 and the opening / closing operation of the specific winning opening 5 are also controlled based on this operation command.

  The display device D includes a CPU 21, a program ROM 22, a work RAM 23, a video RAM 24, a character ROM 25, an image controller 26, an input / output port 27, and the LCD display 3. The CPU 21 of the display device D performs display control (variable display) of the LCD display 3 in accordance with an operation command output from the control unit C. The program executed by the CPU 21 is stored in the program ROM 22. Has been. The work RAM 23 is a memory that stores work data used when the CPU 21 executes a program.

  The video RAM 24 is a memory for storing data to be displayed on the LCD display 3, and the display content of the LCD display 3 is changed by rewriting the content of the video RAM 24. That is, the variable display of the symbols in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 adjusts the timings of the CPU 21, the video RAM 24, and the input / output port 27, intervenes in reading and writing data, and displays display data stored in the video RAM 24 at a predetermined timing with reference to the character ROM 25. It is displayed on the LCD display 3.

  Next, each process executed by the pachinko gaming machine P configured as described above will be described with reference to the flowcharts of FIGS. FIG. 3 is a flowchart of reset interrupt processing executed every 2 ms in the control unit C of the pachinko gaming machine P. The main control of the pachinko gaming machine P is executed by this reset interrupt process.

  In the reset interrupt process, first, a stack pointer is set (S1), and a pattern written in a predetermined area of the RAM 13 is checked (S2). If the predetermined pattern is written in the predetermined area as a result of the check, the RAM 13 is normal and normal (S2: normal), and the process proceeds to S3. On the other hand, if the predetermined pattern is not written in the predetermined area as a result of the check in S2, it is the reset interrupt process executed first after the power is turned on, or there is an abnormality in the RAM 13 (S2: abnormal) In this case, the process proceeds to S22, the contents of the RAM 13 are once cleared, the initial value is written into the RAM 13 (S22), and the next reset interrupt process is awaited.

  In the process of S3, a timer interrupt is set (S3). The timer interrupt set here includes a timer interrupt that generates a strobe signal for transmitting a command for controlling the display of the LCD display 3 to the display device D. After setting the timer interrupt, each interrupt is permitted (S4). After the permission of the interrupt, the output data updated in the previous reset interrupt process by the special symbol variation process (S15), the display data creation process (S17), the ramp / information processing (S18), etc. A port output process for outputting to the port is executed (S5). After the port output process is executed, a random number update process (S6) described later is executed to update the value of the random number counter 13a by "+1", and a storage timer subtraction process is executed (S7). The storage timer subtraction process shortens the symbol variation display time when there is a predetermined number or more of reserved balls for jackpot determination and when the symbol display is being displayed on the LCD display 3.

  In the switch reading process (S8), the value of each switch is read to win the winning ball 2 and the big winning hole 5 (including the V zone 5a) of the ball that has been driven into the game area 1, This is a process for detecting passing, and also winning balls and rental balls. The count abnormality monitoring process (S9) is a process for monitoring whether there is an abnormality in the switch data read by the switch reading process of S8. For example, even though the big winning opening 5 is opened and a hit ball is detected by the V count switch that detects the passing of the hit ball through the V zone 5a, the winning in the big winning openings 5 other than the V zone 5a is detected 10 When a single shot cannot be detected by the count switch, some abnormality has occurred in the 10 count switch, such as the 10 count switch being pulled out or broken. Further, when a single prize ball is not paid out even though the motor for paying out a prize ball is driven, some abnormality has occurred in the prize ball payout device. As described above, in the count abnormality monitoring process (S9), the presence / absence of the abnormality as described above is monitored based on the switch data read by the switch reading process (S8).

  In the symbol counter update process (S10), a counter update process for determining a symbol to be stopped and displayed as a result of the variable display performed on the LCD display 3 is performed. In the symbol check process (S11), based on the counter value updated in the symbol counter update process (S10), the jackpot symbol, the off symbol, and the reach symbol used in the special symbol variation process (S15). Etc. are determined.

  If no error has occurred in the processing from S3 to S11 (S12: normal), the normal symbol variation processing (S13) displays the variation of the 7-segment LED, and the variation display results in a win. In this case, a hit process for releasing a normal electric accessory (not shown) for a predetermined time is executed. Thereafter, the state flag is checked (S14), and if the change of the symbol on the LCD display 3 is being displayed (S14: changing the symbol), the timing at which the hit ball passes the symbol operation gate 4 by the special symbol change process (S15). On the basis of the value of the random number counter 13a read in step (b), it is determined whether or not a big hit is made, and a display symbol variation process on the LCD display 3 is executed. On the other hand, if the result of checking the status flag is a big hit (S14: big hit), a big hit process (S16) such as opening the big prize opening 5 is executed. Further, as a result of checking the status flag, if the symbol is not changing or big hit (S14: Other), the processing of S15 and S16 is skipped and the process proceeds to the display data creation processing of S17. If an error is confirmed in the process of S12 (S12: error), each process of S13 to S16 is skipped and the process proceeds to a display data creation process of S17.

  In the display data creation process (S17), demo data displayed on the LCD display 3, display data of the 7 segment LED, and the like are created in addition to the symbol variation display. In the lamp / information processing (S18), the lamp of the holding ball is displayed. Various lamp data including data are created. In the sound effect process (S19), sound effect data corresponding to the game situation is created. These display data and sound effect data are output to each device by the port output process (S5) and the timer interrupt process described above.

  After the sound effect process (S19) ends, during the remaining time until the next reset interrupt process occurs, the symbol counter update process (S20), which is the same process as S10, and the initial value counter update process (S21) ) And repeatedly. Since the execution time of each process of S1-S19 changes according to the state of the game, the remaining time until the next reset interrupt process occurs is not a fixed time but changes according to the state of the game. Therefore, by repeatedly executing the symbol counter update process (S20) using the remaining time, the stop symbol can be changed at random. Further, by repeatedly executing the initial value counter updating process (S21) using the remaining time, the value of the initial value counter 13b serving as the initial value of the update of the random number counter 13a cannot be grasped by the “hanging board”. can do.

  FIG. 4 is a flowchart of random number update processing. In the random number updating process (S6), the value of the random number counter 13a is updated by “+1” within the range of “0 to 630 (0 to 276h)” via the internal register 11b of the CPU 11 and used by the control unit C. There are other random number updates.

  First, the value of the random number counter 13a composed of 2 bytes is written to the 2-byte internal register 11b (S31). The value of the internal register 11b is incremented by 1 (S32), and it is checked whether or not the value of the internal register 11b after the addition is “631” or more, that is, whether or not the update range value of the random number counter 13a is exceeded. (S33). If the value of the internal register 11b after the addition is “631” or more (S33: Yes), the value of the internal register 11b is cleared to “0” because it exceeds the update range value (S34). On the other hand, if the value of the internal register 11b after addition is “630” or less (S33: No), the value is within the update range, so the process of S34 is skipped and the process proceeds to S35.

  In the process of S35, the updated value of the internal register 11b is compared with the value of the initial value memory 13c. Since the initial value of the update of the random number counter 13a is stored in the initial value memory 13c, when both values are equal (S35: Yes), the update of the random number counter 13a is completed once. Therefore, in such a case, the value of the 2-byte initial value counter 13b is written to the internal register 11b (S36), and the value of the internal register 11b is written to the initial value memory 13c and the random number counter 13a (S37, S38). The initial value for updating the random number counter 13a is changed.

  On the other hand, when the updated value of the internal register 11b is not equal to the value of the initial value memory 13c (S35: No), the update of the random number counter 13a has not been completed yet, so the processes of S36 and S37 are performed. Is skipped, the value of the internal register 11b updated in the processing from S32 to S34 is written to the random number counter 13a (S38), and the random number counter 13a is updated. Thereafter, another random number update process used in the control unit C is performed (S39), and this random number update process is terminated.

  FIG. 5 is a flowchart of the initial value counter update process. In the initial value counter update process (S21), the value of the initial value counter 13b that counts the initial value of the update of the random number counter 13a is set via the internal register 11b of the CPU 11 to "0 to 630 ( 0 + 1 ”within the range of“ 0 to 276h) ”.

  First, the value of the initial value counter 13b composed of 2 bytes is written to the 2-byte internal register 11b (S41). The value of the internal register 11b is incremented by 1 (S42), and it is checked whether or not the value of the internal register 11b after the addition is “631” or more, that is, whether or not the update range of the random number counter 13a is exceeded. (S43). If the value of the internal register 11b after the addition is “631” or more (S43: Yes), it exceeds the update range value of the random number counter 13a, so the value of the internal register 11b is cleared to “0” (S44). . On the other hand, if the value of the internal register 11b after addition is “630” or less (S43: No), the value is within the update range of the random number counter 13a, so the process of S44 is skipped and the process proceeds to S45. To do.

  In the processing of S45 and S46, the updated value of the internal register 11b is not written in the initial value counter 13b in the order of the upper byte and the lower byte by the 2-byte write command of the 68-system CPU 11, but in the order of the lower byte and the upper byte. Each is written to the initial value counter 13b. That is, first, the updated lower byte value of the 2-byte internal register 11b is written to the lower byte of the 2-byte initial value counter 13b (S45), and then the upper byte value of the 2-byte internal register 11b is written. The data is written into the upper byte of the 2-byte initial value counter 13b (S46). In the 80-series CPU, the value of the internal register can be written to the initial value counter 13b in the order of the lower byte and the upper byte with one instruction by a 2-byte write instruction.

  As described above, the initial value counter update process is repeatedly executed during the remaining time until the next reset interrupt occurs in the reset interrupt process (S21). Therefore, the next reset interrupt may occur after the lower byte of the internal register 11b is written to the initial value counter 13b by the process of S45 and before the upper byte is written by the process of S46. Since the reset interrupt has the highest interrupt priority and is a non-maskable interrupt that cannot prohibit the start of the interrupt process, in this case, the initial value counter update process is performed without performing the process of S46. The process is forcibly terminated, and the process of S1 in FIG. 3 is executed. As a result, the value during writing becomes the updated value of the initial value counter 13b.

  However, since the value updated in the addition direction by the internal register 11b is written to the initial value counter 13b in the order of the lower byte and the upper byte, after the lower byte is written and before the upper byte is written, that is, S45. Even if the next reset interrupt occurs during the processing of S46 and the value in the middle of writing becomes the updated initial value counter 13b, the value of the initial value counter 13b is changed to a value within the original update range. It can be maintained within the range of “0 to 630 (0 to 276 h)”.

  For example, when the value of the initial value counter 13b is “1FFh”, the value of the internal register 11b of the CPU 11 is updated to “200h” by the processing from S41 to S44. Since the updated value is written from the internal register 11b to the initial value counter 13b in the order of the lower byte upper byte, the value of the initial value counter 13b once becomes “100h” by writing the lower byte (S45), and then the upper byte. Is "200h" (S46), and the update of the initial value counter 13b is completed. Therefore, even if the next reset interrupt occurs after writing to the lower byte of the initial value counter 13b and before writing to the upper byte, the value of the initial value counter 13b is only updated to “100h”. Therefore, the value is not outside the range of “0 to 630 (0 to 276h)” that is the value of the original update range.

  Thus, the value of the initial value counter 13b is updated in the range of “0 to 630 (0 to 276h)” that is the value of the original update range and the update range of the random number counter 13a. Even if the value is used as the initial value for updating the random number counter 13a, the value of the random number counter 13a can always be updated within a predetermined update range.

  FIG. 6 is a flowchart of the initial value counter update process in the second embodiment. The initial value counter updating process of the first embodiment updates the value of the initial value counter 13b by “+1” in the addition direction, and writes the updated values to the initial value counter 13b in the order of lower byte and upper byte. On the other hand, in the initial value counter update process of the second embodiment, the value of the initial value counter 13b is updated by “−1” in the subtraction direction, and the updated value is obtained by one instruction of 2-byte writing of the 68-system CPU 11. Are written to the initial value counter 13b in the order of the upper byte and the lower byte. In addition, the same code | symbol is attached | subjected to the part same as above-described 1st Example, and the description is abbreviate | omitted.

  First, the value of the initial value counter 13b composed of 2 bytes is written to the 2-byte internal register 11b (S51). The value of the internal register 11b is decremented by 1 (S52), and it is checked whether or not the value of the internal register 11b after the subtraction is “631 (277h)” or more (S53). If the value of the internal register 11b before subtraction is “0”, the value becomes “0FFFFh” by subtraction. Therefore, if the value of the internal register 11b after the subtraction is equal to or greater than “631 (277h)” including “0FFFFh” (S53: Yes), “630 (276h)” which is the maximum value of the update range of the random number counter 13a. Is written to the internal register 11b (S54). On the other hand, if the value of the internal register 11b after the subtraction is equal to or less than “630 (276h)” (S53: No), the process of S54 is skipped and the process proceeds to S55.

  In the process of S55, the value of the 2-byte internal register 11b updated in the subtraction direction is written to the initial value counter 13b in the order of the upper byte and the lower byte by one instruction of 2-byte write of the 68-system CPU 11 (S55). The value counter update process is terminated. In the 80 series CPU, the value of the internal register of 2 bytes cannot be written in the order of the upper byte and the lower byte by one instruction, so one byte is written in order of the upper byte and the lower byte by two instructions.

  As described above, the initial value counter update process is repeatedly executed during the remaining time until the next reset interrupt occurs in the reset interrupt process (S21). Therefore, the next reset interrupt may occur after the upper byte of the internal register 11b is written to the initial value counter 13b and before the lower byte is written in the process of S55. The reset interrupt has the highest interrupt priority and is a non-maskable interrupt that cannot prohibit the start of interrupt processing. In this case, the lower byte is not written to the initial value counter 13b. The initial value counter update process is forcibly terminated, and the process of S1 in FIG. 3 is executed. As a result, the value during writing becomes the updated value of the initial value counter 13b.

  However, since the value updated in the subtraction direction in the internal register 11b is written to the initial value counter 13b in the order of the upper byte and lower byte, after the upper byte is written and before the lower byte is written, that is, the process of S55 Even if the next reset interrupt occurs and the value during writing becomes the updated initial value counter 13b, the value of the initial value counter 13b is a value within the original update range. 0 to 630 (0 to 276 h) ".

  For example, when the value of the initial value counter 13b is “200h”, the value of the internal register 11b of the CPU 11 is updated to “1FFh” by the processing from S51 to S53. Since the updated value is written from the internal register 11b to the initial value counter 13b in the order of the upper byte and lower byte, the value of the initial value counter 13b once becomes “100h” by writing the upper byte, and then by writing the lower byte. It becomes “1FFh” (S55), and the update of the initial value counter 13b is completed. Therefore, even if the next reset interrupt occurs after writing to the upper byte of the initial value counter 13b and before writing to the lower byte, the value of the initial value counter 13b is only updated to “100h”. Therefore, the value is not outside the range of “0 to 630 (0 to 276h)” that is the value of the original update range.

  FIG. 7 is a flowchart of the initial value counter update process in the third embodiment. In the initial value counter update process of the third embodiment, the method of subtracting the value of the internal register 11b in the initial value counter update process of the second embodiment is changed to reduce the program size and improve the processing speed. In addition, the same code | symbol is attached | subjected to the part same as the above-mentioned 1st and 2nd Example, The description is abbreviate | omitted.

  First, the value of the initial value counter 13b composed of 2 bytes is written to the 2-byte internal register 11b (S61). It is checked whether or not the value of the internal register 11b is “0” (S62). If it is “0” (S62: Yes), “631 (277h), which is the maximum value + 1 of the update range of the random number counter 13a + 1. ] "Is written to the internal register 11b (S63). On the other hand, if the value of the internal register 11b is not “0” (S62: No), the process of S63 is skipped and the process proceeds to S64. In the process of S64, the value of the internal register 11b is decremented by 1 (S64), and then the value of the 2-byte internal register 11b updated in the subtraction direction is converted into a higher order by one instruction of 2-byte write of the 68 system CPU11. Writing to the initial value counter 13b in the order of byte lower bytes (S65), the initial value counter update processing is terminated.

  By updating the value of the initial value counter 13b in the subtraction direction as described above, it is possible to perform processing with a small program size and high speed. Although the initial value counter update process is repeatedly executed during the remaining time of the reset interrupt process, the initial value counter 13b can be sufficiently updated even if the remaining time is small.

In each of the above embodiments, the regular processing described in claim 1 corresponds to the processing in S1 to S19 in FIG. 3, and the predetermined processing corresponds to the processing in S20 and S21 in FIG. The reading means corresponds to the switch reading process (S8) of FIG. The first update means corresponds to the processes from S31 to S34 and S38 of the random number update process (S6) of FIG. 4, and the initial value counter update process (S21) of FIGS. 5 and 6 corresponds to the second update means . . The process of S2 of FIG. 3 corresponds to the determination means, the processes of S3 to S21 of FIG. 3 correspond to the game execution means, and the process of S22 of FIG. 3 corresponds to the initialization means.

  The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be easily made without departing from the spirit of the present invention. It can be guessed.

  For example, the value of the initial value counter 13b is updated after it is once read into the internal register 11b of the CPU 11, but is directly read and updated into the ALU in the CPU 11 without going through the internal register 11b. May be.

  The modification of this invention is shown below. 3. The ball game machine according to claim 2, wherein the value updated by the second updating means is written to the initial value counter by a write command in which 2 bytes are written in one order in the order of the upper byte and the lower byte. A bullet ball game machine 1 characterized by being executed.

  3. The ball game machine or the ball game machine 1 according to claim 1, wherein the value of the initial value counter is equal to the value of the random number counter when the value of the random number counter matches the value of the initial value memory. A ball game machine 2 which is written in an initial value memory.

1 is a front view of a gaming board of a pachinko gaming machine that is a first embodiment of the present invention. It is the block diagram which showed the electrical structure of the pachinko gaming machine. It is the flowchart which showed the reset interruption process. It is the flowchart which showed the random number update process. It is the flowchart which showed the initial value counter update process. It is the flowchart which showed the initial value counter update process of 2nd Example. It is the flowchart which showed the initial value counter update process of 3rd Example.

11 CPU of control unit
13 RAM of Control Unit (Storage Unit )
13a Random number counter 13b Initial value counter 13c Initial value memory C Control unit (control means)
P Pachinko machine (bullet ball machine)

Claims (2)

Has a random number counter, a first updating means for updating the value of the random number counter within a predetermined range, and a reading means for reading the value of the random number counter based on a predetermined trigger, read out by the read means in a ball-shooting game machine having a control means for applying a game value Jo Tokoro in Yu technique's when the value of the random number counter matches with a predetermined value,
The value of the random number counter goes around by being updated a predetermined number of times by the first updating means,
When the value of the random number counter makes a round, the first update unit updates the next round using any value within the predetermined range as an initial value of the update,
The control means includes
An initial value counter that is updated in the same range as the predetermined range and is used to change the initial value of the update of the random number counter;
Second updating means for updating the value of the initial value counter;
A discriminating means for discriminating whether or not the data in the storage means including the random number counter and the initial value counter is valid after the power supply of the ball game machine is turned on;
A game execution means for executing a game using the data in the storage means when determined to be valid by the determination means;
An initialization means for initializing the data in the storage means when it is determined that the determination means is not valid,
Perform periodic processing based on a periodic interrupt signal, and repeatedly perform predetermined processing in the period until the next periodic processing is performed after the end of the periodic processing,
In the predetermined process, the update by the second update means is performed,
The second updating means may adjust the value of the initial value counter so that the value of the initial value counter can be corrected to a value within the predetermined range even when the value of the initial value counter is a value outside the predetermined range. A ball game machine characterized by renewal . 2. The ball game machine according to claim 1, wherein the ball game machine is a pachinko game machine.

Images