JP5083334B2 - Game machine - Google Patents

Description

The present invention relates to Yu technique machine that will be represented by such as a pachinko game machine.

For example, a pachinko gaming machine includes a display device that can display various types of symbols in a variable manner, and is configured to start variable display when a ball that has been driven into the game area passes through the symbol operating port. . When the variation display stops matches the symbol combination predetermined become those Tari, predetermined game value Ru is provided to the player.

Occurrence of such skilled enough, the sphere is determined by the timing of passing through the pattern actuation port. That is, it is provided with a random number counter that is periodically updated in a certain range by 1 count (for example, by 1 count every 2 ms, in the range of 0 to 346). the value of the random number counter (i.e., the random number value) read out, the read random number value, for example, when matching the predetermined value such as "7", and generates an equivalent or.

Recently, however, there have been reports of fraudulent acts using illegal boards called “hanging boards”. This fraud, unauthorized hanging board (attach the incorrect "hanging board"), is intended to unduly generate those or. Specifically, the false random number counter for the same function and a random number counter for determining a person or provided pachinko machine described above (1 count by periodically counter which is updated in a certain range) "hanging provided in the substrate "by resetting (0 cleared) and the combined value of the false random number counter power up or the like of the pachinko gaming machine, to grasp the timing of generation of those have enough in" hanging board ". Then, in accordance with the generation timing of those have enough grasped, the symbol actuation port passing signals of a sphere incorrectly generated in the "hanging board" which was output to the main control board of the pachinko gaming machine, unduly Tari those Is to generate. Amusement halls and the like have suffered a great deal of damage due to fraudulent acts using this “hanging board”.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a gaming machine that can prevent an illegal act by a “hanging board” or the like.

Gaming machine of claim 1, wherein in order to achieve this purpose, a random number counter for repeatedly updating the random number in a predetermined range, and against the random number value is updated with the random number counter, predetermined game to the player Storage means for storing 1-byte data including a predetermined bit indicating whether or not to add value, the bit position of the predetermined bit being changed according to the random number value, at an address relating to the random value; When a determination timing for whether or not to give a predetermined game value to the player has arrived, an address related to the random number value indicated by the random number counter at that time is output to the storage means, and the output address is reading means for reading data of said stored byte from said storage means, identification means for identifying the bit position of the predetermined bit from the data read by the reading means , The bit position specified by the specifying means, check the state of the predetermined bits, and a determination means for determining whether or not to grant the predetermined game value to the player.

According to the gaming machine of the present invention, Ru can prevent abuse by "hanging board" or the like.

It is a front view of the game board of the pachinko game machine which is one Example of this invention. It is the block diagram which showed the electrical structure of the pachinko gaming machine. (A) is the figure which showed the structure of 1 byte of comparison ROM for every bit, (b) is the figure which showed judgment results, such as jackpot by the state of a jackpot bit and a high probability jackpot bit. It is a figure explaining the acquisition (reading) system of the data with respect to the random number value based on the random number value read from a random number counter. It is the flowchart which showed the reset interruption process. It is the figure which showed the structure of 1 byte of the comparison ROM in 2nd Example for every bit. It is the flowchart which showed the reset interruption process in 2nd Example. It is the flowchart which showed the reset interruption process in 3rd Example.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the first embodiment, description will be made using a pachinko gaming machine as an example of a gaming machine, in particular, a first type pachinko gaming machine. Note that it is naturally possible to use the present invention for the third kind pachinko gaming machine and other gaming machines.

  FIG. 1 is a front view of the game board of the pachinko gaming machine P. Around the game board 1, there are provided a plurality of winning holes 2 through which 5 to 15 prize balls are paid out by winning a ball. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying symbols as a plurality of types of identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction, and in each of the three divided display areas, symbols are displayed in a variable manner.

  Below the LCD display 3, a symbol operation port (first type start port) 4 is provided. When the sphere passes through the symbol operating port 4, the above-described variation display on the LCD display 3 is started. Below the symbol operating port 4, a specific winning port (large winning port) 5 is provided. The specific winning opening 5 is a predetermined time (for example, 30 seconds) so that the ball is a big hit and the ball is easy to win when the display result after the fluctuation of the LCD display 3 matches one of the predetermined symbol combinations. It is a winning opening that is opened (until the second elapses or 10 balls are won). A V zone 5a is provided in the specific winning opening 5, and when the ball passes through the V zone 5a while the specific winning opening 5 is opened, a continuation right is established and the specific winning opening 5 is closed. Thereafter, the specific winning opening 5 is opened again for a predetermined time (or until a predetermined number of balls win the specific winning opening 5). The opening / closing operation of the specific winning opening 5 can be repeated up to 16 times (16 rounds), and the state in which the opening / closing operation can be performed is a state in which a predetermined game value is given (special game state). is there.

  FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine P. As shown in FIG. The main control board C of the pachinko gaming machine P includes an MPU 11 that operates based on an operation clock 11a of 8.192 MHz, a ROM 12 that stores various control programs and fixed value data executed by the MPU 11, and an execution of the control program RAM 13 which is a memory for temporarily storing various data sometimes, 16-bit random number counter 14 which counts up at every falling edge of the clock pulse output from the 7.15909 MHz clock 14a, and input / output A port 16 and a comparison ROM 17 that stores predetermined data for the random number value counted by the random number counter 14, that is, data such as whether or not the random value is a big hit. The program shown in the flowchart of FIG. 5 is stored in the ROM 12 as a part of the control program.

  The random number counter 14 is a 16-bit counter that counts up one count at each falling edge of the clock pulse output from the 7.15909 MHz clock 14a. Therefore, the random number counter 14 can update the random number value in the range of “0 to 65535” at a high speed that cannot be followed by software control. When the MPU 11 outputs the lower address of the random number counter 14 and the read signal, the 16-bit count value (random number value) of the random number counter 14 is once latched in the 16-bit output register inside the random number counter 14. The value of the lower byte of the latched random number counter 14 is output to the data bus and read into the MPU 11. Next, when the MPU 11 outputs the upper address of the random number counter 14 and the read signal, the upper byte of the count value (random number value) latched in the output register inside the random number counter 14 when the lower byte of the random number counter 14 is read. Is output to the data bus and read into the MPU 11. In this way, the value of the 16-bit random number counter 14 is read by the MPU 11. In the random number counter 14, the count value is updated based on the clock pulse of the clock 14a even during the reading of the count value. The value of the random number counter 14 is read at the timing when the sphere passes through the symbol operating port 4 and is used for determining the jackpot.

  The count value of the random number counter 14 is not initialized when the power is turned on, and starts counting up from an indefinite value at the time of power on. Therefore, the “hanging board” cannot grasp the indefinite initial value of the random number counter 14, and therefore cannot grasp the count value of the random number counter 14, that is, the random number value. Furthermore, since the random number counter 14 is externally attached to the MPU 11, even if a reset interrupt is applied to the MPU 11 every 2 ms, the count value of the random number counter 14 is not cleared to “0” each time. , Can continue counting. Therefore, a complicated process of storing the count value of the random number counter 14 every time a reset interrupt of the MPU 11 and writing back the stored value to the random number counter 14 is not necessary.

  Here, the relationship between the operation clock 11a of the MPU 11 and the clock 14a of the random number counter 14 will be described. Since the operation clock 11a of the MPU 11 has a frequency of 8.192 MHz, it is possible to obtain an interval of 2 ms for the reset interrupt processing executed by the main control board C with 16,384 clocks. On the other hand, since the clock 14a of the random number counter 14 has a frequency of 7.15909 MHz, an interval of 2 ms for the reset interrupt process cannot be obtained. Specifically, at 14,318 clocks, 1.99997485714 ms, which is less than 2 ms, and at 14,319 clocks, which is one clock higher than that, 2.000114539697 ms, exceeding 2 ms.

  While the game control of the pachinko gaming machine P is performed every 2 ms by the main control board C, the update of the random number value by the random number counter 14 that determines the jackpot cannot obtain the 2 ms interval 7.15909 MHz clock 14a, when the “hanging board” that acts illegally operates in synchronization with the main control board C, the count value (random number value) of the random number counter 14 cannot be grasped. When operating in synchronization with the random number counter 14, it cannot operate in synchronization with the main control board C. Therefore, since the passing signal of the symbol operating port 4 cannot be output from the “hanging board” to the main control board C of the pachinko gaming machine P in accordance with the occurrence timing of the jackpot, illegal acts using the “hanging board” are prevented. can do.

  The comparison ROM 17 is a memory that stores predetermined data for the random number value updated by the random number counter 14, that is, data such as whether or not the random number value is a big hit, for each random value, and the update range of the random number counter 14. It has a size of 64K bytes per minute. The data for the random value is provided for each random value by one byte and is stored at the address of the comparison ROM indicated by the random value. For this reason, the comparison ROM 17 occupies a large address space of “0000h to 0FFFFh”, but is arranged not at the memory address but at the addresses “000Eh” and “000Fh” on the I / O address. Even if the memory has a large size of 64 Kbytes, the comparison ROM 17 does not occupy a 64 Kbyte memory space, and the memory space can be used effectively. The comparison ROM 17 is arranged on the I / O address, so that the comparison ROM 17 is accessed via the input / output port 16.

  FIG. 3A is a diagram showing the configuration of 1-byte data in the comparison ROM 17 for each bit. As shown in FIG. 3A, the 0th bit of the comparison ROM 17 is assigned to the jackpot bit x (17a), the first bit is assigned to the high probability jackpot bit y (17b), and the second bit is assigned to the prime bit z (17c). ing. Depending on the state of each of these bits 17a and 17b, the big hit is determined as shown in FIG. That is, when the jackpot bit x (17a) is “0”, it is a loss (17d) regardless of the state of the high probability jackpot bit y (17b). When the jackpot bit x (17a) is “0”, there is no setting that the high probability jackpot bit y (17b) is “1” (17e). On the other hand, when the jackpot bit x (17a) is “1”, if the high probability jackpot bit y (17b) is “0”, it is a jackpot (17f), and the high probability jackpot bit y (17b) is “ If it is “1”, it is a high probability jackpot (17 g).

  The prime bit z (17c) is a bit indicating that the random number value is a prime number. If the prime bit z (17c) is “1”, the target random number value is a prime number. ", The target random value is not a prime number. In the first embodiment, the prime bit z (17c) is not used for the jackpot determination.

  Here, with reference to FIG. 4, a method for acquiring (reading) predetermined data for a random number value stored in the comparison ROM 17, that is, data for determining whether or not the random value is a jackpot will be described. First, the count value (random number value) of the random number counter 14 is read by the MPU 11 in the order of the lower byte and the upper byte (41), the lower byte of the random value is transferred from the MPU 11 to “000Eh” of the I / O address, The data is output to the I / O address “000Fh” (42). The 16-bit random number value is once latched in the input latch register 16a (16 bits) of the input / output port 16, and is output from the input / output port 16 to the comparison ROM 17 as 16-bit address data (43). Since the lead terminal RD bar of the comparison ROM 17 is grounded and is always active (44), when the address output to the comparison ROM 17 is stabilized, the data for the random number value is read from the comparison ROM 17 (45) and input / output The data is input to the output buffer 16b (8 bits) of the port 16. When the MPU 11 executes a read instruction for the I / O address “000Eh”, the data input to the output buffer 16b is read by the MPU 11 (46), and the data for the random value is acquired (read). Is completed.

  As shown in FIG. 4, the input latch register 16a and the output buffer 16b are provided separately for the I / O addresses “000Eh” and “000Fh” (the output buffer 16b is “ 000Eh ”only and not“ 000Fh ”). When a data write instruction is executed from the MPU 11 to the I / O addresses “000Eh” and “000Fh”, the data is latched into the input latch register 16a, while the MPU 11 receives the I / O address “000Eh”. When the data read command is executed, the 8-bit data input to the output buffer 16b is read into the MPU 11.

  As shown in FIG. 2, the MPU 11, ROM 12, and RAM 13 are connected to each other via a bus line 15, and the bus line 15 is also connected to an input / output port 16. The input / output port 16 is connected to the display control board D and other input / output devices 19 as well as the comparison ROM 17. The main control board C transmits various commands to the display control board D and other input / output devices 19 via the input / output port 16 to control these devices. The main control board C and the display control board D are connected via two buffers (inverter gates) 18 and 28 with fixed inputs and outputs. Therefore, transmission / reception of commands between the main control board C and the display control board D is performed only in one direction from the main control board C to the display control board D, and from the display control board D to the main control board C. You cannot send commands to

  The display control board D includes an MPU 21, a program ROM 22, a work RAM 23, a video RAM 24, a character ROM 25, an image controller 26, an input port 29, and an output port 27. The output of the inverter gate 28 is connected to the input of the input port 29, and the output of the input port 29 is connected to a bus line connecting the MPU 21, the program ROM 22, and the work RAM 23. An image controller 26 is connected to the input of the output port 27, and the LCD display 3 is connected to the output of the output port 27.

  The MPU 21 of the display control board D is for controlling the (variation) display of the LCD display 3 based on the control command transmitted from the main control board C. The program ROM 22 is executed by the MPU 21. Various control programs to be executed are stored. The work RAM 23 is a memory in which work data used when the MPU 21 executes a program is stored.

  The video RAM 24 is a memory for storing data to be displayed on the LCD display 3, and the display content of the LCD display 3 is changed by rewriting the content of the video RAM 24. That is, the variable display of the symbols in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 adjusts the timing of each of the MPU 21, the video RAM 24, and the output port 27, intervenes in reading and writing data, and displays the display data stored in the video RAM 24 at a predetermined timing with reference to the character ROM 25. This is displayed on the display 3.

  Next, with reference to FIG. 5, the reset interrupt process performed on the main control board C will be described. FIG. 5 is a flowchart of a reset interrupt process executed every 2 ms on the main control board C. In this reset interrupt process, first, it is checked whether or not the process is the first process executed after power-on (S1). If it is the first process executed (S1: Yes), the RAM 13 Initialization processing such as setting the initial value after the content is once cleared to “0” is executed (S2). After execution of the process of S2, the execution of the process waits until the next reset interrupt process occurs.

  If it is determined in the process of S1 that the reset interrupt process is executed for the second time and after the power is turned on (S1: No), the game of the pachinko gaming machine P is controlled by each process of S3 to S11. Is called. In the control of the game, first, it is checked whether or not the ball has passed the first type starting port (symbol operating port) 4 (S3), and the ball has passed the first type starting port (symbol operating port) 4. If it is (S3: Yes), each process of S4-S10 is performed in order to determine whether it is a big hit.

  First, the value (random number value) of the random number counter 14 is read by the MPU 11 (41 in FIG. 4), and the read value is written to the BC register which is an internal register of the MPU 11 (S4). Next, the value of the BC register is output to “000Eh” and “000Fh” which are I / O addresses of the comparison ROM 17 (S5, 42 in FIG. 4). As described with reference to FIG. 4, the value of the BC register (random number value) is once latched in the input latch register 16 a of the input / output port 16 by the processing of S <b> 5 and then from the input / output port 16. It is output as an address to the comparison ROM 17 (43 in FIG. 4). Since the read signal of the comparison ROM 17 is always active (44 in FIG. 4), when the address output from the input / output port 16 is stabilized, the data of the comparison ROM 17 stored at the address indicated by the random value, that is, the random value Is read from the comparison ROM 17 and output to the input / output port 16 (45 in FIG. 4). The data output from the comparison ROM 17 to the input / output port 16 is input to the output buffer 16 b of the input / output port 16.

  Next, by the process of S6, the value of “000Eh” that is the address of the comparison ROM 17 of the I / O address is read (46 in FIG. 4), and the read value is written to the D register that is an internal register of the MPU 11 ( S6). Since the data for the random number value has already been input to the output buffer 16b of the input / output port 16 referred to when the MPU 11 is read, the data for the random number value is read into the D register by the processing of S6. Can do.

  After the data for the random value is read into the D register, the state of the jackpot bit x (17a) of the D register is checked (S7). If the jackpot bit x (17a) is "1" (S7: Yes), it is a jackpot occurrence. In such a case, the state of the high probability jackpot bit y (17b) is further examined (S8), It is determined whether or not the jackpot is a high probability jackpot. That is, if the high-probability jackpot bit y (17b) is “1” (S8: Yes), the high-probability jackpot processing is executed because the high-probability jackpot is generated (S9). If (17b) is “0” (S8: No), the jackpot processing is executed (S10) because it is a normal jackpot occurrence. In the process of S7, if the jackpot bit x (17a) is “0” (S7: No), it is not a jackpot, so the processes of S8 to S10 are skipped and the process proceeds to S11. .

  In the process of S11, each process (S11) for controlling the progress of the game is executed on the main control board C, and after the execution of each process (S11), until the next reset interrupt process occurs. Wait for processing to execute.

  As described above, according to the pachinko gaming machine P of the first embodiment, data such as a jackpot for a random value is stored in advance at the address indicated by the random value of the comparison ROM 17, and when a jackpot determination trigger comes. The random number value read from the random number counter 14 is output to the comparison ROM 17 as an address, and the data for the random number value is read from the comparison ROM 17 to determine the jackpot or the like. Therefore, the jackpot etc. can be determined in a short time regardless of the size of the update range of the random number value, so the “hanging board” or the like can be used without causing any trouble in controlling the game of the pachinko gaming machine P. In order to prevent illegal acts, the update range of random values can be expanded.

  Next, a second embodiment will be described with reference to FIGS. In the first embodiment, as shown in FIG. 3, the jackpot bit x (17a) is the 0th bit, the high probability jackpot bit y (17b) is the first bit, and the prime bit z (17c) is 2 bits. In the second embodiment, the storage position of each bit is changed according to the random number value. Hereinafter, the same reference numerals are given to the same parts as those of the first embodiment described above, and the description thereof is omitted, and only the parts different from the first embodiment will be described.

  FIG. 6 is a diagram showing a 1-byte data configuration of the comparison ROM 17 in the second embodiment for each bit. As shown in FIG. 6, in the second embodiment, the jackpot bit x (17a) is arranged at the remaining bit position obtained by dividing the random number value by 8, and the high probability jackpot bit y (17b) is placed at the position of the +1 bit. And a prime bit z (17c) is arranged at the position of the +1 bit. When the value added to the bit position is +1 or more, the corresponding bit of the high probability big hit bit y (17b) or prime bit z (17c) is the bit of the difference between the value added by +1 and “8” Placed in position.

  For example, when the random value is “0”, the remainder of dividing the random value by 8 is “0”, so each bit is arranged as 60 in FIG. When the random value is “189”, the remainder of dividing the random value by 8 is “5”, so each bit is arranged as 65 in FIG. Furthermore, when the random value is “511”, the remainder of dividing the random value by 8 is “7”, so each bit is arranged as 67 in FIG. In the second embodiment as well, the prime bit z (17c) is not used for the jackpot determination as in the case of the first embodiment.

  With reference to FIG. 7, the reset interruption process of 2nd Example performed by the main control board C is demonstrated. In the reset interrupt process of the second embodiment, after writing data for the random number value into the D register by each of the processes of S4 to S6, the value of the BC register for storing the random number value is divided by “8”, and the remainder is MPU11. Is written into the E register, which is an internal register (S21).

  After the data for the random number value is written to the D register and the remainder obtained by dividing the random number value by “8” is written to the E register, the bit of the D register located at the value of the E register, that is, the jackpot bit x (17a) The state is examined (S22). If the jackpot bit x (17a) is “1” (S22: Yes), the jackpot is generated. Therefore, in such a case, the state of the bit of the D register located at the value of the E register + 1, that is, the high probability big hit bit y (17b) is further examined (S23), and the big hit is the high probability big hit. It is determined whether or not. If the high-probability jackpot bit y (17b) is “1” (S23: Yes), the high-probability jackpot processing is executed because the occurrence of a high-probability jackpot (S9). Conversely, the high-probability jackpot bit y (17b) ) Is “0” (S23: No), it is a normal jackpot occurrence, so jackpot processing is executed (S10).

  When the remainder of dividing the random number value by “8” is “7” (when the value of the E register is “7”), the value obtained by adding “+1” to the remainder becomes “8”. As described with reference to FIG. 6, the high-probability jackpot bit y (17b) is arranged at the bit position of the difference between the value obtained by adding +1 and “8”, that is, the 0th bit (67 in FIG. 6).

  In the processing of S22, if the bit of the D register located at the value of the E register, that is, the jackpot bit x (17a) is “0” (S22: No), the jackpot is not generated, so the following S23, Each process of S9 and S10 is skipped, and the process proceeds to S11.

  As described above, according to the pachinko gaming machine P of the second embodiment, the bit position of the big hit bit x is changed according to the random value, so that the data line between the comparison ROM 17 and the input / output port 16 is disconnected, etc. Thus, it is possible to prevent an illegal act of generating a jackpot.

  When the bit position of the jackpot bit x is fixed, the signal line at that bit position is cut and pulled up, so that the output of the signal line can be fixed to “1” and an unreasonable jackpot can be generated. . However, such fraud can be prevented by changing the bit position of the jackpot bit x according to the random value as in the second embodiment. For example, only when the value one bit before the jackpot bit x (the seventh bit when the jackpot bit x is the 0th bit) is “0” and the jackpot bit x is “1”, A big hit is generated. According to this method, when all signal lines are cut and pulled up, the bit immediately before the jackpot bit x is always “1”, so that no jackpot is generated. Therefore, it is possible to prevent an illegal act of generating a jackpot by cutting the data line between the comparison ROM 17 and the input / output port 16 or the like.

  Next, a third embodiment will be described with reference to FIG. In the first and second embodiments described above, the prime bit z (17c) is not used for the jackpot determination. In the third embodiment, the jackpot determination is performed using the prime bit z (17c). Yes.

Specifically, the jackpot is generated only when the random value is a prime number, and the jackpot determination table (not shown) in the ROM 12 is the same as the comparison ROM 17 having a size corresponding to the update range of the random value. Is provided. The jackpot determination is made only by referring to the jackpot determination table in the ROM 12 only when the prime bit z (17c) of the data corresponding to the random number value read from the comparison ROM 17 is “1”. This is done according to the status of data jackpot bit x (17a) and high probability jackpot bit y (17b) for the numerical value. As described above, the prime bit z (17c) is “1” only when the target random number value is a prime number. Hereinafter, the same reference numerals are given to the same parts as those of the first embodiment described above, and the description thereof is omitted, and only the parts different from the first embodiment will be described.

  As shown in FIG. 8, in the reset interrupt process of the third embodiment, after data for a random number value is written to the D register by each process of S4 to S6, the state of the prime bit z (17c) of the D register is changed. Check (S31). If the prime bit z (17c) of the D register is “1” (S31: Yes), the target random number value is a prime number, so there is a possibility of a big hit. Therefore, in such a case, the value-th data in the BC register, which is a random value, is read from the jackpot determination table in the ROM 12, and the read data is written to the D register (S32). As a result, data such as a jackpot for the random number value is stored in the D register. Thereafter, the processing of S7 and S8 causes the jackpot bit x (17a) and the high probability jackpot bit y (17b) of the D register. The occurrence of a big hit or the like is determined according to the state.

  In the processing of S31, if the prime bit z (17c) is “0” (S31: No), the target random number value is not a prime number, so there is no possibility of a big hit. Therefore, in such a case, each process of S32 and S7 to S10 is skipped, and the process proceeds to S11.

  As described above, according to the pachinko gaming machine P of the third embodiment, since the big hit is generated only when the random value is a prime number, the big hit is determined only when the prime bit z is “1”. Just do it. Therefore, it is possible to efficiently execute the control by reducing the number of jackpot determinations. Further, by determining the jackpot in two stages, that is, using the data in the comparison ROM 17 and the data in the jackpot determination table in the ROM 12, even if the comparison ROM 17 is replaced with an illegal ROM, the jackpot is unfairly performed. It cannot be generated. Therefore, the effect of preventing fraud can be further improved.

  The third embodiment may be modified as follows. That is, instead of the jackpot determination table of the third embodiment, a jackpot table that stores a random number that is a jackpot and a high probability jackpot table that stores a random number that is a high probability jackpot are provided in the ROM 12, respectively. When the prime bit z of the data read from the comparison ROM 17 is “1”, it is determined whether or not the target random number value is stored in the jackpot table and the high probability jackpot table in the ROM 12. It is configured to determine the occurrence of jackpots and high probability jackpots. Also in this modified example, since the jackpot determination is performed only when the random number is a prime number, the number of jackpot determinations can be reduced, and the game control is not hindered.

  Further, in the third embodiment, random numbers for generating jackpots are determined in a continuous range, for example, “7 to 1035”, and random numbers for generating high probability jackpots are, for example, “7 to 273”. Only when the prime bit z is “1”, it may be determined whether or not the random value is a value within the range to determine the jackpot. In this case, the jackpot determination is made in the range, but since the prime number does not exist continuously, the entire range does not function as one random number value, and the meaning of expanding the update range of the random number value is lost. There is nothing. In this modification, the jackpot determination table is not used and is deleted.

  In the first embodiment, the reading means according to claim 1 corresponds to the processes of S5 and S6, and the determination means corresponds to the processes of S7 to S10. In the second embodiment, the reading means according to claim 1 corresponds to the processes of S5 and S6, and the determining means corresponds to the processes of S21 to S23, S9, and S10. Further, in the third embodiment, the reading means according to claim 1 corresponds to the processes of S5 and S6, and the determination means corresponds to the processes of S31, S32, S7 to S10.

  The present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be easily made without departing from the spirit of the present invention. It can be guessed.

  For example, in the present embodiment, the comparison ROM that stores data such as jackpots for random numbers is configured separately from the MPU 11, but the comparison ROM 17 may be integrated with the MPU 11, that is, incorporated in the MPU 11. If the comparison ROM 17 is built in the MPU 11, the comparison ROM 17 cannot be exchanged illegally, so that the effect of preventing illegal acts can be further improved.

  The modification of this invention is shown below. 2. The gaming machine control device according to claim 1, wherein the storage means is arranged on an I / O address. It is possible to effectively use the memory address by arranging the storage means for storing predetermined data (for example, data such as jackpot) corresponding to the random number value not on the memory address but on the I / O address. it can. For example, if the random number counter is composed of a 16-bit counter and the storage means is arranged on the memory address, the memory space of 0000 to 0FFFFh is entirely occupied by the storage means. However, by arranging the storage means on the I / O address, the memory space of 0000 to 0FFFFh can be effectively used as an address other than the storage means.

  A gaming machine control device according to claim 1 or a gaming machine control device 1 comprising an MPU for controlling a game, wherein the storage means is built in the MPU. Control device 2. By incorporating the storage means in the MPU, it is possible to prevent the act of exchanging the storage means with an unauthorized one in order to unjustly generate a predetermined game value (for example, jackpot).

  2. The gaming machine control device according to claim 1, or the gaming machine control device 1 or 2, wherein the data of the storage means read by the reading means is provided with a jackpot bit indicating whether or not a jackpot has occurred. A control device 3 for a gaming machine, characterized in that: The presence or absence of a jackpot is determined based on the status of the jackpot bit.

  In the gaming machine control device 3, the bit position of the jackpot bit changes according to a random value output as an address to the storage means. If the bit position of the jackpot bit is fixed, the signal line at that bit position is disconnected and pulled up (or pulled down) to fix the output of the signal line to “1 (or 0)” and illegally A jackpot can be generated. However, this fraud can be prevented by changing the bit position of the jackpot bit according to the random value. For example, if the value one bit before the jackpot bit (the seventh bit when the jackpot bit is the 0th bit) is “0” and the jackpot bit is “1”, the jackpot is generated. is there. According to this method, when all the signal lines are cut and pulled up, no jackpot is generated.

  2. The gaming machine control device according to claim 1, or the gaming machine control device 1 or 2, wherein the random number value output as an address to the storage means is a prime number in the data of the storage means read by the reading means. A control device 5 for a gaming machine, which is provided with a prime bit indicating that If the jackpot is generated only when the random number value is a prime number, the jackpot determination need only be performed when the prime bit is “1 (or 0)”. Can be executed efficiently. In addition, by performing the jackpot determination in two stages as described above, even if the storage means is illegally exchanged, the jackpot cannot be illegally generated, so that the effect of preventing illegal acts can be further improved.

  2. The game machine control device according to claim 1, or the game machine control devices 1 to 5, wherein the random number counter is updated by a high-speed pulse that cannot be updated by a software control. A game machine control device 6 characterized. Therefore, in the software control using the “hanging board” or the like, the count value cannot be updated by following the random number counter, so that it is impossible to grasp the random value using the “hanging board” or the like.

  2. The gaming machine control device according to claim 1, or the gaming machine control device 1 to 6, further comprising an MPU for controlling a game, and updating the count value by the random number counter is an operation clock of the MPU. A game machine control device 7, which is performed by an asynchronous clock. Therefore, in the software control using the “hanging board” or the like, the count value cannot be updated in synchronization with the update of the random number counter, so that it is impossible to grasp the random number value using the “hanging board” or the like. In addition, if the clock for updating the count value of the random number counter is a clock that is too fast to follow the update of the count value by software control, it will be possible to further grasp the random number value by software control such as “hanging board”. Can be difficult.

  2. The gaming machine control device according to claim 1, or the gaming machine control devices 1 to 7, wherein the random number counter is counted by a signal that is continuously output at non-uniform intervals according to a game control state. The game machine control device 8 is characterized in that the update is performed. Therefore, since the random number counter is constantly updated at non-uniform intervals, it is possible to make it impossible to grasp the random number value by the “hanging board” or the like.

  2. The gaming machine control device according to claim 1 or the gaming machine control device 1 to 8, further comprising an MPU for controlling a game, wherein the random number counter is an M1 signal output from the MPU, a memory Request signal, IO request signal, read signal, write signal, refresh signal, wait signal, bus request signal, bus acknowledge signal, at least one address bus signal, or at least one data bus signal A gaming machine control device 9 that updates a count value based on any one of the signals. Since these signals are constantly output at non-uniform intervals according to the control state of the game, it is not necessary to provide a separate circuit for generating the signals, and the circuit cost can be reduced. In addition, you may use combining several signals among the above-mentioned signals.

  2. The gaming machine control device according to claim 1, wherein the random number value is updated by the random number counter starting from an indefinite value. . For example, when the power is turned on, the random number that is the count value of the random number counter is not initialized, and the random number is updated from the indeterminate value at the time of turning on the power. Can be difficult.

3 Liquid crystal display 11 Main control board MPU
11a
MPU operation clock 14 Random number counter 14a Random number counter operation clock 16 Input / output port 17 Comparison ROM (storage means)
17a jackpot bit 17b high probability jackpot bit 17c prime bit C main control board (control device for gaming machine)
D Display control board P Pachinko machine (game machine)

Claims (1)

A random number counter that repeatedly updates a random value within a predetermined range;
And against the random number value is updated with the random number counter comprises a predetermined bit which indicates whether to assign a predetermined game value to the player, the change bit position of the predetermined bit in response to the random number value Storage means for storing the 1-byte data being stored at an address related to the random number value;
When it is time to determine whether or not to give a predetermined game value to a player, an address related to the random value indicated by the random number counter at that time is output to the storage means and stored in the output address. reading means for reading the 1-byte of data from said storage means,
Specifying means for specifying the bit position of the predetermined bit from the data read by the reading means;
And determining means for determining whether or not to give a predetermined game value to the player by examining the state of the predetermined bit for the bit position specified by the specifying means. Gaming machine.

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