JP2000167212A - Pachinko game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent illegal actions using a 'hanging substrate' or the like. SOLUTION: The value of an initial value counter is repeatedly updated during residual time in a reset interruption processing by an initial value counter updating processing (S22). The reset interruption processing is executed at every 2ms, and since the processing time of respective processings S1-S20 executed in the reset interruption processing of one time is changed corresponding to the condition of a game, the residual time of the reset interruption processing is not fixed time and is unfixed time changed corresponding to the condition of the game. Since the unfixed time can not be recognized by the 'hanging substrate' and the value of the initial value counter repeatedly updated within the unfixed time is used as the initial value of the updating of a random number counter, the recognition of the timing of large winning generation by the 'hanging substrate' is made impossible and the illegal action by the 'hanging substrate' is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ball game machine typified by a pachinko game machine and the like, and more particularly to a ball game machine capable of preventing fraudulent acts such as a "hanging board".

[0002]

2. Description of the Related Art A pachinko gaming machine of this type is provided with a display device capable of variably displaying a plurality of types of symbols, and when a ball hit into a game area passes through a symbol operation gate,
It is configured to start variable display. When the variable display is stopped in accordance with a predetermined combination of symbols, a big hit occurs, a predetermined game value is given to the player, and a large number of game balls can be paid out.

[0003] The occurrence of such a big hit is determined at the timing when the hit ball passes through the symbol operation gate. That is, in a certain range periodically (eg, 1
A counter that is updated (in the range of 0 to 630 every 2 ms for each count) is provided, and when the hit ball passes through the symbol operation gate, the value of the counter is read, and the read value of the counter is, for example, When a predetermined value such as "7" matches, a big hit is generated. When a big hit occurs, a big hit command is transmitted to the display board of the display device via the cable connected to the connector of the control board. The display device controls the variable display based on the received jackpot command, and causes the jackpot display to stop at a predetermined combination of symbols to appear.

[0004]

[Problems to be solved by the invention] However, recently,
There have been reports of fraudulent activities using fraudulent substrates called "hanging substrates". This fraudulent act involves hanging an improper board (attaching an improper "hanging board") between the control board and the display board of the display device, thereby causing an unreasonable jackpot. Specifically, a counter (a counter that is periodically updated in a fixed range by one count) that functions similarly to the counter for determining the jackpot provided in the pachinko gaming machine is placed in the “hanging board”. By setting the value of the counter and resetting (clearing it to 0) when the power of the pachinko gaming machine is turned on, it is possible to grasp the timing of occurrence of a jackpot in the “hanging board”. Then, in accordance with the timing of the occurrence of the jackpot that has been grasped, an illegally generated symbol passing gate operation signal for the hit ball is generated in the "hanging board" and outputted to the control board of the pachinko machine to generate an unreasonable jackpot. It is to let. At amusement arcades and the like, there has been a problem that a great deal of damage has been caused by an illegal act using the “hanging board”.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is impossible to grasp the timing of jackpot occurrence, thereby preventing an illegal act using a "hanging board" or the like. It aims to provide ball game machines.

[0006]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a ball game machine, wherein an interrupt process which is periodically executed, a random number counter, and a value of the random number counter are assigned to the interrupt processing. First updating means for updating by a reading process, and reading means for reading a value of the random number counter at a predetermined timing, wherein the value of the random number counter read by the reading means is one of a predetermined value. If they match,
A predetermined game value is given to a player under predetermined conditions, and an initial value memory for storing an initial value of the random number counter being updated, and a value written to the initial value memory and the random number counter, An initial value counter composed of at least 2 bytes for counting the initial value of the next update of the random number counter, reading the value of the initial value counter, and updating the value in the addition direction within the range of the update of the random number counter The updated value is written to the initial value counter in the order of the upper byte and the lower byte, and the second updating means is repeatedly executed during the remaining time until the next interrupt processing by the interrupt processing. Returning means for returning the value of the initial value counter to a value within a range of updating of the random number counter before writing the value of the initial value counter to the random number counter and the initial value memory; It is provided.

In addition, the ball game machine according to a second aspect of the present invention provides an interrupt processing that is periodically executed, a random number counter, and first updating means for updating the value of the random number counter by the interrupt processing. Reading means for reading the value of the random number counter at a predetermined timing, and when the value of the random number counter read by the reading means matches one of predetermined values, the player is provided with a predetermined condition. In the initial value memory for storing the initial value of the random number counter being updated, and a value written to the initial value memory and the random number counter, the next update of the random number counter is performed. An initial value counter composed of at least two bytes for counting the initial value of the random number counter, and reading out the value of the initial value counter, and subtracting the value within the range of updating the random number counter. Updated, it writes the updated value in the order of low-order byte high-order byte to its initial value counter,
A second updating unit that is repeatedly executed during the remaining time until the next interrupt processing is generated by the interrupt processing, and that the value of the initial value counter is written to the random number counter and the initial value memory before writing to the random number counter and the initial value memory. Return means for returning the random number counter to a value within the range of update.

According to the ball game machine of the present invention, in the interrupt processing periodically executed, the value of the random number counter is set to the first value.
The information is updated by the updating means and is read by the reading means at a predetermined timing. When the read value of the random number counter matches one of the predetermined values, a jackpot is won, and a predetermined game value is given to the player under predetermined conditions.

The value of the initial value counter for counting the initial value of the next update of the random number counter is written to the random number counter and the initial value memory, and the initial value of the update of the random number counter is changed. As described above, the initial value of the update of the random number counter is not a fixed value but a value that is periodically changed. Even if the counter is reset, the value of the incorrect counter cannot be made to match the value of the random number counter. Therefore, it is possible to prevent the “hanging substrate” or the like from knowing the timing of the occurrence of the big hit.

Further, the value of the initial value counter for counting the initial value of the update of the random number counter is repeatedly updated by the second updating means during the remaining time of the interrupt processing that is periodically executed. Since the length of the remaining time of the interrupt process changes according to the state of the game, it cannot be grasped by a “hanging board” or the like. Therefore, since the value of the initial value counter is updated by repeatedly executing the second updating means during the remaining time, it is possible to prevent the value of the random number counter from being grasped by a "hanging board" or the like in this regard. it can.

According to the first aspect of the present invention, the value of the initial value counter is composed of at least two bytes, and the value of the initial value counter is read by the second updating means and is within the range of updating the random number counter. After updating in the addition direction, the updated value is written to the initial value counter in the order of upper byte and lower byte. After writing the updated value to the upper byte of the initial value counter and before writing to the lower byte, if the remaining interrupt processing time runs out and the next interrupt occurs, the value of the initial value counter becomes a random number. The value may be out of the range for updating the counter.

For example, if the value of the random number counter is "0-276
h ”, the case where the value of the initial value counter is“ 1FFh ”will be described. In this case, the value of the initial value counter must also be updated within the range of "0 to 276h". The value of the initial value counter of “1FFh” is read by the second updating means,
It is assumed that the value is updated in the addition direction, for example, “+1”, and the updated value becomes “200h”. The updated value is written to the initial value counter by the second updating means in the order of the upper byte and the lower byte. Therefore, the value of the initial value counter changes from “1FFh” to “2FFh” after the writing of the upper byte, and further to the lower byte. Is updated to “200h”. However, if an interrupt occurs after writing to the upper byte and before writing to the lower byte, the updating of the initial value counter ends without writing to the lower byte. Becomes a value of “2FFh”, which is a value outside the range of updating the random number counter.

When the value of the initial value counter becomes a value outside the range of updating the random number counter, the value of the random number counter becomes a value outside the range that should be updated. For example, the probability of occurrence of a jackpot differs from the expected probability, or the initial value of the update of the random number counter is not changed thereafter. However, since the value of the initial value counter is returned (returned) to a value within the range of the update of the random number counter before writing to the random number counter and the initial value memory by the return means, these problems are avoided. You can do it.

According to the second aspect of the present invention, the value of the initial value counter is composed of at least two bytes, and the value of the initial value counter is read by the second updating means and is within the range of updating the random number counter. , The updated value is written to the initial value counter in the order of the lower byte and the upper byte. Therefore, after the updated value is written to the lower byte of the initial value counter and before writing to the upper byte, the remaining time of the interrupt processing is exhausted and the next interrupt occurs. May be outside the range of updating the random number counter. If the value of the initial value counter becomes a value outside the range of updating the random number counter, as described above, the value of the random number counter becomes a value outside the range that should be updated, causing a predetermined problem. However, the value of the initial value counter is returned (returned) to a value within the range of the update of the random number counter by the return means before writing to the random number counter and the initial value memory. Can be.

[0015]

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In this embodiment, a description will be given using a pachinko gaming machine as an example of a ball and ball gaming machine, particularly, a first-type pachinko gaming machine. Note that it is naturally possible to use the present invention for a third-type pachinko gaming machine and other ball-and-ball gaming machines.

FIG. 1 is a front view of a game board of a pachinko gaming machine P in the first embodiment. Around the game board 1, there are provided a plurality of winning ports 2 from which 5 to 15 game balls are paid out when a hit ball wins. In the center of the game board 1, a liquid crystal (LCD) display 3 for displaying a plurality of kinds of symbols as identification information is provided. The display screen of the LCD display 3 is divided into three in the horizontal direction, and in each of the three divided display areas,
Each symbol is displayed in a variable manner.

A symbol operation gate (first type starting port) 4 is provided below the LCD display 3, and when the hit ball passes through the symbol operation gate 4, the above-mentioned LCD is activated.
The variable display on the display 3 is started. Below the symbol operation gate 4, a specific winning opening (large winning opening) 5 is provided. When the display result after the change of the LCD display 3 matches one of the predetermined symbol combinations, the specific winning opening 5 becomes a big hit and a predetermined time (for example, 30) so that the hit ball can easily win. The winning opening is opened until the second elapses or until 10 hit balls are won. The specific winning opening 5 includes a V zone 5a
When the specific winning opening 5 is opened, the hit ball
When the player passes through the zone 5a, the continuation right is established, and after the specific winning opening 5 is closed, the specific winning opening 5 is again set for a predetermined time (or until a predetermined number of hit balls wins in the specific winning opening 5).
Be released. The opening and closing operation of this specific winning opening 5 is 1 at the maximum.
The state in which the opening / closing operation can be performed six times (16 rounds) and can be performed is a state in which a predetermined game value is given (special game state).

FIG. 2 is a block diagram showing an electric configuration of the pachinko gaming machine P. The control unit C of the pachinko gaming machine P includes a CPU 11 which is an arithmetic device and its CPU 1
1 includes a ROM 12 that stores various control programs executed by the control unit 1 and fixed value data, and a RAM 13 that is a memory for temporarily storing various data. 3 to 5 are stored in the ROM 12 as a part of the control program.

The CPU 11 includes an ALU for performing calculations,
An accumulator (hereinafter referred to as "Acc") 11a, a plurality of internal registers 11b, and a flag register 11c are provided. The value of a counter or the like provided in the RAM 13 is
Once loaded (written) into the internal register 11b of the CPU 11 and updated in the internal register 11b, it is saved (written) into the original counter of the RAM 13 and updated.

In the 68-system 8-bit CPU 11,
The value of the paired 2-byte (16-bit) internal register 11b can be saved (written) to a 2-byte memory (in the RAM 13) of a continuous address with one instruction. In this case, since the data bus of the bus line 14 is composed of 8 bits, the upper byte,
It is performed in the order of the lower byte. Also, 80-system 8-bit C
In the PU, contrary to the CPU 11 of the 68 series, the value of the paired internal register of 2 bytes (16 bits) is saved to the 2-byte memory of the continuous address by one instruction in the order of the lower byte and the upper byte. can do.

The RAM 13 includes a random number counter 13a, an initial value counter 13b, and an initial value memory 13c. The random number counter 13a is a counter for determining the occurrence of a jackpot, and the random number updating process (S7) in FIG.
In the range of “0-630 (0-276h)”,
It is updated by one count every 2 ms. For this reason, the random number counter 13a is composed of 2 bytes. Random number counter 1 obtained when the hit ball passes the symbol operation gate 4
If the value of 3a is, for example, "7", a big hit occurs. When a big hit occurs, a big hit command is sent from the control unit C to a display device D described later. The display device D is
Based on the jackpot command, the variable display of the LCD display 3 is controlled to a jackpot state.

The initial value counter 13b is a random number counter 1
This is a counter for counting the initial value of the update of 3a, and is composed of 2 bytes like the random number counter 13a. The value of the initial value counter 13b is set to “0 to 630 (276) which is the same as the update range of the random number counter 13a by the initial value counter updating process (S6, S22) in FIG.
h)), is updated by one count.

The initial value counter updating process shown in FIG. 5 is performed during the remaining time in the reset interrupt process shown in FIG. 3, that is, from the end of the sound effect process (S20) until the next reset interrupt process occurs. Is repeatedly executed (S22). The reset interrupt processing is executed every 2 ms. However, since the processing time of each processing from S1 to S20 executed in one reset interrupt processing changes according to the game situation, the remaining time of the reset interrupt processing is not changed. The time is not a fixed time, but an indefinite time that changes according to the game situation. Since the "hanging board" cannot grasp this indefinite time, by using the value of the initial value counter 13b repeatedly updated within the indefinite time as the initial value of the update of the random number counter 13a, the "hanging board" It is impossible to grasp the timing of the occurrence of the jackpot due to the "substrate".

As will be described later with reference to FIG. 5, the value of the initial value counter 13b is stored in the internal register 1 of the CPU 11.
1b. Writing from the internal register 11b to the initial value counter 13b is performed by the 68
The instruction is performed in the order of an upper byte and a lower byte. Therefore, for example, when the value of the initial value counter 13b before the update is “1FFh”, “20” is stored in the internal register 11b.
After being updated to "0h", the updated value is written to the initial value counter 13b in the order of the upper byte and the lower byte (S45). That is, the value of the initial value counter 13b is “1”.
The upper byte of the internal register 11b is temporarily written to "2FFh" from the state of "FFh", and then the lower byte of the internal register 11b is written and updated to "200h".

However, since the initial value counter updating process of FIG. 5 is repeatedly executed during the remaining time of the reset interrupt process, the upper byte of the updated internal register 11b is written to the initial value counter 13b. Before writing the lower byte of the internal register 11b (during the process of S45), the next reset interrupt process may occur. The reset interrupt is a non-maskable interrupt for which the occurrence of an interrupt cannot be prohibited, has the highest priority, and is forcibly started even during the execution of an instruction of the CPU 11. It is. Therefore, at this timing (after writing the upper byte of the updated internal register 11b to the initial value counter 13b and before writing the lower byte of the internal register 11b), when a reset interrupt occurs, the initial value counter 13b May be “767 (2FFh)” which exceeds the range of the original update range “0-630 (0-276h)”.

The update range of the value of the random number counter 13a is also "0".
630 (0 to 276h) ”, the value (767 (2FFh)) of the initial value counter 13b is
When the initial value of the random number counter 13a is used, the update cycle of the random number counter 13a fluctuates to make the probability of occurrence of a jackpot different from the set value, or the initial value of the update of the random number counter 13a cannot be changed thereafter. There is a problem that it is lost. In the random number update process (S7) of FIG. 4, the value of the random number counter 13a cannot be equal to or more than "631 (277h)" (S33: Yes, S34). "631 (27
7h) ”is written into the initial value memory 13c as an initial value for updating the random number counter 13a (S3).
6, S37), and thereafter, in the processing of S35, the branch of Yes cannot occur.

Here, the value of the initial value counter 13b is written as an initial value to the random number counter 13a in a random number updating process (S36 to S38 in S7). On the other hand, the value of the initial value counter 13b that has become a value outside the original update range is:
By re-executing the initial value counter update processing in FIG. 5, the value is returned to the value within the original update range. "631 (27
7h) "or more is cleared to" 0 "(S43: Yes, S44, S4).
5). Therefore, in the present embodiment, in order to avoid the occurrence of the above-described inconvenience, not only the initial value counter update processing of FIG. 5 is repeatedly executed during the remaining time of the reset interrupt processing (S22), but also the random number update processing is performed. It is executed at least once before the execution of (S7) (S6).

The initial value memory 13c stores the random number counter 13
This is a memory for storing the initial value of the update of a, and is composed of 2 bytes like the random number counter 13a. In this embodiment, the initial value of the update of the random number counter 13a is changed every time the random number counter is updated. Therefore, the updated value of the random number counter 13a is stored in the initial value memory 13c.
When the values 13a and 13c match, the value of the initial value counter 13b is changed to the value of the random number counter 13a and the initial value memory. 13c, the initial value of the update of the random number counter 13a is changed. Therefore, even if the initial value of the update of the random number counter 13a is changed, there is uniformity of the random numbers (the same value is not obtained when continuously obtained, and all values can be extracted with the same probability). You can get a random value.

These CPU 11, ROM 12, RAM
13 are connected to each other via a bus line 14, and the bus line 14 is also connected to an input / output port 15. The input / output port 15 is connected to the display device D and another input / output device 16. The control unit C is connected to the display device D or another input / output device 1 via the input / output port 15.
6 to send an operation command to control these devices. L
The variable display of the CD display 3 and the opening / closing operation of the special winning opening 5 are also controlled based on the operation command.

The display device D includes a CPU 21, a program ROM 22, a work RAM 23, and a video RAM 24.
, Character ROM 25, image controller 26
, An input / output port 27 and the LCD display 3. The CPU 21 of the display device D responds to the operation command output from the control unit C to the LCD display 3.
The program ROM 22 stores a program executed by the CPU 21. The work RAM 23 is a CPU
21 is a memory that stores work data used when the program is executed by the program 21.

The video RAM 24 is a memory in which data to be displayed on the LCD display 3 is stored.
The display content of the D display 3 is changed. That is, the change display of the symbol in each display area is performed by rewriting the contents of the video RAM 24. The character ROM 25 is a memory for storing character data such as symbols displayed on the LCD display 3. The image controller 26 includes a CPU 21, a video RAM 24,
By adjusting the timing of each input / output port 27,
In addition to reading and writing data, the video RAM 2
The display data stored in the LCD 4 is displayed on the LCD display 3 at a predetermined timing with reference to the character ROM 25.

Next, each processing executed in the pachinko gaming machine P configured as described above will be described with reference to flowcharts of FIGS. FIG. 3 shows the pachinko machine P
12 is a flowchart of a reset interrupt process executed every 2 ms in the control unit C of FIG. Main control of the pachinko gaming machine P is executed by this reset interrupt processing.

In the reset interrupt processing, first, a stack pointer is set (S1), and a pattern written in a predetermined area of the RAM 13 is checked (S2). As a result of the check, if the predetermined pattern is written in the predetermined area, there is no abnormality in the RAM 13 and it is normal (S2: normal), and the process shifts to S3. On the other hand, as a result of the check in S2, if the predetermined pattern is not written in the predetermined area, it is the reset interrupt processing executed first after the power is turned on, or the RAM 13 is abnormal (S2: abnormal). In this case, the process proceeds to S23, where the content of the RAM 13 is once cleared,
Then, an initial value is written into the memory 13 (S23), and the process waits for the next reset interrupt processing.

In the process of S3, a timer interrupt is set (S3). The timer interrupt set here is LC
For example, there is a timer interrupt for generating a strobe signal for transmitting a command for controlling the display of the D display 3 to the display device D. After the setting of the timer interrupt, each interrupt is set to a permission state (S4). After the interruption is permitted, the output data updated in the previous reset interruption processing by the special symbol change processing (S16), the display data creation processing (S18), the ramp / information processing (S19), and the like are simultaneously processed. A port output process for outputting to a port is executed (S5). Thereafter, an initial value counter updating process (S6) described later is executed to update the initial value counter 13b by "+1" in the adding direction, and a random number updating process (S7) is executed to change the value of the random number counter 13a to "1". +1 "is updated, and a storage timer subtraction process is executed (S8). The storage timer subtraction process is performed when the number of reserved balls for the jackpot determination is equal to or more than a predetermined number and the symbol display is being changed and displayed on the LCD display 3.
This is to reduce the fluctuation display time of the symbol.

In the switch reading process (S9), the value of each switch is read so that the hit ball hit into the game area 1 wins the winning opening 2 or the large winning opening 5 (including the V zone 5a) and the symbol operation. This is a process for detecting passing of the gate 4 and further award balls and lending balls. Count abnormality monitoring processing (S
10) is a process for monitoring whether there is any abnormality in the switch data read by the switch reading process in S9. For example, the special winning opening 5 is opened and the V
When a hit ball is detected by the V count switch that detects the passing of the zone 5a, but a hit ball of one ball cannot be detected by the 10 count switch that detects a winning in the special winning opening 5 other than the V zone 5a. Some abnormality has occurred in the 10 count switch, for example, when the 10 count switch is removed. In addition, if one prize ball is not paid out even though the motor that pays out the prize ball is driven, some abnormality has occurred in the prize ball payout device. As described above, in the count abnormality monitoring process (S10),
Based on the switch data read by the switch reading process (S9), the presence or absence of the above-described abnormality is monitored.

In the symbol counter updating process (S11), L
As a result of the variable display performed on the CD display 3, a counter updating process for determining a symbol to be stopped and displayed is performed. Further, in the symbol check process (S12), based on the value of the counter updated in the symbol counter update process (S11), a big hit symbol used in the special symbol variation process (S16), a lost symbol, and a reach symbol. Are determined.

In the processing from S3 to S12, if no error has occurred (S13: normal), the fluctuation of the 7-segment LED is displayed by the normal symbol fluctuation processing (S14), and the fluctuation display results in Occurs, an ordinary electric accessory (not shown) is opened for a predetermined time to execute a hitting process. Thereafter, the state flag is checked (S15), and if the symbol is being displayed on the LCD display 3 while the symbol is being changed (S15: symbol is being changed), the timing at which the hit ball passes through the symbol operation gate 4 by the special symbol changing process (S16). Is determined based on the value of the random number counter 13a read in step (1), and a process of changing the display symbol on the LCD display 3 is performed. On the other hand, as a result of checking the state flag, if a big hit is being made (S15: big hit), a big hit process (S17) such as opening the big winning port 5 is executed. Further, as a result of checking the state flag, it is found that the symbol is not fluctuating or a big hit (S15: other), S16 and S1
The process skips the process of No. 7 and shifts to the display data creation process of S18. In the process of S13, if an error is confirmed (S13: error), S14 to S17
Are skipped, and the process proceeds to the display data creation process in S18.

In the display data creation processing (S18), demonstration data to be displayed on the LCD display 3 and display data of the 7-segment LED are created in addition to the symbol change display. Various types of lamp data are created, including sphere lamp data. In the sound effect processing (S20), sound effect data according to the game situation is created. The display data and the sound effect data are sent to the port output processing (S5).
And output to each device by timer interrupt processing.

After the end of the sound effect processing (S20), S11 is executed for the remaining time until the next reset interrupt processing occurs.
Symbol counter update processing which is the same processing as (S21)
And the initial value counter updating process (S22), which is the same process as S6, is repeatedly executed. Since the execution time of each processing of S1 to S20 changes according to the state of the game, the remaining time until the next reset interrupt processing occurs is not a fixed time but changes according to the state of the game. Therefore,
The symbol counter is updated using the remaining time (S2).
By repeatedly performing 1), the stop symbol can be changed at random. Further, by repeatedly executing the initial value counter updating process (S22) using the remaining time, the value of the initial value counter 13b, which is the initial value of the update of the random number counter 13a, cannot be grasped by the "hanging board". can do.

FIG. 4 is a flowchart of the random number updating process. In the random number update process (S7), the value of the random number counter 13a is set to “0” via the internal register 11b of the CPU 11.
630 (0 to 276 h) ", and updates the other random numbers used by the control unit C in increments of" +1 ".

First, the value of the 2-byte random number counter 13a is written into the 2-byte internal register 11b (S31). One is added to the value of the internal register 11b (S3
2) It is checked whether or not the value of the internal register 11b after the addition is equal to or more than "631", that is, whether or not the value exceeds the update range of the random number counter 13a (S33). If the value of the internal register 11b after the addition is “631” or more (S3
3: Yes), since the value exceeds the update range, the value of the internal register 11b is cleared to "0" (S34). On the other hand, if the value of the internal register 11b after the addition is equal to or less than “630” (S33: No), since the value is within the update range, the process of S34 is skipped, and the process proceeds to S35.

In the process of S35, the updated value of the internal register 11b is compared with the value of the initial value memory 13c.
Since the initial value of the update of the random number counter 13a is stored in the initial value memory 13c, if both values are equal (S
35: Yes), this means that the update of the random number counter 13a has been completed once. Therefore, in such a case, 2
The value of the byte initial value counter 13b is stored in the internal register 11
b (S36), the value of the internal register 11b is written to the initial value memory 13c and the random number counter 13a (S37, S38), and the initial value of the update of the random number counter 13a is changed.

On the other hand, if the value of the updated internal register 11b is not equal to the value of the initial value memory 13c (S3
5: No), since the updating of the random number counter 13a has not been completed yet, the processing of S36 and S37 is skipped, and the value of the internal register 11b updated in the processing of S32 to S34 is written to the random number counter 13a. (S3
8) Update the random number counter 13a. After that, another random number used in the control unit C is updated (S3).
9), the random number updating process ends.

FIG. 5 is a flowchart of the initial value counter updating process. Initial value counter update processing (S6, S2
In 2), via the internal register 11b of the CPU 11,
The value of the initial value counter 13b that counts the initial value of the update of the random number counter 13a is set to “+” within the range of “0 to 630 (0 to 276h)” of the update range of the random number counter 13a.
1 "at a time.

First, the value of the initial value counter 13b composed of 2 bytes is written into the 2-byte internal register 11b (S41). The value of the internal register 11b is incremented by 1 (S
42), the value of the internal register 11b after the addition is “631”
It is checked whether the above is true, that is, whether the value exceeds the update range value of the random number counter 13a (S43). If the value of the internal register 11b after the addition is “631” or more, (S
43: Yes), the value of the internal register 11b is cleared to "0" because the value exceeds the update range value of the random number counter 13a (S44). On the other hand, the internal register 11b after the addition
Is less than or equal to "630" (S43: No), since the value is within the update range of the random number counter 13a, the process of S44 is skipped, and the process proceeds to S45.

In the process of S45, the 68 system CPU 11
According to the byte write command, the value of the 2-byte internal register 11b is written to the initial value counter 13b in the order of the upper byte and the lower byte with one command (S45), and the initial value counter 13b is updated. In addition, 80 series C
In the PU, the value of the updated 2-byte internal register is 1
The data is written to the initial value counter 13b by two instructions in the order of the upper byte and the lower byte, byte by byte.

As described above, the initial value counter updating process is repeatedly executed during the remaining time until the next reset interrupt occurs in the reset interrupt process (S2).
2). Therefore, in the processing of S45, the internal register 1
When the next reset interrupt occurs after the upper byte of 1b is written to the initial value counter 13b and before the writing of the lower byte, the value of the lower byte of the internal register 11b is not written to the initial value counter 13b. 3 is executed.

For example, if the value of the initial value counter 13b is "1"
If “FFh”, the value of the internal register 11b is set to “200h” by the processing of S41 to S44. S45
When the upper byte of the internal register 11b is written into the initial value counter 13b by the processing described above, the value of the initial value counter 13b once becomes "2FFh", which is outside the update range of the random number counter 13a. Normally, immediately after that, the lower byte of the internal register 11b is written to the initial value counter 13b, and the value of the initial value counter 13b becomes the value of "200h". When the next reset interrupt occurs,
Writing of the lower byte is stopped, and the initial value counter 13
The value of b remains "2FFh".

When the value of the initial value counter 13b is used in the processing of S36 of the random number update processing (S7), the initial value of the update of the random number counter 13a is set to a value outside the update range. However, in the present embodiment, the initial value counter updating process is also performed before the random number updating process (S7) (S6), so that the value of the initial value counter 13b is out of the updating range of the random number counter 13a. Even when the value becomes the value, the value is stored in the random number counter 13 before the random number updating process (S7).
The value can be returned to a value within the update range of a. This is because in the initial value counter updating process, the value “631” or more is cleared to “0” (S43: Yes, S44). Therefore,
The value of the random number counter 13a can always be updated within a predetermined update range.

Further, as in the present embodiment, by executing the initial value counter updating process not only for the remaining time (S22) but also before the random number updating process (S7) (S6), the remaining time is insufficient. Even in this case, the initial value counter 13b
Can be surely updated.

FIG. 6 is a flowchart of the initial value counter updating process in the second embodiment. In the initial value counter updating process of the first embodiment, the value of the initial value counter 13b is updated by "+1" in the addition direction, and the updated value is written to the initial value counter 13b in the order of the upper byte and the lower byte. On the other hand, in the initial value counter updating process of the second embodiment, the value of the initial value counter 13b is updated by “−1” in the subtraction direction, and the updated value is transmitted to the initial value counter 13b in the order of the lower byte and the upper byte. Writing. The same parts as those in the first embodiment are denoted by the same reference numerals,
The description is omitted.

First, the value of the 2-byte initial value counter 13b is written to the 2-byte internal register 11b (S51). The value of the internal register 11b is subtracted by 1 (S
52), the value of the internal register 11b after the subtraction is "631
(277h) ”is checked (S53).
If the value of the internal register 11b before the subtraction is “0”, the value becomes “0FFFFh” by the subtraction. Therefore,
If the value of the internal register 11b after the subtraction is equal to or more than "631 (277h)" including "0FFFFh" (S53:
Yes), "630 (276h)" which is the maximum value of the update range of the random number counter 13a is written to the internal register 11b (S54). On the other hand, if the value of the internal register 11b after the subtraction is equal to or less than "630 (276h)" (S53: N
o), the process of S54 is skipped, and the process proceeds to S55.

In the processing of S55, the value of the lower byte of the 2-byte internal register 11b updated in the subtraction direction is written to the lower byte of the 2-byte initial value counter 13b (S55). The value of the upper byte of 11b is written to the upper byte of the 2-byte initial value counter 13b (S56). That is, the updated 2-byte value of the internal register 11b is written into the initial value counter 13b by two instructions, one byte at a time, in the order of the lower byte and the upper byte. The 80-system CPU can write the value of the internal register of 2 bytes to the initial value counter 13b in the order of the lower byte and the upper byte with one instruction by a two-byte write instruction.

As described above, the initial value counter updating process is repeatedly executed during the remaining time until the next reset interrupt occurs in the reset interrupt process (S2).
2). For this reason, the internal register 1
After the lower byte of 1b is written to the initial value counter 13b and before the writing of the upper byte by the processing of S56, the next reset interrupt may occur. Since the reset interrupt has the highest priority and is a non-maskable interrupt in which the start of the interrupt process cannot be prohibited, in such a case, the initial value counter updating process is performed without performing the process of S56. The process is forcibly terminated, and the process of S1 in FIG. 3 is executed. As a result, the value being written becomes the value of the updated initial value counter 13b.

For example, if the value of the initial value counter 13b is "2
00h ", the value of the internal register 11b of the CPU 11 is set to" 1FF "by the processing of S51 to S53.
h ”. The updated value is obtained from the internal register 11b in the order of the lower byte and the upper byte from the initial value counter 13b.
The value of the initial value counter 13b is temporarily set to "2FFh" by writing the lower byte (S5).
5) Then, by writing the upper byte, "1FF
h ”(S56), and the updating of the initial value counter 13b is completed. Therefore, if the next reset interrupt occurs after writing to the lower byte of the initial value counter 13b and before writing to the upper byte, the initial value counter 13b
The value of b is “2FFh”, which is a value outside the range of the original update range “0-630 (0-276h)”.

If the value of the initial value counter 13b is used in the processing of S36 in the random number update processing (S7), the initial value of the update of the random number counter 13a becomes a value outside the update range. However, in the present embodiment, the initial value counter updating process is also performed before the random number updating process (S7) (S6), so that the value of the initial value counter 13b is out of the updating range of the random number counter 13a. Even when the value becomes the value, the value is stored in the random number counter 13a before the random number updating process (S7).
Can be returned to a value within the update range of. In the initial value counter update process, a value equal to or greater than “631 (277h)” is “630 (2
76h) ”(S53: Yes, S
54). Therefore, the value of the random number counter 13a can always be updated within a predetermined update range.

In each of the above embodiments, the non-maskable reset interrupt processing corresponds to the interrupt processing according to claims 1 and 2, and the first update means corresponds to the random number update processing (S7) in FIG. To S34 and S38. Further, the second updating means corresponds to the initial value counter updating processing in S22, and the returning means corresponds to the initial value counter updating processing in S6 executed before the random number updating processing (S7).

As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be made without departing from the gist of the present invention. Can easily be inferred.

For example, in this embodiment, the random number counter 13
Before the random number updating process (S7) for updating a, the initial value counter updating process (S6) is executed, and the initial value counter 1 is updated.
The value of 3b has been returned to a value within the update range of the random number counter 13a. However, the present invention is not necessarily limited to such a method. For example, before writing the value of the initial value counter 13b to the random number counter 13a and the initial value memory 13c (before the processing of S36), the initial value counter 1
3b is checked, and the value is checked by the random number counter 13a.
If it is outside the update range of “631” or more, “0” or “630” is written to the initial value counter 13b,
The value of the initial value counter 13b may be returned to a value within the update range of the random number counter 13a, and the returned value may be written to the random number counter 13a and the initial value memory 13c.

The update of the value of the initial value counter 13b is performed after the value is once read into the internal register 11b of the CPU 11, but is read directly into the ALU in the CPU 11 without passing through the internal register 11b and updated. You may do it.

Hereinafter, modified examples of the present invention will be described. 3. The ball game machine according to claim 1, wherein said return means is constituted by third update means for updating the value of said initial value counter with a value within an update range of said random number counter. 3. The ball and ball game machine 1 wherein the updating means is executed at least once before the execution of the first updating means.

[0062] In the ball game machine or the ball game machine 1 according to claim 1, writing of the value updated by the second updating means to the initial value counter is performed by writing 2 bytes in the order of upper byte and lower byte. Is executed by a write command performed by one command.

In the ball game machine or the ball game machine 1 or 2 according to claim 1 or 2, the value of the initial value counter is set when the value of the random number counter matches the value of the initial value memory. The ball game machine 3 written in the random number counter and the initial value memory.

[0064]

According to the ball game machine of the present invention, the initial value of the update of the random number counter for determining the jackpot is not a fixed value but a value that is periodically changed. Even if the "hanging board" resets an invalid counter inside the apparatus when the machine is turned on, the value of the counter cannot be made to match the value of the random number counter. Therefore, there is an effect that it is impossible to grasp the timing of occurrence of the jackpot due to the “hanging board” or the like, and it is possible to prevent the fraud by the “hanging board” or the like.

In addition, the value of the initial value counter for counting the initial value of the update of the random number counter is repeatedly updated during the remaining time of the interrupt processing that is periodically executed. Since the length of the remaining time of the interrupt process changes according to the state of the game, it cannot be grasped by a “hanging board” or the like. Therefore, since the value of the initial value counter is repeatedly updated during the remaining time, there is also an effect that it is possible to prevent the value of the random number counter from being grasped by a "hanging board" or the like.

The value of the initial value counter is returned to a value within the range of updating the random number counter by the return means before writing to the random number counter and the initial value memory. Therefore, the value of the random number counter can be updated within the range of the original value to be updated, so that the probability of occurrence of a jackpot changes to an unexpected probability, or the initial value of the random number counter is updated. This has the effect of avoiding the problem of no longer being changed.

[Brief description of the drawings]

FIG. 1 is a front view of a gaming board of a pachinko gaming machine according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of the pachinko gaming machine.

FIG. 3 is a flowchart showing a reset interrupt process.

FIG. 4 is a flowchart showing a random number update process.

FIG. 5 is a flowchart showing an initial value counter update process.

FIG. 6 is a flowchart illustrating an initial value counter update process according to the second embodiment.

[Explanation of symbols]

 Reference Signs List 11 CPU of control unit 11b Internal register of CPU of control unit 13 RAM of control unit 13a Random number counter 13b Initial value counter 13c Initial value memory C Control unit P Pachinko game machine (ball game machine)

Continued on the front page (72) Inventor Yoshio Yamazaki 7-49 Haruoka-dori, Chikusa-ku, Nagoya-shi J-Tai Co., Ltd. (72) Inventor Hideaki Sato 7-49 Haruoka-dori, Chikusa-ku, Nagoya Jt. F-term (for reference) 2C088 AA33 BC30 BC45

Claims (2)

[Claims] 1. An interrupt process periodically executed, a random number counter, first updating means for updating the value of the random number counter by the interrupt process, and reading a value of the random number counter at a predetermined timing. Reading means for providing a predetermined game value to a player under predetermined conditions when the value of the random number counter read by the reading means matches one of predetermined values. An initial value memory for storing an initial value of the random number counter being updated; and at least two bytes for counting the initial value of the next update of the random number counter, the value being written to the initial value memory and the random number counter. An initial value counter composed of: and a value of the initial value counter are read, and the value is updated in the addition direction within the range of updating the random number counter, and the updated value is Second updating means for writing to the initial value counter in the order of upper byte and lower byte, and repeatedly executed during the remaining time until the next interrupt processing is performed by the interrupt processing; and And a return means for returning a value to a value within an update range of the random number counter before writing the value to the random number counter and the initial value memory. 2. An interrupt process that is periodically executed, a random number counter, a first updating unit that updates the value of the random number counter by the interrupt process, and reads a value of the random number counter at a predetermined timing. Reading means for providing a predetermined game value to a player under predetermined conditions when the value of the random number counter read by the reading means matches one of predetermined values. An initial value memory for storing an initial value of the random number counter being updated; and at least two bytes for counting the initial value of the next update of the random number counter, the value being written to the initial value memory and the random number counter. And the value of the initial value counter is read out, the value is updated in the subtraction direction within the range of updating the random number counter, and the updated value is Second updating means for writing to the initial value counter in the order of the lower byte and the upper byte, and repeatedly executed during the remaining time until the next interrupt processing occurs by the interrupt processing; And a return means for returning a value to a value within an update range of the random number counter before writing the value to the random number counter and the initial value memory.