JPH05134929A - Data access control system - Google Patents

Abstract

PURPOSE:To provide a data access control system which never breaks the data area of a memory. CONSTITUTION:The program address area included in a program area 3 is stored in a register memory 5 together with the data address area included in a data area 4. A comparison check circuit 6 checks the program address area and the data address area stored in the memory 5 and the program address and the data address informed from a CPU 2 when a write instruction is carried out. If the write data address is included in the data address area, the data are written into the area 4 from the CPU 2. If the write data address is not included in the data address area, the occurrence of a program fault is reported to the CPU 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data access control system, and more particularly to preventing data destruction on a memory.

[0002]

2. Description of the Related Art Conventionally, in this type of data access control method, a data area on a memory can be written when all write instructions are executed.

[0003]

In this conventional data access control method, since a write command can write to the data areas on all the memories, when a program failure occurs, the data on the memory which should not be written is originally written. It happens that data is written in the data area of, and the failure of the program cannot be recognized,
There was a problem that the data area on the memory was destroyed.

It is an object of the present invention to provide a data access control system which does not destroy the data area on the memory.

[0005]

In order to achieve the above object, the present invention provides a memory comprising a program area and a data area, a central processing unit, a program address area in the program area, and a program. Therefore, a comparison check is performed between the registered memory that stores the data address area in the data area to be written, the program address where the write command exists in the program area, and the program address area stored in the registered memory, and , A comparison check circuit for performing a comparison check of the data address written by the instruction and the data address area stored in the registered memory.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. FIG. 2 is a memory map of one embodiment of the present invention.
As shown in FIGS. 1 and 2, one embodiment of the present invention is a memory 1 including a program area 3 and a data area 4.
A central processing unit (hereinafter referred to as CPU) 2, a program address area in a program area 3, and a registration memory 5 for storing a data address area in a data area 4 to be written according to a program, A comparison check is performed between the program address in the program area 3 where the write command exists and the program address area 7 stored in the registration memory 5, and the data address to be written by the command is stored in the registration memory 5. It is composed of a comparison check circuit 6 for performing a comparison check with the data address area 8.

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. First, the CPU 2 stores the program address area in the program area 3 and the data address area in the data area 4 to be written according to the program in the registration memory 5, and the data is executed by executing the instruction in the program area 3. When the area 4 is written, the comparison check circuit 6 is notified of the program address at the time of executing the instruction.

The comparison check circuit 6 checks the program address area 7 and the data address area 8 stored in the registration memory 5 and the program address and the data address at the time of execution of the write command notified from the CPU 2, and checks each address. According to the area check result, if the write data address is in the data address area 8, data is written from the CPU 2 to the data area 4, and if the write data address is not in the data address area 8, a program failure has occurred. Is notified to the CPU 2. As described above, according to this embodiment, at the time of writing data, it is possible to prevent the data from being destroyed in the memory and to instantly notify that the program failure has occurred.

[0010]

As described above, according to the present invention, by performing address management, the write data address is
If it is in the data address area stored in the registration memory, write the data in the data area. If the write data address is not in the data address area stored in the registration memory, write the data in the data area. Since the above is not performed, the effect of preventing the data destruction on the memory and the effect of notifying the CPU that the instruction cannot be accepted can be recognized that the program failure has occurred instantly.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a memory map of one embodiment of the present invention.

[Explanation of symbols]

 1 Memory 2 Central Processing Unit 3 Program Area 4 Data Area 5 Registered Memory 6 Comparison Check Circuit 7 Program Address Area 8 Data Address Area

Claims (1)

[Claims] 1. A registration for storing a memory composed of a program area and a data area, a central processing unit, a program address area in the program area, and a data address area in the data area to be written according to a program. The memory and the program address where the write command exists in the program area and the program address area stored in the registered memory are compared and checked, and the data address written by the instruction and the data stored in the registered memory A data access control method comprising a comparison check circuit for performing a comparison check with an address area.