JPH0287239A - Microprogram processor - Google Patents

Abstract

PURPOSE:To prevent limitation from being given even in the case of address allocation on a control memory by stopping the processing of a micro-instruction word when execution permission information and the contents of an execution level display means show noncoincidence. CONSTITUTION:The micro-instruction word read by a next instruction address 5-a, which is outputted from a micro-instruction control part 5, is set to a micro- instruction register 2 and the execution permission information are set to a register 3 respectively. Here, the contents of a current level register 7 to hold the execution level of a micro-instruction and the contents of the register 3 receive a check by a comparing and deciding circuit 6. When it is decided in the comparing and deciding circuit 6 that the coupling of both contents is unfair, it is instructed by a signal line 6-1 to the micro-instruction control part 5 that the execution of the micro-instruction word is suppressed. Thus, any limitation is not given in the case of the address allocation on the control memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram processing device, and particularly to a microprogram processing device configured such that the microprogram has a plurality of execution levels and interrupt processing is performed at a predetermined execution level depending on the processing content. The present invention relates to a microprogram processing device.

Traditionally, microprogram malfunction prevention technology includes:
There are methods for determining whether the microprogram address has exceeded a certain range, and methods for detecting that the same location is being looped.

Of the conventional methods mentioned above, the former requires that the firmware module to perform a certain process fall within a certain address range, and this is especially true for devices with horizontal microinstructions, due to restrictions on address allocation in control memory. Become. Furthermore, the latter method has the disadvantage of requiring a large amount of hardware for stall monitoring.

Therefore, the present invention was made to solve the drawbacks of the conventional ones, and its purpose is to eliminate the need for complicated hardware and to improve control memory. An object of the present invention is to provide a microprogram processing device that does not impose any restrictions on address assignment.

According to the present invention, there is provided a microprogram processing device in which a microprogram has a plurality of execution levels and is configured to perform a process of interrupting a predetermined execution level depending on the processing content. , a control memory having a storage section for storing execution permission information in advance for instructing the microprogram execution level at which these microinstructions can be executed in correspondence with the microinstruction words in a storage section for storing the microinstruction words; , execution level display means for displaying the current microprogram execution level, and comparison means for comparing the execution permission information corresponding to the microinstruction word read from the control memory to be executed with the contents of the execution level display means. There is obtained a microprogram processing device characterized in that the processing of the microinstruction word is stopped when the comparison result shows a mismatch.

Xc] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, 1-1 and 1-2 are control memories; 1-1 and 1-2 are control memories;
2 is an area for storing ordinary microinstructions, and 1-1 is an area for storing execution permission information, which is a feature of the present invention. 2 is a microinstruction register that stores the microinstruction word read from the control memory; 3 is an execution permission register that stores execution permission information; 4 is a microaddress register that stores the address in the control storage of the microinstruction register 2; 5 is a microinstruction control unit, 6 is a comparison/judgment unit which is one of the features of the present invention, 7 is a count level register indicating the level of the microprogram currently being executed, and 8 is a pre-pierce level register for storing the interrupt level. be. The current level register 7 consists of 4 bits, and the correspondence between its contents and levels is shown in FIG.

The microprogram processing device has five execution levels from level 0 to level 4, and interrupt processing is performed at a predetermined execution level according to each processing content.For example, execution level 0 is failure processing, execution It is assumed that level 1 is data chaining, execution level 2 is command chaining, etc. Therefore, the microprogram in the control memory consists of a unique part corresponding to each execution level and a part common to each level (for example, memory access processing).The microinstruction control unit 5 decodes and executes microinstructions. , the next instruction is determined, interrupt processing, etc. are controlled.

Next, the operation in this embodiment will be explained.

The microinstruction words in the control memory are stored by an external service processor (not shown) or the like. Next instruction address 5- output from microinstruction control unit 5
The microinstruction word read by a is set in the microinstruction register 2, and the execution permission information is set in the register 3. Here, the contents of the current level register 7, which holds the execution level of the microinstruction, and the contents of the register 3 are checked by the comparison/judgment circuit 6.

The check logic is as shown in FIG. 2. For example, if the contents of register t3 (consisting of 3 bits) are "011", only execution at execution level 3 is permitted. If the bus is checked here, the contents of the microinstruction register 2 will be executed normally. If there is an invalid combination in the comparison/judgment circuit 6 (for example, the current bell register 7
is "oioo" and the contents of register 3 are "011"), the signal line 6-
1 instructs the microinstruction control unit 5 to suppress execution of the microinstruction word. Microinstruction control unit 5
outputs a microinstruction execution inhibit signal (not shown) and instructs a control section (not shown) to stop the clock.

1. As explained above, according to the present invention, execution permission information is added to the control memory in addition to the microinstruction word, and by comparing this execution permission information with the execution level of the microprogram, This has the effect of providing a highly reliable microprogram processing device that can detect program malfunctions and that does not impose the same restrictions on address assignment on control storage.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between execution permission information and execution level, and FIG. 3 is a diagram showing the relationship between current bell register graph data and execution level. be. Explanation of symbols of main parts 1-1... Execution permission information storage section 1-2...
...Microinstruction word storage unit 5...Microinstruction control unit 6...Comparison judgment unit

Claims (1)

[Claims] (1) A microprogram has multiple execution levels,
A microprogram processing device configured to perform processing that interrupts a predetermined execution level depending on the processing content, and in addition to a storage section that stores microinstructions, there is also a storage section that can execute these microinstructions. a control memory having a storage section for storing execution permission information that instructs the microprogram execution level in advance in correspondence with these microinstruction words; an execution level display means for displaying the current microprogram execution level; a comparison means for comparing the execution permission information corresponding to the micro-instruction read from the micro-instruction with the contents of the execution level display means, and when the comparison result shows a mismatch, processing of the micro-instruction is performed. A microprogram processing device characterized by being configured to stop.