JPH01321521A - Information processor - Google Patents

Abstract

PURPOSE:To prefetch an instruction at a high speed after the cancel conditions are satisfied by retrying the instruction identified by an identification means and at the same time canceling the instruction set at the stage of a pipeline and its relative information by the subsequent instructions including the one to be retried. CONSTITUTION:A circuit 134-138 identifies the specific one of subsequent instructions when a register having the possibility of conflict produces a cancel instruction during a pipeline process. A circuit 139-142 recognizes the specific instruction that carried out the cancel together with the cancel instruction. Then a circuit 102 invalidates the register number designated by the cancel instruction out of those register numbers having the possibility of conflict. When the cancel conditions are satisfied, this satisfaction is checked in plural cycles and the number of the register to be invalidated with a request for cancel is invalidated. Thus an instruction can be prefetched at a high speed after the cancel conditions are satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides information for performing pipeline processing of an instruction such as a branch instruction, which cancels pipeline processing in response to the establishment of a pipeline cancel condition during pipeline processing. It relates to a processing device.

In general, branch instructions predict whether the address of the instruction to be executed next to the branch instruction is the branch destination address or the address following the branch instruction, and pipeline processing is performed continuously. When prediction of the address of the next instruction after a branch instruction fails, a pipeline processing cancellation instruction is issued based on the satisfaction of a pipeline processing cancellation condition in one predetermined cycle out of a plurality of cycles. By issuing this instruction, the correct branch destination instruction is retaken.

Furthermore, in this type of pipeline processing, an instruction to be executed next to a branch instruction, which is a subsequent instruction, is input before execution of a branch instruction, which is a preceding instruction, is completed. In other words, the preceding branch instruction instructs the arithmetic control unit to perform an operand operation, and writes (updates) the result of the operand operation to the same register.
If a subsequent instruction specifies successive operation, a register contention problem will occur, and this reading must be performed after the operand operation results are correctly reflected.

For this reason, in conventional systems, the address calculation by the subsequent instruction is started after waiting for the operand operation result in the arithmetic control unit by the preceding instruction.
As shown in Japanese Patent Publication No. 9088, an equivalent operand operation is performed using a dedicated arithmetic circuit prior to obtaining the operand operation result in the arithmetic control section, and
As shown in Japanese Patent Application No. 37, an address generating circuit that performs address calculation is made to be able to perform operations between operands, and the results of the operand operations are used to successively read registers for subsequent instructions.

Furthermore, even if a check mechanism is provided to check whether a preceding instruction and a subsequent instruction are in a conflicting relationship that instructs writing and successive output to the same register, multiple If the pipeline processing cancellation condition is checked in the cycle , and a cancellation instruction is issued in the cycle in which the condition is satisfied, the correspondence between the register number of the register having the above-mentioned conflicting relationship and the instruction that caused the cancellation becomes unclear. For this reason, there is a drawback that it is not possible to identify the register number of the register in which there is a possibility of a conflicting relationship occurring, which would otherwise have to be invalidated due to cancellation.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information processing apparatus that eliminates the above-mentioned drawbacks and speeds up the retaking of commands after the cancellation clause ft'' is established.

The apparatus of the present invention includes a determining means for determining whether a condition for canceling pipeline processing is met, and a determination signal from the determining means to determine which stage of the pipeline processing an instruction is in. an identification means for identifying whether the instruction should be re-processed; and a means for retrying the instruction identified by the identification means, and for retrying the instruction at a stage of the pipeline with subsequent instructions including the instruction targeted for retry. and means for canceling an instruction and its related information.

Example Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes an operation (OP
) An instruction register 1 containing a code field, a base field B, an index field A decoder 2 outputs a selection instruction signal indicating whether the selection instruction signal is a branch instruction, and when the selection instruction signal from the decoder 2 indicates a branch instruction, it selects "1", and when it indicates that it is not a branch instruction, it selects "0".

A selector 3 that selects a branch instruction identification value BICO, a branch instruction identification register 4 that stores a branch instruction identification value BICO, and an adder 5 that adds the branch instruction identification value BICO from this branch instruction identification register 4 and the selection result from the selector 3 are decoded. (D
) are ready for the stage.

The pipeline processing of this embodiment is this instruction decoding (D).
In addition to the stage, there is an address generation (A) stage, an address translation (T') stage, a memory succession (0) stage,
It consists of six stages: an arithmetic execution (E) stage and an arithmetic result storage (W) stage.

The addition result of adder 5 is branch instruction identification (fIBIC1 to B
1C5 is stored in registers 7 to 11 provided at each stage of the pipeline described above. Further, the addition result of the adder 5 is given to a register determination control section 6 which operates asynchronously with each stage of the pipeline described above. This register confirmation control unit 6 has a pipe structure, and includes a register group 61 to 65 for registering register numbers to be updated for the number of pipeline stages from A stage to W stage, and registers 61 to 65 for register numbers to be updated, and an adder 6. A register group 66-70 for storing addition results, and the register group 61-65.
It has register groups 71-75 that hold validity bits indicating whether or not valid data is held.

The contents of register groups 61-65, the contents of base field B of instruction register 1, and the index field
The register confirmation waiting match detection circuit 15 outputs a signal indicating that the processing of the preceding instruction has not been completed and instructs the instruction register 1 to continue holding the instruction if they match. It is provided in the D stage of one embodiment of the invention.

In the A stage of this embodiment, it is determined whether the prediction of the address of the instruction to be executed next to the branch instruction is successful or unsuccessful, and when the prediction fails, a signal indicating prediction failure is sent to the line 104.
A branch prediction determination circuit 12 is provided. Also, in the E stage of one embodiment, a branch prediction is performed to determine whether prediction of the address of an instruction to be executed next to a branch instruction is successful or unsuccessful, and outputs a signal indicating prediction failure to the line 105 when prediction fails. A determination circuit 14 is provided.

Next, due to branch Jl failure, the confirmation waiting registration validity bit is “0”.
The instruction circuit 13 that instructs the setting to `` will be explained in detail with reference to FIGS. 1 and 2.

Referring to FIGS. 1 and 2, the instruction circuit 13 receives a prediction failure signal from the branch prediction judgment circuit 14 in the E stage via the game 1-131.
, an AND gate 132 which takes the logical product of the negative output of this gate 131 and the prediction failure signal applied from the branch prediction decision port FR112 in the A stage via the line 104;
In response to the output of the AND gate 132, the 1! j, obtained branch instruction identification fl
A selector 133 selects at BICl and selects a branch instruction identification value BIC4 given from register 10 via line 10 (3) in response to the output of game 1-131, and the selection result from this selector 133 and register 66- Comparison circuit group 134-138 for comparing the addition result from 70
, and an OR gate group 139-142 that takes the logical sum of the outputs from these comparison circuits 134-138. The stage recognizes that the information is due to an incorrect stream instruction due to a branch prediction failure, and invalidates the validity bits of the register group corresponding to the stage above the register storing the matched value. , outputs a signal to the line 102 indicating that a reread instruction is to be set due to a failure in branch prediction to the instruction register 1.

The address calculation according to one embodiment of the present invention is
As shown in Publication No. 8, a base register (BR) reads out a base address based on the contents of base field B.
) 17, a register 19 that stores the base address from this pace register (BR) 17, a general-purpose register (GR) 18 that reads the index address according to the contents of the index field X, this general-purpose register (GR) 18
a register 20 for storing an index address from;
Register 21 for storing the displacement of displacement field D, these registers 19-2
A logical address register (LAR) 23 stores the addition result of the address adder (AA) 22 as a logical address based on the contents of address adder 1, and converts the logical address of this logical address register (LAR) 23 into a physical address. Address translation buffer (TL
B) 24, a physical address register (PAR) that stores the physical address converted by this TLB 24
25, an operand cache memory (
OC14) 26, this operand cache memory 2
Operand register (O
R) 27, an arithmetic unit (ALU) 28 that performs calculations based on the operands from the operand register 27, and two registers that hold the calculation results from the calculation unit 28.

Referring to FIGS. 1 and 3, the pending registration register set instruction control unit 16 includes an OR circuit 161 that calculates the logical sum of the validity bits provided via the line 101 from any of the register groups 71 to 75; An OR circuit 162 is provided which calculates the logical sum of the logical sum result of the OR circuit 161 and the computation end signal 305 indicating storage of the computation result in the register 29. The output of this OR circuit N162 is given to the register group 61-75 as a set instruction signal.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIGS. 1 to 4, instructions a-g
Of these, instructions s, c, e, and f are branch instructions, and O
marked c, e and f. Failure in branch prediction of instruction C is determined in E stage circuit 14 at machine cycle T9. Instruction d- indicates a retry due to branch prediction failure. R6 to Rf and Rd- indicate update register numbers in each instruction, and in response to determination of branch prediction failure, the contents of register 10 and the contents of register group 66-70 are compared by comparison circuit group 134-138. , when any of the ratio axis results match, the OR circuits 1139-141 generate a signal that invalidates the validity bit of the stage above the stage that showed the match, and @
102 to register groups 71-74 to invalidate them.

Note that the 81Ci value of the stage of branch prediction failure is added by 1 to the 81CO value in register 4, and the cell l-1 is added to register 4, and the branch instruction identifier is reassigned.

The operations of these instructions will be described in detail below.

At timing 'rO, instruction a is stored in instruction register 1, and "OII" is set in register 4.

Next, at timing 1'1, the contents of fields B and X of instruction a are set in registers 19 and 20 by reading the address from BR17 and OR,18. Also,
The contents of field D are set in register 21. At the same time, a branch instruction is set in register 1. Note that since the instruction a set at timing 'l'0 is not a branch instruction, the selector 3 selects "0" based on the decoding result of the decoder 2. As a result, the adder 5 selects "0".
Addition of 10 “0” is performed, and the addition result “0” is added to registers 4 and 7 and register 6 of register confirmation control unit 6.
6. At the same time as '0' is stored in the register 66, a register number R is stored in the register 61.

Further, at timing T2, the address of the instruction a is generated by the address adder 22 and set in the logical address register LAR23. Further, the address before addition related to the instruction C is also stored in at least one of the registers 19-21, and the instruction C is set in the register 1. Since the instruction set at timing TI is decoded by the decoder 2 as a branch instruction, the selector 3 selects "1". As a result, the adder 5 performs addition of "0, ten" and "1", and the addition result is "
1" is set in registers 4.7 and 66. Note that register 8 is set with °"0 from register 7, and register 67 is set with "0" from register 66. At this time, register The register number "R5" is set in the register 61 corresponding to the register 66, and the register number "R6'" is set in the register 62 corresponding to the register 67.

When the operation continues in this manner until timing T9,
A prediction failure signal is applied via line 105 from the determination circuit 14 of the E stage.

Referring to FIGS. 2 and 4, this signal is
31 to the selector 133, selects the value "2'° of the register 10, and supplies it to the comparison circuit group 134-138. The comparison circuit group 134-138 selects the value "2" of the register 10 and the register group 66- 70 and outputs "1" from the comparator circuit 135 that finds a match.This output "1" is given to the orter 1 to groups 139-142
The logical sum result “1” is sent to timing 1゛1 via @102
0 invalidates the validity bits of the register group 71-73 and sets a redo instruction d- to register 1.

Referring to FIGS. 1 and 4, the value "2" set in the register 10 at timing 'r9 is incremented by +1 and stored in the register 4 as 1-. In this way, after the cancellation condition is satisfied, the command can be retaken and the status of the song can be set within the next machine cycle.

As explained above, according to the present invention, registers that may have a conflicting relationship such as a preceding instruction and a subsequent instruction instructing writing and successive writing to the same register are circuits 134-138 for identifying which instruction is due to a subsequent instruction when cancellation is applied during line processing;
When a cancellation occurs, circuits 139-142 recognize which instruction is the canceled instruction along with the cancellation instruction, and the preceding instruction and the subsequent instruction instruct writing and continuing to the same register. By having a circuit 102 that invalidates register numbers that should be invalidated by cancellation among register numbers registered as registers that may have a conflicting relationship such as
If the pipeline processing cancellation condition is met during pipeline processing, check whether the pipeline processing cancellation condition is met in multiple cycles for the instruction to cancel the pipeline processing, and if the cancellation condition is met, cancel the pipeline processing. When canceling, the register number of the register that should be invalidated due to the cancellation among the registers that may have a conflicting relationship can be invalidated, which speeds up the retaking of the instruction after the cancellation condition is satisfied. It has the effect of being able to be transformed into

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a register determination controller 6, register groups 1.7 and 1 of the embodiment.
0 and the instruction circuit 13, FIG. 3 is a diagram showing the relationship between the register confirmation waiting control section 6 and the confirmation waiting registration register set instruction control section 16 of one embodiment, and FIG. FIG. 3 is a diagram for explaining the operation of one embodiment. Explanation of codes of main parts 1...Instruction register 2...Decoder 3...Selector 5...Adder 6...Waiting for register confirmation Control unit 12.14...Determination circuit 15...Register confirmation match detection circuit 16...
...Confirmation (41 Registration register set j/Instruction control unit 22...Address adder 24...TLn 26...Operand cache memory 28...
...ALU

Claims (1)

[Claims] A determining means for determining whether a condition for canceling pipeline processing is satisfied, and in response to a condition satisfaction determination signal from this determining means, an instruction at which stage in the pipeline processing is an instruction that requires redoing the processing. an identification means for retrying the instruction identified by the identification means, and means for canceling an instruction in a pipeline stage and its related information in an instruction subsequent to the retry instruction, including a retry instruction; An information processing device comprising: