JPH07113890B2 - Information processing equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing apparatus for canceling pipeline processing during pipeline processing in response to the establishment of a pipeline cancel condition, for example, pipeline processing of an instruction such as a branch instruction. Regarding

2. Description of the Related Art Generally, a branch instruction predicts whether the address of the instruction to be executed next to the branch instruction is the branch destination address or the address next to the branch instruction, and continuously performs pipeline processing. When the prediction of the address of the instruction next to the branch instruction fails, one of the plurality of cycles is limited to a predetermined cycle and a pipeline processing cancel instruction is issued when the pipeline processing cancel condition is satisfied. By issuing this instruction, the correct branch destination instruction is retaken.

In addition, in this type of pipeline processing, an instruction to be executed next to a branch instruction, which is a subsequent instruction, is input before execution of a branch instruction, which is a preceding instruction, is completed. That is, the preceding branch instruction instructs the operand operation in the operation control unit, and the operand operation result is written (updated) in the register
If the subsequent instruction specifies to read, a register conflict problem occurs, and this read must be performed after the operand operation result is correctly reflected.

For this reason, in the conventional system, the address calculation by the subsequent instruction is started after waiting for the operand operation result in the operation control section by the preceding instruction to be obtained.
As shown in Japanese Patent Laid-Open No. 88-88, prior to obtaining an operand arithmetic result in the arithmetic control unit, an equivalent arithmetic operation is performed by a dedicated arithmetic circuit, and as shown in Japanese Patent Laid-Open No. 61-90237, address calculation is performed. It has been made possible to perform an arithmetic operation between operands in an address generation circuit for performing the operation, and use the operand arithmetic result for register reading of a subsequent instruction.

Further, even if a check mechanism for checking whether the preceding instruction and the succeeding instruction are in a competing relationship for instructing writing and reading to the same register is provided, a plurality of instructions are provided for an instruction for canceling pipeline processing. If the pipeline processing cancel condition is checked in the cycle and a cancel instruction is issued in the cycle in which the condition is satisfied, the correspondence relationship between the register number of the register having the above-mentioned conflict relationship and the canceled instruction becomes unknown. For this reason, there is a drawback in that the register number of a register that may have a conflict relationship that must be invalidated due to cancellation cannot be identified.

OBJECT OF THE INVENTION It is an object of the present invention to provide an information processing apparatus which eliminates the above-mentioned drawbacks and speeds up instruction re-execution after a cancel condition is satisfied.

According to the present invention, in response to an input of a branch instruction, an information processing apparatus for performing pipeline processing while performing branch prediction processing for predicting an address to be executed next to this branch instruction, In response to the failure of (1), an information processing apparatus including an invalid register instructing means for outputting information indicating that the write destination register of the instruction after the branch instruction is invalid.

The invalid register instruction means assigns a branch instruction number assigning means for assigning different numbers to the instruction being executed, and the register number to be written by the instruction being executed, to the branch instruction immediately before the branch instruction. Register number holding means for holding together with the branch instruction number given by the number giving means, and judging means for outputting the branch instruction number given by the branch instruction number giving means to this branch instruction in response to a branch prediction failure And the branch instruction number output by the determining means and the branch instruction number held by the register number holding means are compared to invalidate the write destination register of the instruction after the branch instruction. And means for outputting information indicating that.

EXAMPLES Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention is an operation (OP).
An instruction register 1 having a code field, a base field B, an index field X, a displacement field D, and a storage destination field R for the operation result,
Decoder 2 that decodes the OP code in the OP code field of this instruction register 1 and outputs a selection instruction signal indicating whether or not it is a branch instruction, and "1" when the selection instruction signal from this decoder 2 indicates a branch instruction. To select "0" to indicate that the branch instruction is not a branch instruction, a branch instruction identification register 4 that stores the branch instruction identification value BIC0, and a branch instruction identification value from the branch instruction identification register 4
An adder 5 for adding the selection results from BIC0 and the selector 3 is provided in the instruction decoding (D) stage.

The pipeline processing of this embodiment decodes this instruction (D).
In addition to the stages, the address generation (A) stage, the address conversion (T) stage, the memory read (O) stage, the operation execution (E) stage and the operation result storage (W) stage are included.

The addition result of the adder 5 is stored as the branch instruction identification values BIC1 to BIC5 in the registers 7 to 11 provided in each stage of the above pipeline. Further, the addition result of the adder 5 is given to the register fixed wait control unit 6 which operates asynchronously with each stage of the above-mentioned pipeline. The register confirmation waiting control unit 6 has a pipe structure, and register groups 61-65 for registering register numbers to be updated for the number of pipeline stages from the A stage to the W stage.
Register group 66-70 for storing the addition result of the adder 5 and register group 71-75 for holding the validity bit indicating whether or not valid data is held in the register group 61-65.
have.

The contents of the register groups 61-65 are compared with the contents of the base field B and the contents of the index field X of the instruction register 1, and if they match, a signal indicating that the processing of the preceding instruction is not completed is output, The register-determined wait coincidence detection circuit 15 for instructing the instruction register 1 to continue holding the instruction is provided in the D stage of the embodiment of the present invention.

In the stage A of this embodiment, it is determined whether or not the prediction of the address of the instruction to be executed next to the branch instruction is successful or unsuccessful, and when the prediction fails, a signal indicating a prediction failure is output to the line 104. The circuit 12 is provided. Also in the E stage of one embodiment, the branch prediction which determines whether the prediction of the address of the instruction to be executed next to the branch instruction succeeds or fails, and outputs a signal indicating the prediction failure to the line 105 when the prediction fails. The determination circuit 14 is provided.

Next, the instruction circuit 13 for instructing to set the fixed waiting registration validity bit "0" due to branch prediction failure will be described in detail with reference to FIGS.

Referring to FIG. 1 and FIG. 2, the instruction circuit 13 receives a prediction failure signal given from the branch prediction judgment circuit 14 in the E stage via the line 105.
Negative output of 31 and branch prediction judgment circuit 12 in the A stage
From the AND gate 132 which takes the logical product with the prediction failure signal given from the line 104 to the branch instruction identification value BIC1 given from the register 7 via the line 103 in response to the output of the AND gate 132. A selector 133 for selecting the branch instruction identification value BIC4 given from the register 10 through the line 106 in response to the output of 131, and a comparison circuit for comparing the selection result from this selector 133 with the addition result from the registers 66-70. A group 134-138, and an OR gate group 139-142 for ORing the outputs from these comparison circuits 134-138,
When a match occurs in any of the comparison circuit groups 134 to 138, it is recognized that the stage above the stage in which the match occurs is the information by the instruction of the wrong stream due to the branch prediction failure, and the value in which the match occurs. From the stage of the register that stores the register to the upper stage, the validity bit of the register group corresponding to the upper stage is invalidated, and a signal for instructing to set the re-reading instruction is given to the instruction register 1 due to a branch prediction failure.
Output to 2.

The address calculation according to one embodiment of the present invention is, as shown in Japanese Patent Publication No. Sho 57-9088, a base register (BR) 17 for reading a base address according to the contents of the base field B, and from this base register (BR) 17. Register 19 for storing the base address of the general purpose register (GR) 1 for reading the index address according to the contents of the index field X
8, register 20 that stores the index address from this general-purpose register (GR) 18, register 2 that stores the displacement of displacement field D
1, an address adder (AA) 22 that calculates an address based on the contents of these registers 19-21, a logical address register (LAR) 23 that stores the addition result of this address adder (AA) 22 as a logical address, An address translation buffer (TLB) 24 that translates the logical address of the logical address register (LAR) 23 into a physical address, a physical address register (PAR) 25 that stores the physical address translated by this TLB 24, and a physical address register 25 Operand cache memory (OCM) 26 that reads the operand by physical address, this operand cache memory 2
Operand register (O
R) 27, an arithmetic unit (ALU) 28 that operates based on the operand from this operand register 27, and a register 29 that holds the arithmetic result from this arithmetic unit 28.

Referring to FIG. 1 and FIG. 3, the fixed wait registration register set instruction control unit 16 is an OR circuit 161 for ORing the validity bits given from any of the register groups 71-75 through the line 101. The OR circuit 162 is provided with an OR circuit 162 which takes the logical sum of the OR result of the OR circuit 161 and the operation end signal 305 indicating the storage of the operation result in the register 29. The output of the OR circuit 162 is used as a set instruction signal in the register group 61-75.
Given to.

Next, the operation of one embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIGS. 1 to 4, instructions a-g
Among these, instructions b, c, e and f are branch instructions, and are indicated by circled b, c, e and f. The branch prediction failure of the instruction c is judged in the circuit 14 at the E stage at the time of machine cycle T9. Instruction d'indicates a retry due to a branch prediction failure. R _{a to} R _f and R _d ′ indicate update register numbers in each instruction, and in response to the determination of branch prediction failure, the contents of the register 10 and the contents of the register groups 66-70 are compared circuit groups 134-138. When any of the comparison results match, the OR circuit group 139-141 sends a signal for invalidating the validity bit of the stage above the stage showing the match.
Generated by the above, and given to the register groups 71-74 via the line 102 to invalidate.

The BIC0 value of the register 4 is incremented by 1 for the BICi value of the stage of the branch prediction failure, and is reset in the register 4 to reassign the branch instruction identifier.

The operation of these instructions will be described in detail below.

At timing T0, instruction a is stored in instruction register 1,
“0” is set in the register 4.

Next, at timing T1, the contents of the fields B and X of the instruction a are read from BR17 and GR18, and the register is read.
Set to 19 and 20. The contents of field B are set in the register 21. With this register 1
The branch instruction b is set to. Since the instruction a set at the timing T0 is not a branch instruction, "0" is selected by the selector 3 according to the decoding result of the decoder 2. As a result, the adder 5 performs addition of "0" + "0", and the addition result "0" is stored in the registers 4 and 7 and the register 66 of the register fixed wait control unit 6. At the same time that "0" is stored in the register 66, the register number _Ra is stored in the register 61.

Further, at timing T2, the address of the instruction a is generated by the address adder 22 and set in the logical address register LAR23. The address before addition related to the instruction b is also stored in at least one of the registers 19-21, and the instruction C is set in the register 1. The instruction b set at the timing T1 is decoded as a branch instruction by the decoder 2, so that "1" is selected by the selector 3. As a result, in the adder 5, “0” +
"1" is added, and the addition result "1" is set in registers 4, 7 and 66. The register 8 is set to "0" from the register 7, and the register 67 is set to "0" from the register 66. Register number "R _c" is set in the register 62 corresponding to the register number "R _b" Kamata register 67 to the register 61 corresponding to the time register 66.

In this way, when it operates until timing T9, E
A prediction failure signal is provided via line 105 from the stage decision circuit 14.

Referring to FIGS. 2 and 4, this signal is gate 13
The value "2" of the register 10 is given to the selector 133 via 1 and given to the comparison circuit groups 134-138. Comparison circuit group
134-138 compare the value "2" of the register 10 with the values of the register groups 66-70, and output "1" from the compared comparison circuit 135. This output "1" is given to the OR gate group 139-142, and the logical sum result "1" invalidates the validity bit of the register group 71-73 at timing T10 via the line 102 and the redo instruction is given to the register 1. Set d '.

Referring to FIGS. 1 and 4, the value “2” set in the register 10 at timing T9 is incremented by 1 and set in the register 4. In this way, it is possible to perform instruction re-execution and other status setting after the cancellation condition is satisfied within the next machine cycle.

Effects of the Invention As described above, according to the present invention, a pipeline processing is performed on a register in which a preceding instruction and a subsequent instruction may have a conflicting relationship in which writing and reading are instructed to the same register. Circuits 134-138 that identify which instruction is a subsequent instruction when canceled, and a circuit that recognizes which instruction the canceled instruction is, together with a cancel instruction, when the cancel is applied
139-142 and the register number registered as a register in which the preceding instruction and the following instruction may have a conflicting relationship in which writing and reading are instructed to the same register,
By having a circuit 102 for invalidating a register number that should be invalidated by canceling, if a pipeline processing cancel condition is satisfied during pipeline processing, the pipe is processed in a plurality of cycles for an instruction to cancel the pipeline processing. If the line processing cancel condition is satisfied, and if the cancel condition is satisfied, and the pipeline processing is canceled, it must be invalidated due to the cancellation in the register that may have the conflicting relationship. Since the register number of the register that does not become invalid can be invalidated, there is an effect that the instruction re-execution after the cancellation condition is satisfied can be speeded up.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a relationship between a register confirmation waiting control unit 6, register groups 1, 7 and 10 and an instruction circuit 13 of the embodiment, and FIG. FIG. 4 is a diagram showing the relationship between the register fixed wait control unit 6 and the fixed wait registration register set instruction control unit 16 in one embodiment, and FIG. 4 is a diagram for explaining the operation of one embodiment of the present invention. Explanation of symbols of main part 1 …… Instruction register 2 …… Decoder 3 …… Selector 5 …… Adder 6 …… Register fixed wait control unit 12,14 …… Judgment circuit 15 …… Register fixed wait match detection circuit 16 …… … Fixed waiting registration register set instruction control unit 22 …… Address adder 24 …… TLB 26 …… Operand cache memory 28 …… ALU

Claims (1)

[Claims] 1. A pipeline process is performed while performing a branch prediction process for predicting an address to be executed next to this branch instruction in response to the input of a branch instruction, and after this branch instruction in response to a branch prediction failure. And an invalid register instructing unit that outputs information indicating that the write destination register of the instruction is invalid, wherein the invalid register instructing unit assigns different numbers to the instruction being executed. An instruction number giving means, a register number holding means for holding the register number to be written by the instruction being executed together with the branch instruction number given by the branch instruction number giving means to the branch instruction immediately before this instruction; A judgment means for outputting the branch instruction number given by the branch instruction number giving means to the branch instruction in response to the prediction failure, and the decision means. The output branch instruction number is compared with the branch instruction number held by the register number holding means, and information indicating that the write destination register of the instruction after this branch instruction should be invalidated is output. An information processing apparatus comprising: