CN112835842A - Terminal sequence processing method, circuit, chip and electronic terminal - Google Patents
Terminal sequence processing method, circuit, chip and electronic terminal Download PDFInfo
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- CN112835842A CN112835842A CN202110246956.XA CN202110246956A CN112835842A CN 112835842 A CN112835842 A CN 112835842A CN 202110246956 A CN202110246956 A CN 202110246956A CN 112835842 A CN112835842 A CN 112835842A
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
Abstract
The embodiment of the application provides an end sequence processing method, an end sequence processing circuit, a chip and an electronic device, wherein the end sequence processing method is applied to the end sequence processing circuit, the end sequence processing circuit is located outside a data access unit, the end sequence processing circuit acquires source data from a memory, the data access unit acquires target data from the end sequence processing circuit, and the end sequence processing method comprises the following steps: determining an endian processing mode for processing the source data into the target data; determining the data access width when the data access unit acquires the target data; and performing endian processing on the source data according to the data access width and the endian processing mode to obtain the target data. According to the embodiment of the application, the endian processing is performed on the endian processing circuit outside the data access unit, so that the data access unit does not need to use extra clock cycles to perform the endian processing, and the consumption of the clock cycles of the data access unit is reduced.
Description
Technical Field
The embodiment of the application relates to the technical field of circuits, in particular to an end sequence processing method, a circuit, a chip and an electronic terminal.
Background
In various application scenarios, such as a screen-swiping display of a smart band/watch, or a large amount of fragmented accesses, the data access unit on the chip needs to perform an endian conversion process to access the external memory to obtain the target data. The endian conversion processing is implemented in the data access unit based on a software layer, which may cause the data access unit to use an extra instruction cycle to execute the endian conversion processing, resulting in a large consumption of clock cycles.
Disclosure of Invention
In view of the above, an objective of the present invention is to provide an end-sequence processing method, circuit, chip and electronic device, which overcome or alleviate the above-mentioned drawbacks in the prior art.
In a first aspect, an embodiment of the present application provides an endian processing method, which is applied to an endian processing circuit, where the endian processing circuit is located outside a data access unit, the endian processing circuit obtains source data from a memory, and the data access unit obtains target data from the endian processing circuit, and the endian processing method includes:
determining an endian processing mode for processing the source data into the target data;
determining the data access width when the data access unit acquires the target data;
and performing endian processing on the source data according to the data access width and the endian processing mode to obtain the target data.
Optionally, in an embodiment of the present application, the performing endian processing on the source data according to the data access width and the endian processing mode to obtain the target data includes:
determining endian processing logic according to the data access width and the endian processing mode;
and performing end sequence processing on the source data according to the end sequence processing logic to obtain the target data.
Optionally, in an embodiment of the present application, the endian processing logic is at least one of a 4-byte endian processing logic, a 2-byte endian processing logic, and a single-byte endian processing logic.
Optionally, in an embodiment of the present application, if a data access width when the data access unit obtains the target data is a single byte, the endian processing circuit obtains the data access width of the source data from the memory as the single byte;
and, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: and according to the single-byte endian processing logic, carrying out endian processing on the source data to obtain the target data, so that the endian of the target data is the same as the endian of the source data.
Optionally, in an embodiment of the present application, if the data access width when the data access unit acquires the target data is 2bytes, the endian processing circuit acquires the data access width of the source data from the memory, where the data access width is 2 bytes;
and, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: according to the 2-byte endian processing logic, the source data is processed in an endian manner to obtain the target data, so that the endianness between 2bytes in the target data is the same as or opposite to the endianness between 2bytes in the source data.
Optionally, in an embodiment of the present application, if the data access width when the data access unit acquires the target data is 4 bytes, the endian processing circuit acquires the data access width of the source data from the memory, where the data access width is 4 bytes;
and, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: according to the 4-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 4 bytes in the target data is the same as or opposite to the endian between 4 bytes in the source data, or so that the endian between the first 2bytes in the target data is opposite to the endian between the first 2bytes in the source data, and the endian between the last 2bytes in the target data is opposite to the endian between the last 2bytes in the source data.
Optionally, in an embodiment of the present application, the determining an endian processing mode for processing the source data into the target data includes: and determining an endian processing mode for processing the source data into the target data according to a mode variable value acquired from an endian processing mode configuration register.
Optionally, in an embodiment of the present application, the number of the endian processing modes is multiple, and correspondingly, multiple endian processing mode identifiers are stored in the endian processing mode configuration register, and one endian processing mode identifier has one of the mode variable values, so that one of the mode variable values corresponds to one of the endian processing modes.
Optionally, in an embodiment of the present application, the determining an endian processing mode for processing the source data into the target data includes: and configuring the mode variable value corresponding to each endian processing mode in the endian processing mode configuration register according to the endian processing configuration data.
Optionally, in an embodiment of the present application, the endian processing mode configuration register is configured on the data access unit.
Optionally, in an embodiment of the present application, the memory is a memory of a serial peripheral interface supporting a 4-line operating mode, and the source data is transmitted to the endian processing circuit through the serial peripheral interface.
Optionally, in an embodiment of the present application, before the determining an endian processing mode for processing the source data into the target data, the determining includes: and judging whether the memory is in a memory mapping mode, if so, determining to process the source data into an end sequence processing mode of the target data.
Optionally, in an embodiment of the present application, the data access unit includes at least one of a central processing unit, a micro control unit, and a direct memory access controller.
In a second aspect, an embodiment of the present application provides an endian processing circuit, where the endian processing circuit is located outside a data access unit, the endian processing circuit obtains source data from a memory, the data access unit obtains target data from the endian processing circuit, and the endian processing circuit is configured to execute the endian processing method according to any embodiment of the present application to perform endian processing on the source data to obtain the target data.
In a third aspect, an embodiment of the present application provides a chip, which includes: the data access unit is used for acquiring target data from the endian processing circuit, and the endian processing circuit is used for executing the endian processing method in any embodiment of the application to perform endian processing on the source data to obtain the target data.
In a fourth aspect, an embodiment of the present application provides an electronic terminal, which includes the chip described in any embodiment of the present application.
In the endian processing scheme provided in the embodiment of the present application, the endian processing circuit is applied to an endian processing circuit, the endian processing circuit is located outside a data access unit, the endian processing circuit acquires source data from a storage device, the data access unit acquires target data from the endian processing circuit, and the endian processing method includes:
determining an endian processing mode for processing the source data into the target data; determining the data access width when the data access unit acquires the target data; according to the data access width and the endian processing mode, the source data is subjected to endian processing to obtain the target data, namely, the endian processing is performed on an endian processing circuit outside the data access unit, so that the data access unit does not need to use extra clock cycles to execute the endian processing, and the consumption of the clock cycles of the data access unit is reduced.
Drawings
Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present application;
FIG. 2 is a schematic flow chart illustrating an end-sequence processing method according to an embodiment of the present disclosure;
FIG. 3 is a flowchart illustrating an exemplary endian process according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another application scenario according to an embodiment of the present application;
fig. 5 is a flowchart illustrating an endian processing method of the application scenario of fig. 4.
Detailed Description
It is not necessary for any particular embodiment of the invention to achieve all of the above advantages at the same time.
In order to make those skilled in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application should fall within the scope of the protection of the embodiments in the present application.
The following further describes a specific implementation of the embodiments of the present application with reference to the drawings of the embodiments of the present application.
FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present application; as shown in fig. 1, in this application scenario, the electronic terminal includes a chip and a memory, where the chip includes a data access unit and an endian processing circuit, where the endian processing circuit is located outside the data access unit, the endian processing circuit obtains source data from the memory and performs endian processing on the source data to obtain target data, and the data access unit obtains the target data from the endian processing circuit.
Optionally, in a specific application, the data Access Unit may be a CPU (Central Processing Unit), an MCU (micro control Unit), or a DMA (Direct Memory Access) controller.
Optionally, in a specific application, the memory is, for example, a FLASH device, such as a memory that is, for example, a Serial Peripheral Interface (spi) memory that supports a 4-wire operating mode, or a QSPI (Serial Peripheral Interface) memory that is also referred to as a 4-wire operating mode.
In this embodiment, the endianness mainly represents the byte order of the stored data. The end sequence can be called a zigzag node sequence, a tail sequence and a bit sequence. The endianness may include Big Endian (Big Endian) and Little Endian (Little Endian). In big endian, the high order bytes are placed at the low address of the memory and the low order bytes are placed at the high address of the memory. In little endian, the low order bytes are placed at the low address of the memory and the high order bytes are placed at the high address of the memory.
In a specific application, the endian processing circuit is, for example, a circuit generated by a hardware programming language (VHDL, Verilog, etc.), and may be specifically a System-on-a-Chip (SoC) Chip.
In a specific application, the source data is not particularly limited, and may be any data, such as pixel data or picture data or font data.
Optionally, in a specific application, the data access width is N times of 8bits, where N ≧ 1, such as 8bits (equivalent to the width of one byte, abbreviated as one byte), 16bits (i.e., the width of 2bytes, equivalent to the width of a half word, or also referred to as a half word), 32 bits (i.e., the width of 4 bytes, equivalent to the width of one word, or also referred to as a single word), and so on. It should be noted that, here, the data access width of a specific numerical value is only an example and is not limited only.
FIG. 2 is a schematic flow chart illustrating an end-sequence processing method according to an embodiment of the present disclosure; as shown in fig. 2, the endian processing method includes:
s201, determining an endian processing mode for processing the source data into the target data;
optionally, in a specific application, the step S201 may specifically include: and determining an endian processing mode for processing the source data into the target data according to a mode variable value acquired from an endian processing mode configuration register. Optionally, in a specific application, the number of the endian processing modes is multiple, and correspondingly, multiple endian processing mode identifiers are stored in the endian processing mode configuration register, and one endian processing mode identifier has one mode variable value, so that one mode variable value corresponds to one endian processing mode, and thus, mutually exclusive relationships are formed between the mode variable values corresponding to different endian processing modes, and switching of the endian processing modes can be quickly realized.
For example, if there are three end-sequence processing modes, which are Mode0, Mode1, and Mode2, respectively, if the acquired Mode variable value is 0, it is determined that the end-sequence processing Mode is Mode 0; and if the acquired Mode variable value is 1, determining that the endian processing Mode is Mode1, and if the Mode variable value is 2, determining that the endian processing Mode is Mode 2. Specifically, 3 endian processing Mode identifications xip _ Mode _ endian _ type _0, xip _ Mode _ endian _ type _1 and xip _ Mode _ endian _ type _2 are stored in the endian processing Mode configuration register, when the Mode variable value of xip _ Mode _ endian _ type _0 is 0, xip _ Mode _ endian _ type _0 is considered to be true, the corresponding endian processing Mode is Mode0, and conversely, when the Mode variable value of xip _ Mode _ endian _ type _0 is other values, xip _ Mode _ endian _ type _0 is considered to be false, and the corresponding endian processing Mode is not Mode 0; when the Mode variable value of xip _ Mode _ endian _ type _1 is 1, the corresponding end-sequence processing Mode is Mode1 if xip _ Mode _ endian _ type _1 is considered to be true, and conversely, when the Mode variable value of xip _ Mode _ endian _ type _1 is other values, the corresponding end-sequence processing Mode is not Mode1 if xip _ Mode _ endian _ type _1 is considered to be false; when the Mode variable value of xip _ Mode _ endian _ type _2 is 2, it is considered that xip _ Mode _ endian _ type _2 is true, and the corresponding endian processing Mode is Mode2, and conversely, when the Mode variable value of xip _ Mode _ endian _ type _2 is other values, it is considered that xip _ Mode _ endian _ type _2 is false, and the corresponding endian processing Mode is not Mode 2. It can be seen that, the relation of mutual exclusion is formed by the variable value of the pattern of xip _ Mode _ endian _ type _0 being 0, the variable value of the pattern of xip _ Mode _ endian _ type _1 being 1, and the variable value of the pattern of xip _ Mode _ endian _ type _2 being 2, so that the fast and convenient switching among the endian processing Mode0, the endian processing Mode1 and the endian processing Mode2 can be facilitated. Optionally, in a specific application, the endian processing mode configuration register is configured on the data access unit, so that the data access unit can quickly acquire a mode variable value from the endian processing mode configuration register and send the mode variable value to the endian processing circuit, so that the endian processing circuit determines, according to the mode variable value, an endian processing mode for processing the source data into the target data, which is equivalent to building a quick entry for data interaction between the data access unit and the endian processing circuit.
For example, when the data access unit is a CPU, the endian processing mode configuration register is configured on the CPU; when the data access unit is an MCU, the endian processing mode configuration register is configured on the MCU, so that a quick entry for data interaction between the CPU and the endian processing circuit is established.
Optionally, in a specific application, the determining an endian processing mode for processing the source data into the target data includes: according to the configuration data of the end sequence processing, the mode variable value corresponding to each end sequence processing mode is configured in the end sequence processing mode configuration register, so that the method is suitable for specific end sequence processing modes in different application scenes by changing the mode variable value in the end sequence processing mode configuration register, or the method can realize the quick switching of the end sequence processing modes according to different stages of data requirements of the data access unit in the same application scene.
For example, if the Mode variable value of the configuration xip _ Mode _ endian _ type _0 is 0, then the xip _ Mode _ endian _ type _0 is considered to be true, and the corresponding end-sequence processing Mode is Mode 0; when the Mode0 needs to be switched to the Mode1, the Mode variable value of the xip _ Mode _ endian _ type _0 is modified to be not 0, and the Mode variable value of the xip _ Mode _ endian _ type _1 is modified to be 1, so that the xip _ Mode _ endian _ type _1 is considered to be true, and the corresponding end-sequence processing Mode is the Mode1, so that the fast switching from the Mode0 to the Mode1 is realized.
S202, determining the data access width when the data access unit acquires the target data;
s203, according to the data access width and the endian processing mode, carrying out endian processing on the source data to obtain the target data with the target endian.
Optionally, in a specific application, the memory is a QSPI memory, and the endian processing circuit obtains the source data from the QSPI memory through an Advanced High-performance Bus (AHB).
Specifically, fig. 3 is a schematic flow chart of the endian processing according to the embodiment of the present application; as shown in fig. 3, step S203 may include:
s213, determining an endian processing logic according to the data access width and the endian processing mode;
optionally, in a specific application, the endian processing logic includes at least one of 4-byte endian processing logic, 2-byte endian processing logic, and single-byte endian processing logic, so as to perform endian processing on the source data respectively corresponding to the data access widths of 8bits, 16bits, and 32 bits to obtain a result that meets the requirement of the data access unit for obtaining the target data, for example, when the CPU is based on an ARM structure, the requirement can be effectively met for most application scenarios of the CPU, and only one configuration is needed to be applied to most application scenarios, thereby saving the design cost of endian processing.
And S223, performing end sequence processing on the source data according to the end sequence processing logic to obtain the target data.
Optionally, in a specific application, if the data access width when the data access unit acquires the target data is a single byte, the endian processing circuit acquires the data access width of the source data from the memory, so as to ensure that the bit width of the source data read from the memory by the endian processing circuit is a single byte each time, and the bit width of the target data read from the endian processing circuit by the data access unit is a single byte, that is, the bit width is equivalent to that the source data read by the endian processing circuit is the same as the bit width of the target data read by the data access unit, thereby avoiding waste of the data access width.
Further, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: and according to the single-byte endian processing logic, carrying out endian processing on the source data to obtain the target data, so that the endian of the target data is the same as the endian of the source data. For example, when performing endianness processing on the source data, the endianness of the source data is kept unchanged, so that the endianness of the target data is the same as the endianness of the source data, or the source data is output according to the source order. If the endian of the source data is big endian, the endian of the target data is also big endian; and if the endian of the source data is the little endian, the endian of the target data is also the little endian. Specifically, if the source data read from the memory at a certain time by the endian processing circuit is AA, the source data participating in one endian processing is AA (that is, the corresponding data access width is a single byte), and the target data obtained after the endian processing is also AA. And if the source data of the next end-sequence processing is BB, the target data obtained after the end-sequence processing is BB as well.
Optionally, in a specific application, if the data access width when the data access unit acquires the target data is 2bytes, the data access width when the endian processing circuit acquires the source data from the memory is 2bytes, so as to ensure that the bit width of the source data read from the memory by the endian processing circuit is 2bytes each time, and the bit width of the target data read from the endian processing circuit by the data access unit is 2bytes, that is, the bit width is equivalent to that the source data read by the endian processing circuit is the same as the bit width of the target data read by the data access unit, thereby avoiding waste of the data access width.
Further, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: according to the 2-byte endian processing logic, the source data is processed in an endian manner to obtain the target data, so that the endianness between 2bytes in the target data is the same as or opposite to the endianness between 2bytes in the source data. For example, when performing endianness processing on the source data, the endianness of the source data is kept unchanged, so that the endianness of the target data is the same as the endianness of the source data, or the source data is output according to the source order. If the endian of the source data is big endian, the endian of the target data is also big endian; and if the endian of the source data is the little endian, the endian of the target data is also the little endian. Specifically, if the source data read from the memory by the endian processing circuit is AABB, that is, the access width of the corresponding data is 2bytes, the source data participating in the endian processing is AABB, and the target data obtained after the endian processing is also AABB; if the source data processed by the next end sequence is CCDD, the target data obtained after the end sequence processing is also CCDD; it follows that the endianness of the source data and the target data is the same. For another example, when performing endian processing on the source data, the endian processing of the source data is performed in a reverse order (or also referred to as endian conversion) so that the endian of the target data is opposite to the endian of the source data, or the source data is output in a reverse order. If the endian of the source data is a big endian, the endian of the target data is a small endian; and if the endian of the source data is a small endian, the endian of the target data is a large endian. Specifically, if the source data read from the memory by the endian processing circuit at a certain time is AABB, the source data participating in the endian processing at a time is AABB, and the target data obtained after the endian processing is BBAA; and if the source data processed by the next endian processing is CCDD, the target data obtained after the endian processing is DDCC, so that the endianness of the source data and the target data is opposite.
Optionally, in a specific application, if the data access width when the data access unit acquires the target data is 4 bytes, the data access width when the endian processing circuit acquires the source data from the memory is 4 bytes, so as to ensure that the bit width of the source data read from the memory by the endian processing circuit is 4 bytes each time, and the bit width of the target data read from the endian processing circuit by the data access unit is 4 bytes, that is, the bit width is equivalent to that the source data read by the endian processing circuit is the same as the bit width of the target data read by the data access unit, thereby avoiding waste of the data access width.
Further, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: according to the 4-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 4 bytes in the target data is the same as or opposite to the endian between 4 bytes in the source data, or so that the endian between the first 2bytes in the target data is opposite to the endian between the first 2bytes in the source data, and the endian between the last 2bytes in the target data is opposite to the endian between the last 2bytes in the source data. For example, when performing endianness processing on the source data, the endianness of the source data is kept unchanged, so that the endianness of the target data is the same as the endianness of the source data, or the source data is output according to the source order. If the endian of the source data is big endian, the endian of the target data is also big endian; and if the endian of the source data is the little endian, the endian of the target data is also the little endian. Specifically, if the source data read from the memory by the endian processing circuit at a certain time is AABBCCDD (that is, the corresponding data access width is 4 bytes), the source data participating in the endian processing is AABBCCDD, and the target data obtained after the endian processing is also AABBCCDD; if the source data of the next endianness processing is EEFFGGHH, the target data obtained after the endianness processing is EEFFGGHH; it follows that the endianness of the source data and the target data is the same. Or, for another example, when performing endian processing on the source data, performing reverse-order processing on the endian of the source data so that the endian of the target data is opposite to the endian of the source data, or outputting the source data in a reverse order. If the endian of the source data is a big endian, the endian of the target data is a small endian; and if the endian of the source data is a small endian, the endian of the target data is a large endian. Specifically, if the source data read from the memory at a certain time by the endian processing circuit is AABBCCDD (that is, the corresponding data access width is 4 bytes), the source data participating in the endian processing is AABBCCDD, and the target data obtained after the endian processing is ddcbbaa; if the source data processed next time in the endian process is EEFFGGHH, the target data obtained after the endian process is HHGGFFEE, so that the endianness of the source data and the target data is opposite. Or, specifically, if the source data read from the memory by the endian processing circuit at a certain time is AABBCCDD (that is, the access width of the corresponding data is 4 bytes), the source data participating in the endian processing is AABBCCDD, and the target data obtained after the endian processing is BBAADDCC; if the source data processed next time in an endian manner is EEFFGGHH, the target data obtained after the endian processing is also ffeehgg, and thus it can be seen that the endianness between the first 2bytes in the target data is opposite to the endianness between the first 2bytes in the source data, and the endianness between the last 2bytes in the target data is opposite to the endianness between the last 2bytes in the source data.
FIG. 4 is a schematic diagram of another application scenario according to an embodiment of the present application; as shown in fig. 4, in this embodiment, taking the memory as a QSPI memory as an example, for this reason, the chip includes a QSPI controller in addition to a data access unit and an endian processing circuit, and therefore, the endian processing circuit is preferably disposed in the QSPI controller, thereby reducing the difficulty of circuit design. In addition, in fig. 4, the source data and the target data are transmitted through the AHB, the endian processing mode configuration register is set on the data access unit, and the endian processing configuration table is stored on the data access unit. As described above, the Mode0 (for example, referred to as the first Mode), the Mode1 (for example, referred to as the second Mode), and the Mode2 (for example, referred to as the third Mode) are used as examples of three modes of endian processing, and the modes of endian processing are described in the following table two.
FIG. 5 is a schematic flow chart illustrating an endian processing method of the present application for the application scenario of FIG. 4; as shown in fig. 5, it includes:
s501, configuring the mode variable value corresponding to each end sequence processing mode and end sequence processing logic corresponding to each end sequence processing mode in an end sequence processing mode configuration register according to end sequence processing configuration data;
in this embodiment, the manner of the source data in QSPI is shown in table one.
Watch 1
In table one, the offset address indicates an offset address, the Saved data indicates source data stored in each offset address, and the bit width of the data stored in each offset address is 8 bits.
In this embodiment, the endian processing configuration data may be embodied by an endian processing configuration table, as shown in table two.
Watch two
In table two, AHB Size indicates a data access width, HSIZE is a variable indicating the data access width, and if the variable is 8, the data access width is 8bits (i.e., a single byte), if the variable is 16 (i.e., 2 bytes), the data access width is 16bits, and if the variable is 32 (i.e., 4 bytes), the data access width is 32 bits. 0x00000000, 0x00000001, 0x00000002, 0x00000003 denote alignment addresses for achieving alignment of data bits, i.e., alignment of data bits of single byte data, data bits of 2byte data, data bits of 4 byte data. If the data access width is 8bits, the aligned addresses are 0x00000000, 0x00000001, 0x00000002, and 0x 00000003; if the data access width is 16bits, the aligned addresses are 0x00000000 and 0x 00000002; if the data access width is 32 bits, the aligned addresses are 0x00000000 and 0x 00000004.
Referring to table two above, if the data access width is one byte (i.e. HSIZE is 8), when performing endian processing on the source data, the endian processing logic corresponding to the endian processing modes Mode0, Mode1, and Mode2 are all one byte endian processing logic; if the data access width is 2bytes (i.e. HSIZE ═ 16), when performing endian processing on the source data, the endian processing logic corresponding to the endian processing modes Mode0, Mode1, and Mode2 is 2-byte endian processing logic; if the data access width is a single word (i.e., HSIZE ═ 32), when performing endian processing on the source data, the endian processing logic corresponding to the endian processing modes Mode0, Mode1, and Mode2 is 4-byte endian processing logic. Specifically, the details of the endian processing logic are described in the above embodiments.
S502, judging whether the memory is in a memory mapping mode;
in this embodiment, the data access unit, the endian processing circuit, and the QSPI memory are all connected through the AHB, and in order to implement data transmission, the memory may be in a memory mapping mode to implement mapping of a physical address space of the QSPI memory onto the AHB, so that the endian processing circuit may read source data from the QSPI memory.
If yes, go to step S503, otherwise, end. Here, in other embodiments, if it is determined that the storage is not in the memory mapping mode, the process may return to step S502 to perform the re-determination until the storage is in the memory mapping mode.
S503, determining an endian processing mode for processing the source data into the target data according to the mode variable value obtained from the endian processing mode configuration register;
in this embodiment, 2 bits are provided in the endian processing Mode configuration register to configure the Mode variable value, for example, if the Mode variable value is 0, it indicates that the endian processing Mode is Mode 0; if the Mode variable value is 1, it indicates that the endian processing Mode is Mode1, and if the Mode variable value is 2, it indicates that the endian processing Mode is Mode 2.
In the endian processing mode configuration register, there are stored 3 endian processing mode identifications xip _ mode _ endian _ type _0, xip _ mode _ endian _ type _1, xip _ mode _ endian _ type _2, as described above, each of the endian processing mode identifications has one of the mode variable values, so that one of the mode variable values corresponds to one of the endian processing modes. When the Mode variable values are 0, 1 and 2, respectively, xip _ Mode _ endian _ type _0, xip _ Mode _ endian _ type _1 and xip _ Mode _ endian _ type _2 are true, which means that the endian processing modes are Mode0, Mode1 and Mode2, respectively.
In other embodiments, Mode0 may be set as the default endian processing Mode. When there is no Mode variable value equal to 1 or 2, it indicates that the endian processing Mode is the default endian processing Mode0, and when there is a Mode variable value equal to 1 or 2, it indicates that the endian processing Mode is not the default endian processing Mode0, actually, the endian processing Mode1 or Mode 2.
S504, determining the data access width when the data access unit acquires the target data;
optionally, in a specific application, different data access width identifiers are configured for different data access widths, that is, the data access width identifiers are mutually exclusive, so that the data access width can be quickly determined according to the value of the data access width identifier. For example, if the data access width is 8bits, 16bits, or 32 bits, the configured data access width identifier is hsize _ byte, hsize _ half _ word, or hsize _ word, respectively, and if hsize _ byte is 1, the data access width is 8bits, that is, a single byte; if hsize _ half _ word is 1, it means that the data access width is 16bits, i.e., half word; if hsize _ word is 1, it means that the data access width is 32 bits, i.e., a single word.
S505, determining an endian processing logic according to the data access width and the endian processing mode;
in this embodiment, details of the endian processing logic are described in the above embodiments.
S506, performing end sequence processing on the source data according to the end sequence processing logic to obtain the target data;
in this embodiment, the detailed description of step S506 can be found in the description of the above embodiments. In the above embodiment, the mode variable value can be modified through the register instruction, so that flexible and convenient switching of the end sequence processing mode is realized, and the requirements of various application scenarios are met.
It should be noted here that the specific numerical values of the above-mentioned endian processing configuration data are merely examples and are not limited. Such as data access width, may also be 64 bits, 128 bits, etc. The number of the endian processing modes can exceed 3, so that the configuration of various possible endian processing modes and endian processing logics can be realized in the same endian configuration data table, flexible switching can be performed in various scenes, and the cost of endian processing design is reduced.
In addition, in the above embodiments, only one memory is taken as an example for description, but it is described here that there is no limitation on the number and type of the memories, that is, one data access unit may access a plurality of memories of the same or different types, such as QSPI memory, PSRAM (Pseudo static random access memory).
The following describes the application of the present invention to a significant reduction in clock consumption, taking as an example its application in a typical scenario.
For example, for the screen refreshing of the smart bracelet/watch, the picture used for the screen refreshing is stored in the QSPI memory, the source data is directly transmitted to the screen for display after being subjected to the end sequence processing by the end sequence processing circuit, which is equivalent to the transmission of P2P, so that the design scheme and the software architecture of the product can be more concise, the development difficulty and the development cost of a user are reduced, and in addition, the data calculation and screen refreshing processing capacity of the CPU can be more powerful. Assuming that the length width of the screen is 454 × 16bits, since 8bits is 1Byte, the data amount of 1 screen is 412232 Bytes.
If the operating frequency of the QSPI memory is 48Mhz, it is in 4-line operating mode (i.e. 4bits are transmitted per SCLK, i.e. it takes 2 clock cycles per byte (also referred to as 2 SCLK)), then the maximum theoretical limit speed is 48 × 4/8 — 24 MByte/Sec.
In addition, when the endian processing circuit reads source data from the QSPI memory, reading 1-byte data is referred to as 1beat data, which takes 2 SCLKs.
In addition, when reading source data, in addition to consuming the 2SCLK, if the endian processing circuit reads source data from the QSPI memory in a sio (single read Instruction) mode and performs endian processing, the whole clock consumption includes: the OVERHEAD clock consumption (also called indirect clock consumption) and the read Data consumption (also called Data Phase consumption) are recorded as OVERHEAD SLCK, the number of the OVERHEAD SLCK is 14 SCLKs, wherein, the time sequence is from front to back: 2 SCLKs (read command transfer consumption), 6 SCLKs (Address Phase consumption), and 6 SCLKs (latency Phase consumption).
(1) Based on the solution provided in this application, if HSIZE ═ 8, since 1Beat data is 1byte data, then read 4Beat data from QSPI memory, that is, 4 byte data, as mentioned above, since reading one byte data consumes 2SCLK, the total of 4 byte data is: 4 × 2SCLK ═ 8SCLK, the clock consumption of Data Phase is 8SCLK, since the whole process will consume: the sum of the OVERHEAD clock consumption (14SCLK) and the Data Phase consumption (4 x 2SCLK), totaling 22SCLK, then:
the access efficiency was (4 × 2)/(14+4 × 2) ═ 36.4%;
the theoretical transmission speed in the case of HSIZE-8 is 24 Mbyte/Sec-36.4% — 8.73 MB/Sec;
the theoretical consumption time for transmitting a screen of data is (412232/(1024) 1000/8.73 — 45 ms.
(2) Based on the scheme provided by the present application, if HSIZE ═ 32, since 1Beat data is 4 bytes of data, then read 4Beat data from QSPI memory, that is, 16 bytes, as described above, since reading one Byte of data consumes 2SCLK, 16 bytes of data, in total: similar to the above calculation method of HSIZE ═ 8, the whole process consumes 16 × 2SCLK ═ 32SCLK, the clock period consumed by Data Phase is 8SCLK, and the overlap SLCK is 14 SCLK: 14SCLK +16 × 2SCLK ═ 46SCLK, then:
the access efficiency was (16 × 2)/(14+2 × 16) ═ 69.6%;
the theoretical transmission speed in the case of HSIZE 32 is 24Mbyte/Sec 69.6% ═ 16.7 MB/Sec;
the theoretical elapsed time for transmitting a screen of data is: (412232/(1024 × 1024)). 1000/16.7 ═ 23.5 ms;
it can be seen that the access efficiency when HSIZE is 32 is higher than that when HSIZE is 8, and the theoretical consumption time for transmitting one screen data when HSIZE is 32 is shorter than that when HSIZE is 8. That is, the wider the data access width, the higher the access efficiency, and the shorter the theoretical consumption time for transmitting one screen data. Here, the case of HSIZE 16 is omitted.
If HSIZE is 32, based on the conventional endian processing method (i.e. software layer), the screen is swiped to the screen after the endian processing is performed, and compared with the case implemented when HSIZE is 32 in the present application, the conventional endian processing method consumes more time to complete the data access theoretically, and is analyzed in detail as follows.
Since the source data read from the memory is first buffered in the RAM in the conventional scheme, and is limited by the size of the RAM, the data stored in the volume memory needs to be divided into N blocks for storage.
Reading a first block of data into an RAM, performing end-sequence processing on the first block of data to obtain corresponding target data, transmitting the target data to a screen buffer area, and displaying the target data on a screen;
and by parity of reasoning, reading in the second block data, … and the Nth block, sequentially carrying out end-to-end processing to respectively obtain corresponding target data, transmitting the target data to a screen buffer area, and displaying on a screen until all the data blocks are brushed into the screen for displaying.
The total number of 16 bytes is calculated when reading the data if reading the 4Beat data. The above-mentioned process of accomplishing the screen brushing can be decomposed into: reading to a RAM, performing endian processing, and writing to a screen cache, then:
read-out to RAM consumes clock cycles: 14+4 × 2 ═ 46SCLK (see above examples for detailed calculations);
clock cycles consumed by the software layer for end-sequence processing: about 2 to 3 SCLK;
clock cycles consumed writing to screen buffer: 4 × 2 ═ 32 SCLK;
the average time consumed for completing the 16 bytes processing is about 80SCLK, and the full screen processing consumes about (412232/16) × 80 ═ 2061160 SCLK. (system scheduling, loop processing, and call out and in times at the software layer are ignored here).
The minimum theoretical elapsed time for transmitting a screen of data is:
2061160/48000000 is 42.9 ms. Wherein 48000000 is the QSPI memory operating frequency of 48 Mhz.
It can be seen that this 42.9ms is much greater than the 23.5ms mentioned above. In other words, after the scheme of this application is used, the frame rate of swiping the screen of wrist-watch/bracelet has obtained very big improvement, makes the product that originally slides and probably blocks and pause no longer block and pause, and the sliding effect becomes more smooth.
Therefore, in the above example, there are multiple endian processing modes, and different endian processing logics can be provided in each endian processing mode, and corresponding endian processing is completed on the endian processing circuit outside the data access unit, so that the data access unit is not required to waste extra clock cycles for data endian processing, and the clock consumption of the data access unit is saved. In addition, because the endian processing device is independent of the data access unit to carry out endian processing, software codes for carrying out endian processing do not need to be arranged on the data access unit, on one hand, the storage space of the data access unit is saved, on the other hand, the software design difficulty of the data access unit is also reduced, and the BUG introduced into the data access unit is reduced. Furthermore, the source data can be directly transmitted to the endian processing circuit without configuring a RAM for buffering the source data, thereby improving the data access speed and the access efficiency.
Thus, particular embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (16)
1. An endian processing method applied to an endian processing circuit, the endian processing circuit being external to a data access unit, the endian processing circuit obtaining source data from a memory, the data access unit obtaining target data from the endian processing circuit, the endian processing method comprising:
determining an endian processing mode for processing the source data into the target data;
determining the data access width when the data access unit acquires the target data;
and performing endian processing on the source data according to the data access width and the endian processing mode to obtain the target data.
2. The endian processing method according to claim 1, wherein the endian processing the source data to obtain the target data according to the data access width and the endian processing mode includes:
determining endian processing logic according to the data access width and the endian processing mode;
and performing end sequence processing on the source data according to the end sequence processing logic to obtain the target data.
3. The endian processing method of claim 2 wherein the endian processing logic is at least one of 4-byte endian processing logic, 2-byte endian processing logic, and single-byte endian processing logic.
4. The endian processing method according to claim 3, wherein if the data access width when the data access unit acquires the target data is a single byte, the endian processing circuit acquires the data access width of the source data from the memory as a single byte;
and, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: and according to the single-byte endian processing logic, carrying out endian processing on the source data to obtain the target data, so that the endian of the target data is the same as the endian of the source data.
5. The endian processing method according to claim 3, wherein if the data access width when the data access unit acquires the target data is 2bytes, the endian processing circuit acquires the data access width of the source data from the memory as 2 bytes;
and, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: according to the 2-byte endian processing logic, the source data is processed in an endian manner to obtain the target data, so that the endianness between 2bytes in the target data is the same as or opposite to the endianness between 2bytes in the source data.
6. The endian processing method according to claim 3, wherein if the data access width when the data access unit acquires the target data is 4 bytes, the endian processing circuit acquires the data access width of the source data from the memory as 4 bytes;
and, the performing, according to the endian processing logic, endian processing on the source data to obtain the target data includes: according to the 4-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 4 bytes in the target data is the same as or opposite to the endian between 4 bytes in the source data, or so that the endian between the first 2bytes in the target data is opposite to the endian between the first 2bytes in the source data, and the endian between the last 2bytes in the target data is opposite to the endian between the last 2bytes in the source data.
7. The endian processing method of any of claims 1-6, wherein the determining the endian processing mode to process the source data into the target data includes: and determining an endian processing mode for processing the source data into the target data according to a mode variable value acquired from an endian processing mode configuration register.
8. The endian processing method according to claim 7, characterised in that the number of endian processing modes is multiple, and correspondingly, multiple endian processing mode identifications are stored in the endian processing mode configuration register, one of the endian processing mode identifications having one of the mode variable values such that one of the mode variable values corresponds to one of the endian processing modes.
9. The endian processing method of claim 8 wherein the determining an endian processing mode to process the source data into the target data is preceded by: and configuring the mode variable value corresponding to each endian processing mode in the endian processing mode configuration register according to the endian processing configuration data.
10. An endian processing method according to any of the claims 7-9, characterised in that the endian processing mode configuration register is arranged on the data access unit.
11. The endian processing method of any of claims 1-10 where the memory is a memory of a serial peripheral interface that supports a 4-wire mode of operation, the source data being transmitted to the endian processing circuitry through the serial peripheral interface.
12. The endian processing method of any of claims 1-11, wherein the determining the endian processing mode to process the source data to the target data is preceded by: and judging whether the memory is in a memory mapping mode, if so, determining to process the source data into an end sequence processing mode of the target data.
13. An endian processing method according to any of claims 1-12 characterised in that the data access unit comprises at least one of a central processing unit, a micro control unit, a direct memory access controller.
14. An endian processing circuit, characterized in that the endian processing circuit is located outside a data access unit, the endian processing circuit obtains source data from a memory, the data access unit obtains target data from the endian processing circuit, the endian processing circuit is configured to execute the endian processing method according to any of claims 1-13 to endian the source data to obtain the target data.
15. A chip, comprising: an endian processing circuit and a data access unit, the endian processing circuit being external to the data access unit, the endian processing circuit obtaining source data from a memory, the data access unit obtaining target data from the endian processing circuit, the endian processing circuit being configured to perform the endian processing method of any of claims 1-13 to endian the source data to obtain the target data.
16. An electronic terminal, characterized in that it comprises a chip according to claim 15.
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