JPH07129398A - Microprocessor - Google Patents

Abstract

PURPOSE:To provide a microprocessor immediate inputting means capable of attaining compact constitution reducing the number of codes without changing bus width. CONSTITUTION:In a microprocessor(MPU) attaining an MPU immediate inputting means, an instruction buffer 2 is connected to an instruction storing means 1 and a selector 9 is connected to the most significant bit(MSB) of the buffer 2. When immediate data having constitution whose bits are less than the bus width only by one bit are judged by a selector based upon one remaining bit, data in the buffer 2 are directly transferred to a control mechanism 8 in a data bus 5. In this constitution, a memory is reduced and processing time is also shortened. When immediate data for the bus width are required, an instruction word for recovering the bus width is added, so that the added contents can be processed by the number of codes and processing time similar to a conventional case.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor used for electronic control or the like, and more particularly to a microprocessor having an immediate value introduction mechanism for introducing a constant from an instruction storage unit into an arithmetic unit as an immediate value.

[0002]

2. Description of the Related Art Conventionally, in a microprocessor, the handling of immediate data having the same width as the bus width for operation is
As shown in FIG. 4, it is generally performed by an instruction set having an instruction word length twice that of the operation bus (or an instruction set having an instruction word length three times when two immediate data are required).
The first half of the bus width has an instruction code + the immediate data of the bus width, and the word length is twice or three times the required immediate data. For example, if the instruction word length is double, 8 bits = 1
In the bus width of bytes, 2 bytes = 1 word is 1 instruction set. Therefore, the code amount increases in a program that uses a large amount of immediate data of the bus width. Since the immediate data is handled by this instruction word set, even the immediate data having a few digits smaller than the bus width requires a double code amount. In addition,
Since there is an instruction code in which the first half of one code is the instruction word and the latter half is the immediate value area, there is no problem for the immediate value of a digit sufficiently smaller than the bus width. Therefore, by increasing the bus width, not only immediate data but also instruction words are abundant, and as a natural development development, a multi-bit bus microprocessor can be designed, and the operation bus width is from 8 bits to 16 bits. , 32 bits, 64 bits, and the functions are enhanced. Of course, this development requires complicated peripheral circuits and designs and cannot be easily implemented.

There is a proposal to add an additional word length of 1 bit or 2 bits to the bus width, as proposed in Japanese Patent Application Laid-Open No. 56-85159, even if the function is not improved so much by hardware. is there. For example, in the case of an 8-bit bus configuration, the configuration is such that a bus line of the 9th or 10th bit is added, a value indicating immediate data is set in the added bit, and if it is an immediate value, that data is immediately sent to the accumulator. It is what is transferred. Therefore, it is not necessary to set the instruction code for transferring the immediate data. Therefore, if attention is paid to the immediate data having the same bus width, it is effective in suppressing the code amount also in this case.

[0004]

However, in the case of the above-mentioned document, an additional hardware structure for the additional word length is required, and the operation bus and the additional bus must be separated. Therefore, there is a problem that the circuit scale and the chip area increase, which is not preferable in design. By the way, in the conventional case, in any bus width, the handling of immediate data equal to the bus width must be done by an instruction set having an instruction word length that is twice as long as the bus, and a code amount that is twice the required immediate length. Alternatively, there is a problem that two bus cycles, that is, the amount of program code becomes large and the processing time is doubled. In particular, since the amount of memory that can be used in the one-chip microcomputer is not large, an increase in the amount of code causes a problem that the processing function and the processing time decrease. Further, since the instruction word length may be larger than the bus width and the instruction may extend over two bus cycles, whether or not the instruction includes the introduction of an immediate value is interpreted in the cycle of the previous instruction, and based on that, It requires a sequence of introducing immediate data after the instruction, which has a drawback of complicating the mechanism. It is said that the immediate data used in an actual program generally occupies 20 to 30% of the code amount, but it can be said that the immediate value of the bus width is actually required less frequently. Therefore, it is difficult to say that it is efficient to set the immediate data of the bus width and add the instruction code for the immediate data of less than the bus width. Therefore, an object of the present invention is to provide a microprocessor immediate value introducing means which realizes a compact and small code amount configuration without changing the bus width.

[0005]

In order to solve the above-mentioned problems, the structure of the present invention uses immediate data having a bus width or less,
The program code of the instruction word consisting of the immediate code and the instruction code stored in advance in the instruction storage unit is sequentially called for each code having the bus width, the instruction code is analyzed by the instruction decoder, and the instruction is executed to execute the immediate value. In a microprocessor having a mechanism for processing immediate data of a code by a data path including an arithmetic unit or the like, the longest immediate data is set to numerical data which is 1 bit smaller than a bus width, and the instruction storage unit is set by the 1-bit value. A selector that determines whether the data from is an immediate value or an instruction, and if it is an immediate code, a mechanism that immediately transfers the immediate code into the data path without sending it to the instruction decoder,
According to the purpose of the immediate data, the program code has an arithmetic process for expanding the immediate data to the same width as the bus width.

Further, in the configuration of the related invention, the 1 bit is
The MSB (most significant bit) of the instruction buffer connected to the instruction storage unit, and the selector activates the control mechanism of the data path when the value of the MSB is 0, and sets the code of the instruction buffer. The control mechanism receives it, and activates the instruction decoder when the value of the MSB is 1.
It is a circuit that causes the instruction decoder to receive the code.

A third configuration related to the above invention is that the arithmetic processing adds an instruction code for restoring the bus width after transferring the immediate code, and the instruction code is
When the immediate data is numeric data having a digit of the bus width, it is a bit set instruction for setting 1 in the MSB.
Alternatively, when the immediate data is address data for addressing that does not allow odd address arrangement, the LSB (least significant bit) is 0, a left shift instruction, or the immediate data is a signed bus width data. In the case of a negative value, it means that it is a one-code instruction that adds 1 as a bit inversion instruction.

[0008]

By introducing the immediate data which is 1 bit smaller than the bus width, it is determined by the remaining 1 bit (MSB etc.) that the data is an immediate code. The determination as an immediate code is made by a selector circuit connected to the instruction buffer. In the case of an immediate code, the data path side of the circuit that operates the data is selected and transferred to its control mechanism. Then, if necessary, in order to obtain immediate data of the bus width, the remaining 1 bit of the immediate code is separately set to the bus width by an additional instruction code and then used for the operation.

[0009]

Of the immediate data frequently used in the program, the frequency of the immediate data of the bus width is low. Therefore, the code amount can be reduced by the configuration of the present invention, and the memory utilization efficiency is improved. The processing time can be shortened. Further, since it is not necessary to change the bus width, the mechanism already provided for the arithmetic operation can be used, so that the mechanism can be simplified, a compact microprocessor can be designed, and the cost can be suppressed.

[0010]

EXAMPLES The present invention will be described below based on specific examples. FIG. 1 shows an embodiment of a microprocessor (hereinafter referred to as MPU) having an immediate value introduction mechanism of the present invention.
The U100 is connected to peripheral devices (not shown) and constitutes a microcomputer system. An instruction buffer 2 is connected to an instruction storage unit 1 in which a program code is configured by an instruction word set of an instruction code and an immediate value code, and the instruction buffer 2 is connected to the MSB (upper bit) of the instruction buffer 2. The selector 9 is connected. The instruction buffer 2 is connected to the instruction decoder 3 and the data path 5. The instruction decoded by the instruction decoder 3 is connected to the data path 5 to transmit the instruction.

In the data path 5, the data from the instruction buffer 2 is connected to the input register 4 through the control mechanism 8. The input data is calculated and processed by the calculator 6 and the accumulator 7.

The MPU 100 reads out the program code and sequentially executes it when the energization starts. The read instruction word is temporarily held in the instruction buffer 2. The MSB (upper 1 bit) of the instruction buffer 2 is a bit that distinguishes whether the data from the instruction storage unit is an instruction code or an immediate code. As shown in an example of FIG. 2, the MSB bit has a bus width of 16 bits. When 15 is "0", it is an instruction to introduce immediate data of the bus width, and when "1", it is an instruction other than the instruction to introduce immediate data. Therefore, when the selector determines that the instruction word is other than the immediate value introduction instruction, the instruction word is transferred to the instruction decoder, the instruction is analyzed, and the execution instruction is given to the data path 5. When the selector determines that the data is immediate data, the data in the instruction buffer 2 is directly transferred to the control mechanism 8 in the data path 5 and reaches the arithmetic unit 6 from the input register 4 to expand the bus width and the like as necessary. ,
Target arithmetic processing is performed.

The immediate data transferred to the data path 5 is
It is set to the bus width as needed, but in many cases it is not necessary to set it to the bus width. For example, 16-bit bus width,
With the MSB as the judgment bit, the numerical value of the constant "146Eh" (h indicates the hexadecimal system. In the binary system, 0001 0100 0110 1110) has the MSB of 0, so the judgment bit is regarded as a data bit and the data is used. Does not cause a problem. Therefore, the processing for correcting the bus width is not required, and only half the code is required as in the conventional case (in the case of FIG. 3 (a)).

Immediate data whose MSB is 1 such as "946Eh" in the case of 16 bits has a constant "146Eh" when viewed from the bus width when held in the instruction buffer 2. I will keep it. Therefore, this is set to the target constant by setting the MSB to 1 by the bit set instruction. In other words, for the microprocessor, since it is programmed in advance, it is known which data is the immediate data, and therefore a command word for processing to make it the target immediate data is added (in the case of FIG. 3 (b)). ).

When the immediate data is an address of an instruction word, in the case of a 16-bit example, since the storage address of a 16-bit instruction word is usually addressed byte by byte, the LSB of the immediate data is "0". Become. Therefore, as the immediate data, the upper 15 bits of the address are set in the immediate data area, and the target address value can be obtained by one left shift command after the transfer and can be set in the same processing time as the conventional one (see FIG. In case of 3 (c)).

Further, when the immediate data is signed data, the MSB is used as a sign bit and the remaining 15 bits are used as numerical data, and the normal MSB is often set to a negative value when it is "1". Then, with the conventional bit configuration,
Since it is determined to be an instruction word, the immediate value data that is inverted as a positive number is prepared here, and the bit width inversion instruction (NEG instruction) is used later to make the data with the bus width as a sign (FIG. 3).
(d)).

As described above, when it is desired to use the immediate data of the bus width, a processing process for bit recovery is required. However, only one additional instruction code can be used, and the code amount and processing time are the same as those in the past.
That is, the data of the full bus width used in the program is infrequent, and nevertheless, the data of the immediate bus width must be used even for the data of the bus width or less. In the configuration, the processing of immediate data is
Both memory and processing time could be shortened.

Suppose that the appearance frequency of the immediate data is Pi, the frequency at which the immediate data whose MSB is 0 is introduced is Pz, the instruction code length of the immediate data introduction according to the prior art is Lo, and the instruction in the immediate data of the present invention is When the code length is Li and the instruction code length used for expanding the bus width is Le, the reduction amount of the code amount is expressed by the equation (1).

[Equation 1] Pi * [1-Pz * Li / Lo- (1-Pz) * (Li + Le) / Lo]. Here, as a general example, Pi = 0.2, Pz =
When calculated as 0.8, Lo = 4 (byte), Li = Le = 2 (byte), the code amount is reduced by 8%.

That is, according to the present invention, the immediate bit data which is not frequently used and has a full bus width is not used, and the remaining 1 bit is used as a judgment bit of an immediate code or an instruction code without using the immediate bit data. The process for the immediate code up to 15 bits which is not necessary is only one code of the immediate code, so that the program can be short and the processing time can be shortened. When immediate data of the bus width is required, an instruction word for recovering the bus width is added, so that this amount can be dealt with with the same code amount and processing time as the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an immediate value introduction mechanism of the present invention.

FIG. 2 is an explanatory diagram showing a configuration example of an instruction word and an immediate value according to the present invention.

FIG. 3 is an explanatory diagram of expanding the bus width of immediate data after immediate value determination.

FIG. 4 is an explanatory diagram showing a configuration example of a conventional command word and an immediate value.

[Explanation of symbols]

 1 instruction storage unit 2 instruction buffer 3 instruction decoder 4 input register 5 data path (entire frame including 6, 7, 8) 6 arithmetic unit 7 accumulator 8 control mechanism 9 selector 10 data bus

Claims (3)

[Claims] 1. Using immediate data having a width less than or equal to a bus width, the program code of an instruction word consisting of an immediate code and an instruction code stored in advance in an instruction storage unit is sequentially called for each code having the bus width. In a microprocessor having a mechanism for analyzing a code with an instruction decoder to execute an instruction and processing the immediate data of the immediate code with a data path having an arithmetic unit etc., the longest immediate data is 1 bit smaller than the bus width. Numerical data, a selector that determines whether the data from the instruction storage unit is an immediate value or an instruction based on the 1-bit value, and, if it is an immediate code, without sending the immediate code to the instruction decoder It has a mechanism for immediately transferring it into the data path, and makes the immediate data the same width as the bus width depending on the purpose of the immediate data. Microprocessor, characterized in that an arithmetic processing for Zhang in the program code. 2. The 1 bit is the MSB (most significant bit) of an instruction buffer connected to the instruction storage unit, and the selector operates the data path control mechanism when the value of the MSB is 0. 7. A circuit for activating the instruction buffer to cause the control mechanism to receive the code, activating the instruction decoder when the value of the MSB is 1, and causing the instruction decoder to receive the code. 1. The microprocessor according to 1. 3. The arithmetic processing is to add an instruction code for recovering the bus width after transferring the immediate code, wherein the instruction code is a case where the immediate data is numerical data having a digit of the bus width. , A bit set instruction that sets the MSB to 1,
Alternatively, when the immediate data is address data for addressing that does not allow odd address arrangement, the LSB (least significant bit) is 0, a left shift instruction, or the immediate data is a negative value as signed bus width data. In the case of, the microprocessor according to claim 2, wherein the microprocessor is a one-code instruction which adds 1 by performing a bit inversion instruction.