CN101504566A - Method for reducing CPU power consumption and CPU - Google Patents
Method for reducing CPU power consumption and CPU Download PDFInfo
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- CN101504566A CN101504566A CNA2009100768123A CN200910076812A CN101504566A CN 101504566 A CN101504566 A CN 101504566A CN A2009100768123 A CNA2009100768123 A CN A2009100768123A CN 200910076812 A CN200910076812 A CN 200910076812A CN 101504566 A CN101504566 A CN 101504566A
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Abstract
The invention discloses a CPU, which comprises a data storage array, an instruction memory, a data storage manager, an instruction storage manager, a controller and a calculator, and also comprises a clock control module. The data storage array comprises a plurality of array blocks; the data storage manager is used for managing access requests pointing to the data storage array; the instruction storage manager is used for managing access requests pointing to the instruction memory; the controller is used for controlling and coordinating the operation of each functional component; the calculator is used for finishing various arithmetic and logical operations; and the clock control module positioned in the data storage manager is used for judging whether an access request aiming at the array blocks exists in a next clock period aiming at each array block in the data storage array, if so, outputting a clock signal to the array blocks in the next clock period, otherwise, prohibiting the clock signal from being output to the array block in the next clock period. Through the switching of the clock signal, the power consumption waste of the memories in a non-access state is avoided so as to reduce the power consumption of the whole CPU apparatus.
Description
Technical field
The present invention relates to the embedded system technology field, particularly relate to a kind of method of the CPU of reduction power consumption, and a kind of CPU of low-power consumption.
Background technology
CPU uses very extensive, and for example, CPU is applied among the various SOC (SystemOn Chip, SOC (system on a chip)) as important devices.
In chip design and using, power consumption is the problem that must consider, and CPU is as important devices, and how reducing its power consumption also is that prior art is thirsted for an improved direction always.For example, publication number is the method that the Chinese patent of CN101162405 discloses a kind of dynamic reduction CPU power consumption.This method can dynamically be adjusted the instruction operation speed of CPU according to the CPU occupation rate.In the CPU operational process, if being lower than the lower limit of setting, the occupation rate of CPU just the instruction operation speed of CPU is reduced, if being higher than the higher limit of setting, the occupation rate of CPU just the instruction operation speed of CPU is improved, wherein the adjustment of the instruction operation speed of CPU is mainly by switch data Cache interface and instruction high speed storage interface, and changes that propagation delay time realizes.
Above-mentioned improvement project is carried out at CPU integral body, the improvement angle that so whether also has other? we do further segmentation with the CPU device, it may comprise control section, arithmetic section and storage area, so whether can improve at certain or a plurality of parts of CPU device, perhaps the operational process to certain or a plurality of parts improves, power consumption with further reduction CPU? because in practical design with in using, those skilled in the art are low more good more for the pursuit of power consumption, and any method that can reduce power consumption all needs.
In a word, need the urgent technical matters that solves of those skilled in the art to be exactly at present: the power consumption that how can further reduce the CPU device.
Summary of the invention
Technical matters to be solved by this invention provides a kind of CPU device that can further reduce the solution of CPU device power consumption and use this solution, reducing the power consumption that storage area is in operation in the CPU device, thereby reduce the power consumption of whole C PU device.
In order to solve the problems of the technologies described above, the embodiment of the invention discloses a kind of CPU, comprising: data storage array, comprise a plurality of array blocks, be used to store data; Command memory is used for storage instruction; Data storage manager is used to manage the request of access of pointing to described data storage array; Instruction storage manager is used to manage the request of access of pointing to described command memory; Controller is used for control and coordinates each functional part operation; Arithmetical unit is used to finish various arithmetic sum logical operations;
Also comprise: be arranged in the clock control module of data storage manager, be used for each array block, judge in next clock period whether the request of access at this array block is arranged at described data storage array; If have, then at next clock period clock signal to this array block, otherwise, forbid that in the next clock period clock signal exports this array block to.
Preferably, described data storage array is tight coupling physical store module TCM, and it comprises the sector block more than 4 or 4, and each sector block comprises the array block bank more than 4 or 4.
Preferably, when described clock control module control clock signal exported an array piece to, the data enable signal that clock control module also is used to control at this array block was an effective status; When described clock control module forbade that clock signal exports an array piece to, the data enable signal that clock control module also is used to control at this array block was a disarmed state.
Preferably, the request of access of the described data storage array of described sensing is that the CPU external unit is sent to data storage manager by data bus.
Preferably, described CPU can also comprise that loading Load/ stores the Store parts; The request of access of the described data storage array of described sensing is that cpu controller sends to data storage manager by loading Load/ storage Store parts.
According to another embodiment of the present invention, a kind of method of the CPU of reduction power consumption is also disclosed, this CPU comprises data storage array, may further comprise the steps: receive the request of access of pointing to described data storage array; At each array block in the described data storage array, judge in next clock period whether the request of access at this array block is arranged; If have, then at next clock period clock signal to this array block, otherwise, forbid that in the next clock period clock signal exports this array block to.
Preferably, when control clock signal exported an array piece to, said method can also comprise: control is effective status at the data enable signal of this array block; When forbidding that clock signal exports an array piece to, said method can also comprise: control is disarmed state at the data enable signal of this array block.
Preferably, the request of access of the described data storage array of described sensing is that the CPU external unit is sent to data storage manager by data bus.
Preferably, the request of access of the described data storage array of described sensing is that cpu controller sends to data storage manager by loading Load/ storage Store parts.
Preferably, described data storage array is tight coupling physical store module TCM, and it comprises the sector block more than 4 or 4, and each sector block comprises the array block bank more than 4 or 4.
Compared with prior art, the present invention has the following advantages:
The inventor of this patent has selected data storage part to improve from whole C PU device, because that the power consumption of memory unit accounts for the ratio of whole C PU device power consumption is also higher, so the present invention can reduce the CPU device power consumption preferably.
Concrete, because existing data storage device has generally all adopted array memory structures, a data storer (for example may comprise a plurality of memory banks, array block bank), when reading or during write data, clock signal is carried on the whole data storage device, but in this data storage device, may only there be several memory banks of minority to be read and write, and the clock signal of all memory banks in this data storage device and data enable signal all are effective, promptly Ci Shi each memory bank is all at consumed energy, even not to the visit of this memory bank.That is to say that at this moment, other memory banks in this data storage device (non-access object) just are in the state of power wastage.The present invention has avoided this part power wastage by the switch of clock signal, thereby has reduced the power consumption of whole C PU device.
Description of drawings
Fig. 1 is the modular construction synoptic diagram of a kind of CPU device of the present invention embodiment;
Fig. 2 is the inner structure synoptic diagram of a kind of data storage array of the present invention;
Fig. 3 is the modular construction synoptic diagram of the another kind of CPU device of the present invention embodiment;
Fig. 4 is the flow chart of steps of the method embodiment of a kind of CPU of reduction power consumption of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
One of core idea of the embodiment of the invention is: at data storage part, in cpu chip, increase controller clock signal, when identifying that data storage device is all or part of to be in idle condition, stop to provide clock signal at the array block that does not have requirements for access, because at COMS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor (CMOS)) in the circuit, power consumption is directly proportional with clock; Stop to provide clock signal so carve at one's leisure, just can remove the energy consumption of idle array block this moment, to reach the purpose that reduces power consumption.
With reference to Fig. 1, show the modular construction of a kind of CPU device of the present invention embodiment, specifically can comprise:
Also comprise:
Be arranged in the clock control module 107 of data storage manager, be used for each array block, judge in next clock period whether the request of access at this array block is arranged at described data storage array; If have, then at next clock period clock signal to this array block, otherwise, forbid that in the next clock period clock signal exports this array block to.Simply situation is exactly, and at each array block, all has line to introduce clock signal, and then clock control module 107 these lines of control are closed, and the input of interrupt clock signal can reach the effect that reduces power consumption.Concrete, clock signal can be produced by special clock generator.
What embodiment shown in Figure 1 adopted is Harvard architecture, with data and instruction separate storage and calling, promptly CPU comprises data channel (data storage array 101 and data storage manager 103) and instruction path (command memory 102 and instruction storage manager 104).
Important improvement part of the present invention just is to have increased clock control module 107 in data storage manager 103.Data storage manager 103 is used to receive and manage the request of access of pointing to described data storage array.Concrete, data storage manager receives request of access, at first judges according to these requests it points to which array block in the cpu data storage array, if same of a plurality of request of access competitions are arranged, then arbitrates, and finds out the highest request of access of priority; The highest visit of processing priority afterwards conducts interviews (comprising read) to this array block.
CPU device shown in Figure 1 can be applied in the various embedded system developments.For example, it can be applied in the ARM embedded system, generally can adopt the CPU of RISC (compacting instruction set processor) structure in the ARM architecture.Certainly, the present invention is not limited to risc architecture, and CISC (complicated order set processor) is feasible.
In the ARM embedded system, data storage manager (MMU, Memory ManagementUnit) can be finished the mapping (because having adopted the page virtual memory management in ARM) to amount of physical memory of the control of memory access authority and virtual memory space.Can receive all request of access (sensing array block) just because of data storage manager at storage array, and have abilities such as control of authority, arbitration management, so based on these information, in data storage manager, increase a functional module, just can judge accurately in next clock period whether request of access at certain array block is arranged, thereby realize clock signal control function at each array block.
With reference to Fig. 2, show a kind of cut-away view of frequently-used data storage array, it comprises 4 sector block0, blockl, block2, block3, each sector block comprises 4 array block bank0, bankl, bank2, bank3.In read and write access at data storage array, at a time, may be only at one or more array block in 16 array blocks; The present invention turn-offs the clock signal that does not have the array block of request of access in this clock period, to reduce power consumption.Above-mentioned structure shown in Figure 2 only is an array structure relatively more commonly used now, in fact, adopt more sector block, and each sector is adopted more, and the array block bank of usefulness is feasible.
Preferably, when described clock control module control clock signal exported an array piece to, the data enable signal that clock control module also is used to control at this array block was an effective status; Promptly when request of access is arranged, guarantee that clock signal and the data enable signal at this array block all is effective.
When described clock control module forbade that clock signal exports an array piece to, the data enable signal that clock control module also is used to control at this array block was a disarmed state; Promptly when not having request of access, guarantee that clock signal and the data enable signal at this array block all is invalid.
With reference to Fig. 3, show another CPU embodiment, it adopts present stage risc architecture realization relatively more commonly used.
The difference of RISC and CISC (complicated order set processor) is: RISC needn't be provided with microprogram control memory as CISC, can finish instruction by shirtsleeve operation (for example, only getting final product by Load and Store operational access) and carry out.General, the memory address of visiting in every instruction can not surpass 1, and the operation of access memory can not mix with arithmetical operation, and most of instruction can be finished in a clock period; And, can realize the parallel work-flow of instructing by adopting the instruction pipelining operation.
It all is feasible that the present invention adopts RISC or CISC structure because the present invention improved be the internal data store parts that they all have.General, the internal data store parts of CPU can comprise Cache (cache memory) and TCM (tight coupling physical store module), owing to The present invention be directed to the improvement that memory unit with array memory structures carries out, so the present invention is when concrete the application, the internal data store parts need to adopt (perhaps comprising at least) tight coupling physical store module TCM.
In fact, TCM is the RAM (Random Access Memory random memory) of a fixed size, closely is coupled to CPU core, and the performance suitable with cache is provided.Its advantage than cache is that program code can accurately control what function or code is placed on there (in the RAM).Wherein, RAM is meant the storer that can randomly, individually conduct interviews, visit the required time basic fixed by instruction to each storage unit.
CPU embodiment shown in Figure 3, its modular construction is more detailed, specifically can comprise:
Load/Store parts 306 are used to send loading or storage instruction, read or write required data by data storage manager 303 from data storage array 301;
Also comprise:
Be arranged in the clock control module 309 of data storage manager, be used for each array block, judge in next clock period whether the request of access at this array block is arranged at described data storage array 301; If have, then at next clock period clock signal to this array block, otherwise, forbid that in the next clock period clock signal exports this array block to.
Embodiment shown in Figure 3 also comprises instruction bus 310 and data bus 311, and the two only is logical partitioning, and in fact, if the bus time-sharing multiplex, the two is same physically.
For the request of access of pointing to described data storage array, a kind of situation is, initiates by CPU is inner, then in risc architecture, all can send to data storage manager by loading Load/ storage Store parts.Finish corresponding read-write operation by data storage manager then; If relate to computing, then call arithmetic unit and finish and get final product.Concrete request of access can comprise usually: address information, the control information of read or write; For write operation, can also comprise the required data that write.
Another kind of situation is, the request of access of the described data storage array of described sensing is the outside initiation of CPU, for example, for DMA (Direct Memory Access, direct memory access (DMA)), it can temporarily take data bus, directly sends request of access at data storage array to data storage manager.
In fact, because CPU inner structure more complicated, segmentation is gone down and is also had the place that does not much relate to, but because its most of function can belong to controller, so the present invention has not just described in detail one by one.Simple example is as follows:
For guaranteeing that instruction can go round and begin again, carry out down without any confusion, CPU may also need to use instruction counter to guarantee can know the address of next bar instruction when executing present instruction.Instruction counter work usually in two kinds of situation, the one, order is carried out, the 2nd, shift and carry out.Before program begins to carry out, the start address of program is sent into instruction counter; When execution command, instruction fetch unit or controller are with the content of automatic modify instruction counter, so that make the address of next the bar instruction that always will carry out of its maintenance.Because the great majority instruction is all carried out in order, gets final product so the process of revising just simply adds 1 usually.When running into transfer instruction such as JMP and instruct, the address of successor instruction (being the content of instruction counter) can not be as obtaining in order usually, but add a displacement addition of shifting forward or backward according to the address of present instruction and obtain, perhaps the address of the direct transfer that provides according to transfer instruction obtains.
Since between data storage array and CPU, exist the differentiation on the operating speed, thus may also need to use address register to keep address information, till the read/write operation of internal memory is finished.And address wire and data line great majority are time-sharing multiplexs, so also want addressed memory temporarily to preserve relevant address date.That is, when CPU and data storage array carry out message exchange (as, read and write data), need to use address register.
With reference to Fig. 4, show a kind of method embodiment of the CPU of reduction power consumption, this CPU comprises data storage array, comprising:
The request of access of data storage array among the CPU is pointed in step 401, reception; The request of access of the described data storage array of described sensing can be sent to the external reference request of data storage manager for the CPU external unit by data bus; The request of access of the described data storage array of described sensing also can be stored the inter access request that the Store parts send to data storage manager by loading Load/ for cpu controller;
If step 403 has, then at next clock period clock signal to this array block;
Step 404 otherwise, forbid that in the next clock period clock signal exports this array block to.
In a preferred embodiment of the invention, the data storage array of described CPU is tight coupling physical store module TCM, it comprises the sector block more than 4 or 4, and each sector block comprises the array block bank more than 4 or 4, promptly comprises 16 array blocks.
Preferably, for step 403, when control clock signal exports an array piece to, also comprise: control is effective status at the data enable signal of this array block.For step 404, when forbidding that clock signal exports an array piece to, also comprise: control is disarmed state at the data enable signal of this array block.
In a word, be able to smooth execution for guaranteeing instruction, in the prior art, the clock signal in any moment and data enable signal all are constant effective, thereby the power consumption of CPU is bigger.Only consider to reduce the CPU power consumption and those skilled in the art are general from the angle that changes the instruction execution priority, promptly under the condition of same CPU power consumption, how to execute instruction as much as possible, thereby improve the utilization factor of CPU, reduce the CPU power consumption indirectly, this design often needs all order set to be made greatly, changed than intricately.The present invention looks for another way, and has directly reduced the power consumption of data storage device, to the change minimum of CPU structure and operational process, and has reached the purpose that reduces the CPU power consumption equally also.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
More than to method and a kind of CPU device of using said method of a kind of CPU of reduction power consumption provided by the present invention, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1, a kind of CPU is characterized in that, comprising:
Data storage array comprises a plurality of array blocks, is used to store data;
Command memory is used for storage instruction;
Data storage manager is used to manage the request of access of pointing to described data storage array;
Instruction storage manager is used to manage the request of access of pointing to described command memory;
Controller is used for control and coordinates each functional part operation;
Arithmetical unit is used to finish various arithmetic sum logical operations;
Also comprise:
Be arranged in the clock control module of data storage manager, be used for each array block, judge in next clock period whether the request of access at this array block is arranged at described data storage array; If have, then at next clock period clock signal to this array block, otherwise, forbid that in the next clock period clock signal exports this array block to.
2, CPU as claimed in claim 1 is characterized in that, described data storage array is tight coupling physical store module TCM, and it comprises the sector block more than 4 or 4, and each sector block comprises the array block bank more than 4 or 4.
3, CPU as claimed in claim 1 or 2 is characterized in that,
When described clock control module control clock signal exported an array piece to, the data enable signal that clock control module also is used to control at this array block was an effective status;
When described clock control module forbade that clock signal exports an array piece to, the data enable signal that clock control module also is used to control at this array block was a disarmed state.
4, CPU as claimed in claim 3 is characterized in that,
The request of access of the described data storage array of described sensing is that the CPU external unit is sent to data storage manager by data bus.
5, CPU as claimed in claim 3 is characterized in that, also comprises loading Load/ storage Store parts;
The request of access of the described data storage array of described sensing is that cpu controller sends to data storage manager by loading Load/ storage Store parts.
6, a kind of method that reduces the CPU power consumption, this CPU comprises data storage array, it is characterized in that, comprising:
Receive the request of access of pointing to described data storage array;
At each array block in the described data storage array, judge in next clock period whether the request of access at this array block is arranged;
If have, then at next clock period clock signal to this array block, otherwise, forbid that in the next clock period clock signal exports this array block to.
7, method as claimed in claim 6 is characterized in that:
When control clock signal exports an array piece to, also comprise: control is effective status at the data enable signal of this array block;
When forbidding that clock signal exports an array piece to, also comprise: control is disarmed state at the data enable signal of this array block.
8, as claim 6 or 7 described methods, it is characterized in that:
The request of access of the described data storage array of described sensing is that the CPU external unit is sent to data storage manager by data bus.
9, as claim 6 or 7 described methods, it is characterized in that:
The request of access of the described data storage array of described sensing is that cpu controller sends to data storage manager by loading Load/ storage Store parts.
10, method as claimed in claim 6 is characterized in that, described data storage array is tight coupling physical store module TCM, and it comprises the sector block more than 4 or 4, and each sector block comprises the array block bank more than 4 or 4.
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| CNA2009100768123A CN101504566A (en) | 2009-01-21 | 2009-01-21 | Method for reducing CPU power consumption and CPU |
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| CNA2009100768123A CN101504566A (en) | 2009-01-21 | 2009-01-21 | Method for reducing CPU power consumption and CPU |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102169717A (en) * | 2011-05-06 | 2011-08-31 | 西安华芯半导体有限公司 | Memory device with data processing function |
| CN101770279B (en) * | 2009-01-07 | 2012-06-20 | 台湾积体电路制造股份有限公司 | System and method for reducing processor power consumption |
| CN111752643A (en) * | 2020-07-01 | 2020-10-09 | 成都傅立叶电子科技有限公司 | Universal FPGA array loading updating maintenance system and method |
| CN112147931A (en) * | 2020-09-22 | 2020-12-29 | 哲库科技(北京)有限公司 | Control method, device and equipment of signal processor and storage medium |
| CN112835842A (en) * | 2021-03-05 | 2021-05-25 | 深圳市汇顶科技股份有限公司 | Terminal sequence processing method, circuit, chip and electronic terminal |
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2009
- 2009-01-21 CN CNA2009100768123A patent/CN101504566A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101770279B (en) * | 2009-01-07 | 2012-06-20 | 台湾积体电路制造股份有限公司 | System and method for reducing processor power consumption |
| CN102169717A (en) * | 2011-05-06 | 2011-08-31 | 西安华芯半导体有限公司 | Memory device with data processing function |
| CN111752643A (en) * | 2020-07-01 | 2020-10-09 | 成都傅立叶电子科技有限公司 | Universal FPGA array loading updating maintenance system and method |
| CN111752643B (en) * | 2020-07-01 | 2023-06-09 | 成都傅立叶电子科技有限公司 | Universal FPGA array loading, updating and maintaining system and method |
| CN112147931A (en) * | 2020-09-22 | 2020-12-29 | 哲库科技(北京)有限公司 | Control method, device and equipment of signal processor and storage medium |
| WO2022062580A1 (en) * | 2020-09-22 | 2022-03-31 | 哲库科技(北京)有限公司 | Control method and apparatus for signal processor, device, and storage medium |
| CN112835842A (en) * | 2021-03-05 | 2021-05-25 | 深圳市汇顶科技股份有限公司 | Terminal sequence processing method, circuit, chip and electronic terminal |
| CN112835842B (en) * | 2021-03-05 | 2024-04-30 | 深圳市汇顶科技股份有限公司 | Terminal sequence processing method, circuit, chip and electronic terminal |
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