WO2022062580A1

WO2022062580A1 - Control method and apparatus for signal processor, device, and storage medium

Info

Publication number: WO2022062580A1
Application number: PCT/CN2021/105786
Authority: WO
Inventors: 刘君
Original assignee: 哲库科技(北京)有限公司
Priority date: 2020-09-22
Filing date: 2021-07-12
Publication date: 2022-03-31
Also published as: CN112147931A; CN112147931B

Abstract

Disclosed are a control method and apparatus for a signal processor, a device, and a storage medium. The method comprises: according to an unexecuted instruction sequence having a preset length, determining the idle information of a target instruction unit corresponding to the unexecuted instruction sequence, wherein the idle information comprises an idle length without continuous operation (S101); and according to the determined idle information, switching on or off a power supply or a clock corresponding to the target instruction unit (S102). Thus, the present application can improve the power consumption efficiency of the signal processor in a working state, and can achieve the purpose of reducing power consumption.

Description

A control method, apparatus, device and storage medium for a signal processor

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed with the China Patent Office on September 22, 2020, the application number is 202011000843.3, and the application name is "a control method, device, equipment and storage medium for a signal processor", all of which are The contents are incorporated herein by reference.

technical field

The present application relates to the field of wireless communication technologies, and in particular, to a control method, apparatus, device, and storage medium for a signal processor.

Background technique

In the current wireless communication system, the vector signal processor has different types of signal processing operations, and different types of signal processing operations use different instruction units. For example, a signal processor with a Variable Length Instruction Word (VLIW) structure may include a Load (LD) instruction unit, a Store (ST) instruction unit, and an Arithmetic Logic instruction unit (Arithmetic Logic). Unit, ALU) and matrix operation instruction unit.

However, for the signal processor of the VLIW structure, in some cases, the LD instruction unit and the ALU instruction unit need to be used for operation. At this time, the ST instruction unit and the matrix operation instruction unit are in an idle state; in some cases, the ST instruction needs to be used. The unit and the matrix operation instruction unit operate. At this time, the LD instruction unit and the ALU instruction unit are in an idle state. Since the current signal processor cannot adjust the power consumption of each instruction unit according to the usage of the instruction unit, the power consumption efficiency of the signal processor is low.

SUMMARY OF THE INVENTION

The present application provides a control method, device, device and storage medium for a signal processor, which can improve the power consumption efficiency of the signal processor in a working state, and can achieve the purpose of saving power consumption.

In order to achieve the above-mentioned purpose, the technical scheme of the present application is achieved in this way:

In a first aspect, an embodiment of the present application provides a control method for a signal processor, the method comprising:

Determine the idle information of the target instruction unit corresponding to the unexecuted instruction sequence based on the unexecuted instruction sequence of preset length; wherein, the idle information includes the idle length of continuous no operation;

According to the determined idle information, switch operation is performed on the power supply or the clock corresponding to the target instruction unit.

In a second aspect, an embodiment of the present application provides a control device for a signal processor, where the control device for the signal processor includes a determination unit and a control unit; wherein,

The determining unit is configured to determine the idle information of the target instruction unit corresponding to the unexecuted instruction sequence based on the unexecuted instruction sequence of the preset length; wherein, the idle information includes the idle length of continuous no operation;

The control unit is configured to perform switching operations on the power supply or the clock corresponding to the target instruction unit according to the determined idle information.

In a third aspect, an embodiment of the present application provides a signal processing device, and the signal processing device includes a memory and a processor; wherein,

the memory for storing executable instructions capable of being executed on the processor;

The processor is configured to execute the method according to the first aspect when executing the executable instructions.

In a fourth aspect, an embodiment of the present application provides a chip, where the chip includes a memory and a processor; wherein,

The processor is configured to cause the signal processing device on which the chip is installed to execute the method according to the first aspect when the executable instructions are executed.

In a fifth aspect, an embodiment of the present application provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program implements the method according to the first aspect when the computer program is executed by at least one processor.

Description of drawings

FIG. 1 is a schematic flowchart of a control method of a signal processor provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a logical architecture of a signal processing device according to an embodiment of the present application;

FIG. 3 is a schematic flowchart of another method for controlling a signal processor provided by an embodiment of the present application;

4 is a schematic flowchart of another method for controlling a signal processor provided by an embodiment of the present application;

5 is a schematic structural diagram of a control device for a signal processor provided by an embodiment of the present application;

6 is a schematic diagram of a hardware structure of a signal processing device provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of a hardware structure of a chip according to an embodiment of the present application.

detailed description

In a first aspect, an embodiment of the present application provides a method for controlling a signal processor, the method comprising:

In some embodiments, the switching operation on the power supply or the clock corresponding to the target instruction unit according to the determined idle information includes:

According to the idle length corresponding to the target command unit, switch the power supply corresponding to the target command unit;

According to the idle length corresponding to the target command unit, a switch operation is performed on the clock corresponding to the target command unit.

According to the idle length and the first delay value corresponding to the target command unit, switch the power supply corresponding to the target command unit;

According to the idle length and the second delay value corresponding to the target command unit, switch the clock corresponding to the target command unit;

Wherein, the first delay value represents the instruction delay required by the target command unit to restore power supply, and the second delay value represents the command delay required by the target command unit to recover the clock.

In some embodiments, the switching operation on the power supply corresponding to the target command unit according to the idle length and the first delay value corresponding to the target command unit includes:

calculating a first difference between the idle length and the first delay value;

comparing the first difference with a first preset threshold;

If the first difference value is greater than or equal to the first preset threshold value, a shutdown operation is performed on the power supply corresponding to the target instruction unit.

In some embodiments, after performing the shutting down operation on the power supply corresponding to the target instruction unit, the method further includes:

If the waiting time period satisfies the first difference value, a power-on operation is performed on the power supply of the target instruction unit.

In some embodiments, when the first difference value is smaller than the first preset threshold value, the target instruction unit according to the idle length and the second delay value corresponding to the target instruction unit The corresponding clock is switched on and off, including:

calculating a second difference between the idle length and the second delay value;

comparing the second difference with a second preset threshold;

If the second difference value is greater than or equal to the second preset threshold value, a shutdown operation is performed on the clock corresponding to the target instruction unit.

In some embodiments, after performing the shutdown operation on the clock corresponding to the target instruction unit, the method further includes:

If the waiting time period satisfies the second difference value, a power-on operation is performed on the power supply of the target instruction unit.

In some embodiments, the method further includes:

Determine the instruction count value, start from the instruction count value and count, and obtain the unexecuted instruction sequence of preset length;

storing the start instruction count value and the idle length corresponding to the target instruction unit for which the clock or power supply shutdown operation is to be performed into a memory;

When the current instruction count value is the start instruction count value, the step of switching the power supply or the clock corresponding to the target instruction unit according to the determined idle information is performed.

In some embodiments, the method further includes:

When the current instruction count value is greater than or equal to the sum of the start instruction count value and the idle length in the memory, the start instruction count value and the idle length are removed from the memory.

In some embodiments, the target instruction unit includes at least one of: a load instruction unit, a storeback instruction unit, an arithmetic logic instruction unit, and a matrix operation instruction unit.

In some embodiments, the control unit is configured to switch the power supply corresponding to the target instruction unit according to the idle length corresponding to the target instruction unit; and, according to the idle length corresponding to the target instruction unit, perform a switching operation on The clock corresponding to the target instruction unit performs a switching operation.

In some embodiments, the control unit is configured to switch the power supply corresponding to the target command unit according to the idle length and the first delay value corresponding to the target command unit; and according to the target command unit The corresponding idle length and the second delay value are used to switch the clock corresponding to the target command unit; wherein, the first delay value represents the command delay required by the target command unit to restore power supply, and the The second delay value represents the instruction delay required for the target instruction unit to recover the clock.

In some embodiments, the control device of the signal processor further includes a calculation unit configured to calculate a first difference between the idle length and the first delay value;

The control unit is further configured to compare the first difference with a first preset threshold; if the first difference is greater than or equal to the first preset threshold, The power supply corresponding to the target command unit performs a shutdown operation.

In some embodiments, the control unit is further configured to perform a power-on operation on the power supply of the target instruction unit if the waiting time period satisfies the first difference value.

In some embodiments, the calculating unit is further configured to calculate a second difference between the idle length and the second delay value;

The control unit is further configured to compare the second difference with a second preset threshold; if the first difference is less than the first preset threshold and the second difference If the value is greater than or equal to the second preset threshold value, a shutdown operation is performed on the clock corresponding to the target instruction unit.

In some embodiments, the control unit is further configured to perform a power-on operation on the power supply of the target instruction unit if the waiting time period satisfies the second difference.

In some embodiments, the control device of the signal processor further includes a buffer unit;

The determining unit is further configured to determine an instruction count value, start from the instruction count value and count, and obtain an unexecuted instruction sequence of a preset length;

The cache unit is configured to store the start instruction count value and the idle length corresponding to the target instruction unit for which the clock or power supply shutdown operation is to be performed in the memory;

The control unit is further configured to perform the switching operation of switching the power supply or the clock corresponding to the target instruction unit according to the determined idle information when the current instruction count value is the start instruction count value. step.

In some embodiments, the control device of the signal processor further includes a discarding unit configured to, when the current instruction count value is greater than or equal to the sum of the start instruction count value and the idle length in the memory, The start instruction count value and the free length are removed from the memory.

In a third aspect, an embodiment of the present application provides a signal processing device, where the signal processing device includes a memory and a processor; wherein,

The processor is configured to execute the method according to any one of the first aspects when executing the executable instructions.

The processor is configured to cause the signal processing device on which the chip is installed to execute the method according to any one of the first aspects when executing the executable instructions.

In a fifth aspect, an embodiment of the present application provides a computer storage medium, where the computer storage medium stores a computer program, and when the computer program is executed by at least one processor, implements the method according to any one of the first aspects .

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the related application, but not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

It should be noted that the Variable Length Instruction Word (VLIW) refers to an instruction whose word length is not fixed. For example, in a variable-length instruction set, the word length of an instruction may be 1 byte, 2 bytes, 3 bytes, 4 bytes, or more. A Fixed Length Instruction Word (FLIW) refers to an instruction with a fixed word length. For example, in a fixed-length instruction set, all instructions are 32 bytes long. Generally speaking, fixed-length instruction words are used in reduced instruction set computers, while variable length instruction words are used in complex instruction set computers.

In a current wireless communication system, a vector signal processor (Vector digital signal processor, VDSP) performs different types of signal processing operations, and different types of signal processing operations use different instruction units. For example, a signal processor with a VLIW structure may include an LD instruction unit, an ST instruction unit, an ALU instruction unit, and a matrix operation instruction unit.

However, for the signal processor of the VLIW structure, in some cases, the LD instruction unit and the ALU instruction unit need to be frequently used for operation. At this time, the ST instruction unit and the matrix operation instruction unit will not operate, that is, in an idle state; and some In this case, the ST instruction unit and the matrix operation instruction unit need to be used. At this time, the LD instruction unit and the ALU instruction unit are in an idle state. That is to say, since the current signal processor cannot adjust the power consumption of each instruction unit according to the usage of the instruction unit, the power consumption efficiency of the signal processor is low.

Based on this, a signal processor control method provided by an embodiment of the present application, the basic idea of the method is: based on an unexecuted instruction sequence of a preset length, determine the target instruction unit corresponding to the unexecuted instruction sequence. Idle information; wherein, the idle information includes the idle length of continuous non-operation; according to the determined idle information, switch operation is performed on the power supply or the clock corresponding to the target instruction unit. In this way, according to the future use of the target command unit, the power supply or clock corresponding to the target command unit is turned off and restored, which can reduce the invalid power consumption of the signal processor to the greatest extent, thereby improving the working state of the signal processor. The power consumption efficiency can improve the activation power consumption index of the signal processor, and achieve the purpose of saving power consumption.

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present application, referring to FIG. 1 , it shows a schematic flowchart of a control method for a signal processor provided by an embodiment of the present application. As shown in Figure 1, the method may include:

S101: Determine idle information of a target instruction unit corresponding to the unexecuted instruction sequence based on an unexecuted instruction sequence of a preset length; wherein the idle information includes an idle length of continuous non-operation.

It should be noted that the methods in the embodiments of the present application are applied to a control device of a signal processor, or a signal processor (or referred to as a signal processing device) integrated with the device.

In this embodiment of the present application, the target instruction unit may include at least one of the following: a load instruction unit, a store-back instruction unit, an arithmetic logic instruction unit, and a matrix operation instruction unit. That is to say, the target instruction unit may be a load instruction unit, a store-back instruction unit, an arithmetic logic instruction unit or a matrix operation instruction unit, etc., which are not specifically limited in this embodiment of the present application.

It should also be noted that, for an unexecuted instruction sequence with a preset length, since the operation instruction is stored in the program memory (Program Memory, PM), the pre-set value from the current instruction count value (Program Counter, PC) can be obtained through the PM. A sequence of unexecuted instructions of set length. Here, the preset length may be represented by W, where W is an integer greater than 0, but the specific value of W is set according to the actual situation, which is not specifically limited in this embodiment of the present application.

In this way, after obtaining the unexecuted instruction sequence of preset length, statistical analysis can be performed on the unexecuted instruction sequence of preset length to determine the start instruction count value corresponding to the target instruction unit and the idle length of continuous non-operation; In other words, the idle information when the target instruction unit is in the idle state continuously can be determined, and the idle information may include the start instruction count value and the idle length of continuous no operation, so that the usage of the target instruction unit in the future period of time can be obtained.

Wherein, regardless of the preset length or the idle length, the embodiment of the present application can be represented by the number of instruction cycles. Here, an instruction cycle specifically refers to the time to fetch an instruction and execute the instruction, which can generally consist of several machine cycles, and an instruction cycle refers to the total time required from fetching an instruction, analyzing an instruction to executing it. That is to say, taking the idle length as an example, the idle length corresponding to the target instruction unit may also be referred to as the length of the target instruction unit without operations for N consecutive instruction cycles, where N is an integer greater than 0.

S102: According to the determined idle information, perform a switching operation on the power supply or the clock corresponding to the target instruction unit.

It should be noted that, after the idle information corresponding to the target instruction unit is obtained, the power supply or clock shutdown and recovery operations corresponding to the target instruction unit can be controlled according to the idle information. Specifically, in some embodiments, the switching operation on the power supply or the clock corresponding to the target instruction unit according to the determined idle information may include:

It should also be noted that the power supply corresponding to the target command unit can be turned off and restored according to the idle length corresponding to the target command unit, or the power supply corresponding to the target command unit can be turned off and restored according to the idle length of the target command unit. . However, there will be a certain command delay due to power recovery and clock recovery. That is to say, whether it is switching the power supply corresponding to the target command unit or switching the clock corresponding to the target command unit, it is necessary to consider when delay situation. Therefore, in some embodiments, the switching operation on the power supply or the clock corresponding to the target instruction unit according to the determined idle information may include:

According to the idle length and the second delay value corresponding to the target command unit, a switch operation is performed on the clock corresponding to the target command unit.

That is, the power supply shutdown and recovery operations are related to the idle length and the first delay value corresponding to the target instruction unit, and the clock shutdown and recovery operations are related to the idle length and the second delay value corresponding to the target instruction unit.

In some embodiments, for the power supply, the switching operation of the power supply corresponding to the target command unit according to the idle length and the first delay value corresponding to the target command unit may include:

comparing the first difference with a first preset threshold;

Further, after the power supply corresponding to the target instruction unit is turned off, the method may further include:

It should be noted that, in the case of performing a shutdown operation on the power supply corresponding to the target command unit, the power supply corresponding to the target command unit can be restored after waiting for the length of the first difference.

In some embodiments, for the clock, when the first difference value is smaller than the first preset threshold value, according to the idle length corresponding to the target instruction unit and the second delay value, the The clock corresponding to the target instruction unit performs a switching operation, which may include:

comparing the second difference with a second preset threshold;

Further, after the shutdown operation is performed on the clock corresponding to the target instruction unit, the method may further include:

It should be noted that, in the case of performing a shutdown operation on the clock corresponding to the target instruction unit, the clock corresponding to the target instruction unit can be recovered after waiting for the length of the second difference.

It should also be noted that the idle length corresponding to the target instruction unit can be represented by N, the first delay value can be represented by D2, the second delay value can be represented by D1, and the first preset threshold value can be represented by T2, The second preset threshold value may be represented by T1; and T2 is greater than T1, that is, the first preset threshold value is greater than the second preset threshold value.

In this way, for the target command unit, if N-D2 is greater than or equal to T2, the control device of the signal processor can turn off the power supply corresponding to the target command unit, and wait for N-D2 command cycles to restore the power supply. In the case where N-D2 is less than T2, if N-D1 is greater than or equal to T1, the control device of the signal processor can turn off the clock corresponding to the target instruction unit and restore the clock after waiting for N-D1 instruction cycles.

In short, based on the unexecuted instruction sequence of the preset length, the usage of the target instruction unit in the future can be counted, that is, the idle information corresponding to the target instruction unit; and then the target instruction unit can be closed and restored according to the idle information. Clock or turn off and restore the power supply, so as to minimize the invalid power consumption of the signal processor and achieve the purpose of saving power consumption.

Referring to FIG. 2 , it shows a schematic diagram of a logical architecture of a signal processing device provided by an embodiment of the present application. As shown in FIG. 2, the logic architecture may include a program memory module 201, an execution prediction and control (Execution Statistic & Control, ESC) module 202, a first instruction unit 203, a second instruction unit 204, a third instruction unit 205, and a third instruction unit 205. Four instruction units 206 and a first first-in, first-out (First Input First Output, FIFO) queue 207, a second FIFO queue 208, a third FIFO queue 209, and a fourth FIFO queue 210. The first instruction unit 203 can perform the LD operation, the second instruction unit 204 can perform the ST operation, the third instruction unit 205 can perform the ALU operation, and the fourth instruction unit 206 can perform the matrix operation; An instruction unit 203 corresponds to the second FIFO queue 208 corresponds to the second instruction unit 204 , the third FIFO queue 209 corresponds to the third instruction unit 205 , and the fourth FIFO queue 210 corresponds to the fourth instruction unit 206 . Here, the first FIFO queue 207, the second FIFO queue 208, the third FIFO queue 209 and the fourth FIFO queue 210 may also be referred to as special registers (Execution Interval FIFO, EIF) corresponding to each instruction unit. In addition, the logic architecture can also include a register module, in which the instruction count value can be stored, such as PC=1000; in addition, the register module can also include a set of prediction control registers (Predict Ctrl Register, PCR) , not shown in Figure 2. That is to say, the logical architecture can be regarded as consisting of an ESC module, an EIF corresponding to each instruction unit, and a set of PCRs.

It should be noted that the first FIFO queue 207, the second FIFO queue 208, the third FIFO queue 209 and the fourth FIFO queue 210 may be a set of memories (or registers), that is, each FIFO queue corresponds to a memory ( or register); it can also be a memory (or register), that is, the four FIFO queues are in the same memory or register. In the embodiments of the present application, no limitation is made to this.

Based on the example of the logic architecture shown in FIG. 2 , the ESC module 202 is the core of the logic architecture, which can be used to periodically obtain a sequence of unexecuted instructions of a preset length from the program memory module 201 , and then count the consecutive unexecuted instruction sequences of each instruction unit. The idle information of the operation is controlled, and the clock (Clock, CLK) and the power supply (Power, PWR) of the corresponding instruction unit are controlled to be turned off and restored according to the idle information of each instruction unit. The idle information for each instruction unit will be cached in the corresponding EIF, and the ESC module 202 can start and stop the corresponding clock or power supply according to the current PC value and the first register content in the EIF, that is, shut down and resume operations.

Exemplarily, as shown in FIG. 2, there are two execution vacancies in the EIF corresponding to the first instruction unit 203, including: an execution vacancy with a length of 4 instruction cycles starting from PC=1000 and an execution vacancy starting from PC=1005 with a length of 4 instruction cycles. 4 instruction cycle execution vacancies. If T1 is equal to 2 instruction cycles, T2 is equal to 3 instruction cycles, D1 is set to 1, and D2 is set to 3; since 4-D2 is smaller than T2 but 4-D1 is larger than T1, then the first instruction unit 203 will be set when PC is 1001. Turn off the clock corresponding to the first command unit 203, and restore the clock corresponding to the first command unit 203 when the PC is 1004; then turn off the clock corresponding to the first command unit 203 when PC=1006, and restore the first command when PC=1009 The clock corresponding to unit 203 . However, there is an execution vacancy in the EIF corresponding to the third instruction unit 205, an execution vacancy with a length of 6 instruction cycles starting from PC=1003, that is, the idle length corresponding to the third instruction unit 205 is 6, at this time, 6-D2 is greater than or equal to T2, then the power supply can be turned off, that is, the ESC module 202 will turn off the power supply corresponding to the third command unit 205 when PC=1004, and turn on the power supply corresponding to the third command unit 205 when PC=1007.

An embodiment of the present application provides a control method for a signal processor. Based on an unexecuted instruction sequence of a preset length, idle information of a target instruction unit corresponding to the unexecuted instruction sequence is determined; wherein, the idle information includes continuous The idle length of no operation; according to the determined idle information, switch operation is performed on the power supply or the clock corresponding to the target instruction unit. In this way, according to the future use of the target command unit, the power supply or clock corresponding to the target command unit is turned off and restored, which can reduce the invalid power consumption of the signal processor to the greatest extent, thereby improving the working state of the signal processor. The power consumption efficiency can improve the activation power consumption index of the signal processor, and achieve the purpose of saving power consumption.

In another embodiment of the present application, before determining the idle information of the target instruction unit corresponding to the unexecuted instruction sequence based on the unexecuted instruction sequence of the preset length, the control device of the signal processor also needs to For the length of the unexecuted instruction sequence, the idle information corresponding to each instruction unit obtained by statistics is cached in the memory (eg, FIFO queue) corresponding to each instruction unit, so as to switch the power supply or clock corresponding to the target instruction unit. In some embodiments, the method may also include:

Further, in some embodiments, the method may also include:

It should be noted that, first determine the instruction count value, such as PC=1000, then start from PC=1000 and count to obtain the unexecuted instruction sequence of preset length; then the target instruction of the clock or power supply shutdown operation to be executed The idle information corresponding to the unit (including the start instruction count value and the idle length) is stored in the memory. Exemplarily, if the start instruction count value stored in the memory is 1000 and the idle length is 4, then when the current instruction count value is 1000, the power supply or clock corresponding to the target instruction unit can be switched at this time. ; Finally, when the current instruction count value is greater than or equal to 1004, the stored data can be removed from the memory or discarded, and the data includes the start instruction count value (1000) and the idle length (4).

Specifically, in the case that the current instruction count value is the start instruction count value, for the power supply, according to the idle length and the first delay value stored in the memory, the corresponding value of the target instruction unit can be The power supply is switched on and off, which may specifically include: calculating a first difference between the idle length and the first delay value; comparing the first difference with a first preset threshold; If the first difference value is greater than or equal to the first preset threshold value, a shutdown operation is performed on the power supply corresponding to the target command unit.

In the case that the current instruction count value is the start instruction count value, for the clock, when the first difference value is smaller than the first preset threshold value, it can be determined according to the idle length and For the second delay value, performing a switching operation on the clock corresponding to the target instruction unit, which may specifically include: calculating a second difference between the idle length and the second delay value; The value is compared with a second preset threshold value; if the second difference value is greater than or equal to the second preset threshold value, a shutdown operation is performed on the clock corresponding to the target instruction unit.

It should also be noted that the control device of the signal processor caches the idle information corresponding to each instruction unit obtained by statistics to the memory (for example, the FIFO queue corresponding to each instruction unit) according to the unexecuted instruction sequence of the preset length. , to update the EIF. In some embodiments, taking the FIFO queue as an example, the method may further include:

Determine the instruction count value, and when the FIFO queues corresponding to all the instruction units are in an under-full state, starting from the instruction count value, obtain an unexecuted instruction sequence of a preset length;

Analyzing the to-be-executed instructions in the unexecuted instruction sequence, determining the instruction type of the to-be-executed instruction; and determining the statistical strategy of the to-be-executed instruction according to the determined instruction type;

According to the determined statistics strategy, the idle information obtained by statistics of each instruction unit is sequentially buffered to the FIFO queue corresponding to each instruction unit.

It should be noted that different instruction types correspond to different statistical strategies. Here, the instruction types may include: a loop start instruction (Loop start Instruction) type, a loop end instruction (Loop end Instruction) type, a branch instruction (Branch Instruction) type, and a common instruction (Other Instruction) type.

Illustratively, referring to FIG. 3 , it shows a schematic flowchart of a control method of another signal processor provided by an embodiment of the present application. As shown in Figure 3, the method may include:

S301: Obtain the instruction count value;

It should be noted that, when acquiring the instruction count value, the delay arrival also needs to be considered, and the sum of the instruction count value and the delay value can be determined as the acquired instruction count value. For example, if the PC value is equal to 1000, considering the delay arrival situation, the instructions after 1005 can be analyzed, that is, the instruction count value obtained here is equal to 1005.

S302: Determine whether all FIFO queues are not full;

S303: If the judgment result is no, set the next instruction count value;

S304: if the judgment result is yes, obtain the unexecuted instruction sequence of preset length from the program memory;

It should be noted that, for S302, if the FIFO queues corresponding to all the instruction units are not in the under-full state, indicating that the judgment result is no, then S303 will be executed; if the FIFO queues corresponding to all the instruction units are in the under-full state, indicating that If the judgment result is yes, then S304 will be executed.

It should also be noted that when S303 is executed, since the FIFO queues corresponding to all the instruction units are not in an under-full state, the information cannot be cached in the EIF at this time, and the next instruction count value needs to be set, that is, PC+1 is obtained. The delay value also needs to be taken into consideration; then the process can be ended, or it can wait to obtain the next instruction count value, and then re-execute the operation of judging whether the FIFO queues corresponding to all instruction units are not full according to the new instruction count value.

S305: Analyze the instructions to be executed in the instruction sequence one by one;

S306: when the to-be-executed instruction is a cycle end instruction type, write previously counted idle information into the corresponding FIFO queue;

S307: write the loop end instruction into the corresponding FIFO queue, and return to step S305;

S308: when the to-be-executed instruction is a cycle start instruction type, write previously counted idle information into the corresponding FIFO queue;

S309: Write the cycle start instruction and the number of cycles into the corresponding FIFO queue, and return to step S305;

S310: when the to-be-executed instruction is a branch instruction type, write previously counted idle information into the corresponding FIFO queue;

S311: Set the count value of the next instruction to be jumped by the branch instruction;

S312: when the to-be-executed instruction is a common instruction type, determine whether the to-be-executed instruction is the same as the current instruction;

S313: if the judgment result is yes, increase the idle length count value of the instruction;

S314: If the judgment result is no, write the previously counted idle information into the corresponding FIFO queue, restart the count according to the current instruction and set the idle length count value to 1, and return to step S305;

S315: When all the to-be-executed instructions in the instruction sequence have been analyzed, set the next instruction count value.

It should be noted that, after S305, according to the instruction type of the instruction to be executed, a corresponding statistical strategy can be selected. For example, the loop end instruction type corresponds to the first statistical strategy, the loop start instruction type corresponds to the second statistical strategy, the branch instruction type corresponds to the third statistical strategy, and the common instruction type corresponds to the fourth statistical strategy, as follows:

If the to-be-executed instruction is the cycle end instruction type, then the first statistical strategy composed of S306 and S307 may be selected for execution, and then return to S305 to analyze the next to-be-executed instruction.

If the instruction to be executed is the cycle start instruction type, then the second statistical strategy composed of S308 and S309 may be selected for execution, and then return to S305 to analyze the next instruction to be executed.

If the instruction to be executed is a branch instruction type, then the third statistical strategy composed of S310 and S311 can be selected for execution; the next instruction count value here specifically refers to the PC value that the branch instruction needs to jump to next, and also needs to be considered delay value; then after S311 , the process can be ended, or the operation of judging whether the FIFO queues corresponding to all the instruction units are not full can be performed again after waiting for the instruction count value.

If the instruction to be executed is a common instruction type, then a fourth statistical strategy composed of S312, S313 and S314 can be selected for execution, and then return to S305 to analyze the next instruction to be executed.

It should also be noted that when all the to-be-executed instructions in the instruction sequence are analyzed, the next instruction count value can be set; if the length of the instruction sequence is W, then the next instruction count value is the instruction after the W length. The count value also needs to consider the delay value.

In this way, the ESC module can count and update the EIF according to the PC value, the register module and the code segment in the program memory (ie, the unexecuted instruction sequence of preset length), that is, write the idle information of each instruction unit into the corresponding FIFO queue. , that is, write the instruction count value of each instruction unit and the corresponding idle length into the corresponding FIFO queue.

It can be understood that after the idle information of each instruction unit is written into the corresponding FIFO queue, the idle information of the corresponding instruction unit can be obtained by reading the corresponding FIFO queue. In some embodiments, the determining the idle information corresponding to the target instruction unit in the instruction sequence may include:

For the target FIFO queue corresponding to the target instruction unit, determine whether the current instruction count value is equal to the instruction count value in the first element of the target FIFO queue;

If the judgment result is yes, read the first element of the target FIFO queue to obtain idle information corresponding to the target instruction unit.

Further, in some embodiments, after the reading the first element of the target FIFO queue, the method may further include:

When the current instruction count value is greater than or equal to the sum of the instruction count value in the first element and the idle length, the first element is popped from the target FIFO queue.

It should be noted that each bit element in the FIFO queue here includes an instruction count value and a corresponding idle length. The target command unit corresponds to the target FIFO queue; for the target command unit, when the current command count value is equal to the command count value in the first element of the target FIFO queue, the first element of the target FIFO queue can be read to obtain the target Idle information corresponding to the instruction unit, so as to switch the power supply or clock corresponding to the target instruction unit according to the idle information. And after reading the first element of the target FIFO queue, if the current instruction count value is greater than or equal to the sum of the instruction count value and the idle length in the first element, it means that the first element has been executed, and the target FIFO queue can be executed at this time. pops up the first element.

It should also be noted that, for the jumping situation of the branch instruction, in some embodiments, the method may further include:

When the current instruction count value is greater than the instruction count value corresponding to the target instruction unit, calculating a third difference between the current instruction count value and the instruction count value corresponding to the target instruction unit;

performing a subtraction operation on the idle length corresponding to the target instruction unit and the third difference to obtain the remaining idle count value corresponding to the target instruction unit;

According to the remaining idle count value and the first delay value, control the power supply corresponding to the target command unit to perform shutdown and recovery operations;

According to the remaining idle count value and the second delay value, the clock corresponding to the target instruction unit is controlled to perform shutdown and recovery operations.

That is to say, when the current instruction count value is greater than the instruction count value corresponding to the target instruction unit, the current instruction count value and the idle length and instruction count value corresponding to the target instruction unit can be calculated to obtain the corresponding instruction count value of the target instruction unit. Remaining idle count value.

After the remaining idle count value is obtained, the power supply corresponding to the target command unit can be controlled to perform shutdown and recovery operations according to the remaining idle count value and the first delay value; specifically, it may include: calculating the remaining idle count value and the the fourth difference between the first delay values; compare the fourth difference with the first preset threshold; if the fourth difference is greater than or equal to the first preset threshold, then The power supply corresponding to the target command unit is turned off, and the power supply corresponding to the target command unit is restored after waiting for the length of the fourth difference. In addition, according to the remaining idle count value and the second delay value, controlling the clock corresponding to the target instruction unit to perform shutdown and recovery operations; specifically, it may include: when the fourth difference value is smaller than the first preset threshold value, calculating the the fifth difference between the remaining idle count value and the second delay value; compare the fifth difference with the second preset threshold; if the fifth difference is greater than or equal to the second If the threshold value is preset, the clock corresponding to the target instruction unit is turned off, and the clock corresponding to the target instruction unit is restored after waiting for the length of the second difference.

For example, referring to FIG. 4 , it shows a schematic flowchart of a control method for another signal processor provided by an embodiment of the present application. As shown in Figure 4, the process may include:

S401: Determine whether there is loop control information in all FIFO queues;

S402: if the judgment result is no, judge whether the target FIFO queue is empty;

It should be noted that Figure 4 provides an example of the logic flow that the ESC module can control the clock and power supply voltage of each command unit according to the idle information obtained by the command execution statistics in the EIF, and this flow is only given without the for loop control information. An example of the process is illustrated as how it works.

That is to say, for S401, if the judgment result is yes, that is, there is loop control information, then the process can be ended; if the judgment result is no, that is, there is no loop control information, then S402 can be executed, that is, the target FIFO queue can be judged is empty.

S403: If the judgment result is no, then judge whether the current PC value is equal to the PC value in the first element of the target FIFO queue;

It should be noted that, for S402, if the judgment result is yes, it indicates that the current target FIFO queue is empty, at this time, it can return to S401, and then select the next FIFO queue as the target FIFO queue and continue to execute S402; otherwise, if the judgment If the result is no, it indicates that the current target FIFO queue is not empty. At this time, S403 can be executed, that is, it is judged whether the current PC value is equal to the PC value in the first element of the target FIFO queue (current PC==PC of 1st FIFO element).

S404: If the judgment result is yes, obtain idle information corresponding to the target command unit, and perform a switch operation on the power supply or clock corresponding to the target command unit;

It should be noted that if the current PC value is equal to the PC value in the first element of the target FIFO queue, the first element of the target FIFO queue can be read at this time to obtain the idle information corresponding to the target instruction unit (including the PC value and the corresponding idle length L). ).

It is still assumed that the first delay value is represented by D2, the second delay value is represented by D1, the first preset threshold value is represented by T2, and the second preset threshold value is represented by T1; then when L-D2≥T2 , at this time, the power supply corresponding to the target command unit can be turned off, and the power supply can be restored after waiting for L-D2 command cycles; when L-D2<T2 and L-D1≥T1, the corresponding power supply of the target command unit can be turned off at this time. clock, and wait for L-D1 instruction cycles to recover the clock. Then after S404, continue to return to S401, select the next FIFO queue as the target FIFO queue and continue to execute S402.

S405: if the judgment result is no, then judge whether the current PC value is greater than or equal to the sum of the PC value and L in the first element;

S406: If the judgment result is yes, pop the first element in the target FIFO queue;

S407: if the judgment result is no, judge whether the current PC value is less than the PC value in the first element;

It should be noted that, for S405, L represents the idle length in the first element; it is judged whether the current PC value is greater than or equal to the sum of the PC value and L in the first element (current PC≥PC+L in 1st FIFO element) ; If the judgment result is yes, it indicates that the first element has been executed. At this time, S406 can be executed to pop the first element from the target FIFO queue; if the judgment result is no, S407 can be executed at this time, and it is necessary to continue to judge whether the current PC value is less than the first position. PC value in element (current PC ≥ PC in 1st FIFO element).

S408: if the judgment result is no, calculate the remaining idle count value corresponding to the target instruction unit;

S409: According to the remaining idle count value, perform a switch operation on the power supply or the clock corresponding to the target instruction unit.

It should be noted that, for S407, if the judgment result is yes, it indicates that the current PC value has not reached the PC value in the target FIFO queue. At this time, nothing is executed, and it continues to return to S401; if the judgment result is no, it indicates that the current PC value is not reached. The PC value has exceeded the PC value in the target FIFO queue. For example, in the case of a branch instruction jump, S408 and S409 need to be executed at this time.

Specifically, for the calculation of the remaining idle count value (idle count), it can be obtained according to idle count=L-(current PC-PC); assuming that the PC value is equal to 1000, the idle length L is equal to 10, and the current PC value is equal to 1005, this It can be calculated that the idle count is equal to 5.

For S409, it is still assumed that the first delay value is represented by D2, the second delay value is represented by D1, the first preset threshold value is represented by T2, and the second preset threshold value is represented by T1; then when idle When count-D2≥T2, the power supply corresponding to the target command unit can be turned off at this time, and the power supply can be restored after waiting for idle count-D2 instruction cycles; when idle count-D2<T2 and idle count-D1≥T1, At this time, the clock corresponding to the target instruction unit can be turned off, and the clock can be recovered after waiting for idle count-D1 instruction cycles. Then after S409, continue to return to S401, select the next FIFO queue as the target FIFO queue and continue to execute S402.

In short, the current wireless communication system can turn on and off some processing units according to the working state of the modem, or adjust the voltage and clock frequency of the processing units to save power. However, when the processing unit runs at a certain voltage and frequency, the usage of the instruction unit by the internal micro-processing is unbalanced when processing different tasks. However, in the embodiment of the present application, the usage of different instruction units in a future period of time can be counted by the instruction code, and the start time and duration of each instruction unit stop working (in an idle state) can be recorded by using the FIFO queue; and can also provide Loop code and branch code instruction unit occupancy information; finally, according to the future use of the instruction unit, the corresponding instruction unit is closed clock operation or safely shut down and restore the power supply, which can minimize the invalid power consumption of the processor; also That is to say, the embodiments of the present application can improve the microscopic power consumption efficiency of the processor in the working state, thereby improving the active power consumption index of the processor.

In addition, some VDSPs can be composed of two parts, a vector control unit (Vector control unit, VCU) and a vector data processing unit (Vector Data unit, VDU). Among them, the VCU mainly performs the control work, and the VDU performs the computation-intensive work, and the VCU accounts for a small part of the VDSP, and the VDU accounts for most of the area and power consumption of the VDSP. The VDSP under this structure can realize this function through the VCU. A possible implementation is to insert a fixed piece of code into the instruction code at certain intervals through the compiler. The function of this code is to count the occupancy of the instruction unit of the next running code, and to control the clock and power supply corresponding to the instruction unit. Shut down or resume at a specific time.

An embodiment of the present application provides a control method for a signal processor, and the specific implementation of the foregoing embodiment is described in detail through the foregoing embodiment. It can be seen from this that, according to the future use of the target instruction unit, the The corresponding power supply or clock is turned off and restored, which can minimize the invalid power consumption of the signal processor, thereby improving the power consumption efficiency of the signal processor in the working state, and improving the activation power consumption index of the signal processor. And achieve the purpose of saving power consumption.

In yet another embodiment of the present application, based on the same inventive concept as the foregoing embodiments, referring to FIG. 5 , it shows a schematic structural diagram of a control device 50 for a signal processor provided by an embodiment of the present application. As shown in FIG. 5 , the control device 50 of the signal processor may include a determination unit 501 and a control unit 502; wherein,

The determining unit 501 is configured to determine the idle information of the target instruction unit corresponding to the unexecuted instruction sequence based on the unexecuted instruction sequence of the preset length; wherein, the idle information includes the idle length of continuous no operation;

The control unit 502 is configured to perform switching operations on the power supply or the clock corresponding to the target instruction unit according to the determined idle information.

In some embodiments, the control unit 502 is specifically configured to switch the power supply corresponding to the target instruction unit according to the idle length corresponding to the target instruction unit; The clock corresponding to the target instruction unit performs a switching operation.

In some embodiments, the control unit 502 is specifically configured to perform a switching operation on the power supply corresponding to the target command unit according to the idle length and the first delay value corresponding to the target command unit; and according to the target command unit The corresponding idle length and the second delay value are used to switch the clock corresponding to the target command unit; wherein, the first delay value represents the command delay required by the target command unit to restore power supply, and the The second delay value represents the instruction delay required for the target instruction unit to recover the clock.

In some embodiments, referring to FIG. 5 , the control apparatus 50 of the signal processor may further include a calculation unit 503 configured to calculate a first difference between the idle length and the first delay value;

The control unit 502 is further configured to compare the first difference value with a first preset threshold value; if the first difference value is greater than or equal to the first preset threshold value, The power supply corresponding to the command unit performs a shutdown operation.

In some embodiments, the control unit 502 is further configured to perform a power-on operation on the power supply of the target instruction unit if the waiting time period satisfies the first difference.

In some embodiments, the calculating unit 503 is further configured to calculate a second difference between the idle length and the second delay value;

The control unit 502 is further configured to compare the second difference with a second preset threshold; if the first difference is less than the first preset threshold and the second difference is greater than or equal to the second preset threshold value, perform a shutdown operation on the clock corresponding to the target instruction unit.

In some embodiments, the control unit 502 is further configured to perform a power-on operation on the power supply of the target instruction unit if the waiting time period satisfies the second difference.

In some embodiments, referring to FIG. 5 , the control device 50 of the signal processor may further include a buffer unit 504; wherein,

The determining unit 501 is further configured to determine an instruction count value, start from the instruction count value and count, and obtain an unexecuted instruction sequence of a preset length;

The cache unit 504 is configured to store the start instruction count value and the idle length corresponding to the target instruction unit for which the clock or power supply shutdown operation is to be performed in the memory;

The control unit 502 is configured to perform the step of switching the power supply or the clock corresponding to the target instruction unit according to the determined idle information when the current instruction count value is the start instruction count value.

In some embodiments, referring to FIG. 5 , the control device 50 of the signal processor may further include a discarding unit 505, configured to be greater than or equal to the starting instruction count value in the memory and the When the free length is the sum, the start instruction count value and the free length are removed from the memory.

It can be understood that, in this embodiment, a "unit" may be a part of a circuit, a part of a processor, a part of a program or software, etc., of course, it may also be a module, and it may also be non-modular. Moreover, each component in this embodiment may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, or can be implemented in the form of software function modules.

If the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or Said part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, the computer software product is stored in a storage medium and includes several instructions for making a computer device (which can be It is a personal computer, a server, or a network device, etc.) or a processor (processor) that executes all or part of the steps of the method described in this embodiment. The aforementioned storage medium includes: U disk, mobile hard disk, read only memory (Read Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes.

Therefore, this embodiment provides a computer storage medium, where the computer storage medium stores a computer program, and when the computer program is executed by at least one processor, implements the method described in any one of the foregoing embodiments.

In yet another embodiment of the present application, for the composition of the control device 50 based on the signal processor and the computer storage medium, see FIG. 6 , which shows a schematic diagram of a specific hardware structure of a signal processing device 60 provided by an embodiment of the present application . As shown in FIG. 6 , the signal processing device 60 may include a processor 601, and the processor 601 may call and execute executable instructions from a memory, so as to implement the method described in any one of the foregoing embodiments.

Optionally, as shown in FIG. 6 , the signal processing device 60 may further include a memory 602 . The processor 601 may call and execute executable instructions from the memory 602 to implement the method described in any one of the foregoing embodiments.

The memory 602 may be a separate device independent of the processor 601 , or may be integrated in the processor 601 .

Optionally, as shown in FIG. 6 , the signal processing device 60 may further include a transceiver 603, and the processor 601 may control the transceiver 603 to communicate with other devices, specifically, may send information or data to other devices, or receive Information or data sent by other devices.

The transceiver 603 may include a transmitter and a receiver. The transceiver 603 may further include an antenna, and the number of the antenna may be one or more.

Optionally, the signal processing device 60 may specifically be the processor or the processing unit described in the foregoing embodiments, or a device integrated with the control apparatus 50 of the signal processor described in any one of the foregoing embodiments. Here, and the signal processing device 60 can implement the corresponding processes implemented by the processor in each method of the embodiments of the present application, which is not repeated here for brevity.

In yet another embodiment of the present application, for the composition of the control device 50 based on the signal processor and the computer storage medium, see FIG. 7 , which shows a schematic diagram of a specific hardware structure of a chip 70 provided by an embodiment of the present application. As shown in FIG. 7 , the chip 70 may include a processor 701, and the processor 701 may invoke and execute executable instructions from the memory to implement the method described in any one of the foregoing embodiments.

Optionally, as shown in FIG. 7 , the chip 70 may further include a memory 702 . The processor 701 may call and execute executable instructions from the memory 702 to implement the method described in any one of the foregoing embodiments.

The memory 702 may be a separate device independent of the processor 701 , or may be integrated in the processor 701 .

Optionally, the chip 70 may further include an input interface 703 . The processor 701 can control the input interface 703 to communicate with other devices or chips, and specifically, can obtain information or data sent by other devices or chips.

Optionally, the chip 70 may further include an output interface 704 . The processor 701 can control the output interface 704 to communicate with other devices or chips, and specifically, can output information or data to other devices or chips.

Optionally, the chip 70 can be applied to the multi-mode terminal described in the foregoing embodiments, and the chip can implement the corresponding processes implemented by the multi-mode terminal in each method of the embodiments of the present application. For the sake of brevity, details are not repeated here. .

It should be understood that the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-chip or a system-on-chip, such as a modem chip or a modem chip set.

It should be noted that, the processor in the embodiment of the present application may be an integrated circuit chip, which has signal processing capability. In the implementation process, each step of the above method embodiments may be completed by a hardware integrated logic circuit in a processor or an instruction in the form of software. The above-mentioned processor can be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA) or other available Programming logic devices, discrete gate or transistor logic devices, discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in conjunction with the embodiments of the present application may be directly embodied as executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media mature in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.

It should also be noted that, the memory in this embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Wherein, the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically programmable read-only memory (Erasable PROM, EPROM). Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. Volatile memory may be Random Access Memory (RAM), which acts as an external cache. By way of illustration and not limitation, many forms of RAM are available, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced SDRAM, ESDRAM), Synchronous link DRAM (Synchronous link DRAM, SLDRAM) ) and direct memory bus random access memory (Direct Rambus RAM, DRRAM). It should be noted that the memory of the systems and methods described herein is intended to include, but not be limited to, these and any other suitable types of memory.

It will be appreciated that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more Application Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP), Digital Signal Processing Device (DSP Device, DSPD), programmable Logic Devices (Programmable Logic Device, PLD), Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA), General Purpose Processors, Controllers, Microcontrollers, Microprocessors, Others for performing the functions described herein electronic unit or a combination thereof. For a software implementation, the techniques described herein may be implemented through modules (eg, procedures, functions, etc.) that perform the functions described herein. Software codes may be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

It should be noted that, in this application, the terms "comprising", "comprising" or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements , but also other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The above-mentioned serial numbers of the embodiments of the present application are only for description, and do not represent the advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined under the condition of no conflict to obtain new method embodiments.

The features disclosed in the several product embodiments provided in this application can be combined arbitrarily without conflict to obtain a new product embodiment.

The features disclosed in several method or device embodiments provided in this application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Industrial Applicability

In the embodiment of the present application, based on the unexecuted instruction sequence of a preset length, the idle information of the target instruction unit corresponding to the unexecuted instruction sequence is determined; wherein, the idle information includes the idle length of continuous no operation; according to the determined idle information The idle information of the target command unit is switched on and off for the power supply or clock corresponding to the target command unit. In this way, according to the future usage of the target command unit, the power supply or clock corresponding to the target command unit is turned off and restored, which can reduce the invalid power consumption of the signal processor to the greatest extent, thereby improving the signal processor in the working state. The power consumption efficiency can improve the activation power consumption index of the signal processor, and achieve the purpose of saving power consumption.

Claims

A control method of a signal processor, the method comprising:

Determine the idle information of the target instruction unit corresponding to the unexecuted instruction sequence based on the unexecuted instruction sequence of preset length; wherein, the idle information includes the idle length of continuous no operation;

According to the determined idle information, switch operation is performed on the power supply or the clock corresponding to the target instruction unit.
The method according to claim 1, wherein, according to the determined idle information, performing a switching operation on a power supply or a clock corresponding to the target instruction unit, comprising:

According to the idle length corresponding to the target command unit, switch the power supply corresponding to the target command unit;

According to the idle length corresponding to the target command unit, a switch operation is performed on the clock corresponding to the target command unit.
The method according to claim 1, wherein, according to the determined idle information, performing a switching operation on a power supply or a clock corresponding to the target instruction unit, comprising:

According to the idle length and the first delay value corresponding to the target command unit, switch the power supply corresponding to the target command unit;

According to the idle length and the second delay value corresponding to the target command unit, switch the clock corresponding to the target command unit;

Wherein, the first delay value represents the instruction delay required by the target command unit to restore power supply, and the second delay value represents the command delay required by the target command unit to recover the clock.
The method according to claim 3, wherein the switching operation of the power supply corresponding to the target command unit according to the idle length and the first delay value corresponding to the target command unit comprises:

calculating a first difference between the idle length and the first delay value;

comparing the first difference with a first preset threshold;

If the first difference value is greater than or equal to the first preset threshold value, a shutdown operation is performed on the power supply corresponding to the target instruction unit.
The method according to claim 4, wherein after the power supply corresponding to the target instruction unit is turned off, the method further comprises:

If the waiting time period satisfies the first difference value, a power-on operation is performed on the power supply of the target instruction unit.
The method according to claim 4, wherein, when the first difference value is smaller than the first preset threshold value, according to the idle length corresponding to the target instruction unit and the second delay value, the The clock corresponding to the target instruction unit performs a switching operation, including:

calculating a second difference between the idle length and the second delay value;

comparing the second difference with a second preset threshold;

If the second difference value is greater than or equal to the second preset threshold value, a shutdown operation is performed on the clock corresponding to the target instruction unit.
The method according to claim 6, wherein after performing the shutting down operation on the clock corresponding to the target instruction unit, the method further comprises:

If the waiting time period satisfies the second difference value, a power-on operation is performed on the power supply of the target instruction unit.
The method of claim 1, wherein the method further comprises:

Determine the instruction count value, start from the instruction count value and count, and obtain the unexecuted instruction sequence of preset length;

The start instruction count value and the idle length corresponding to the target instruction unit of the to-be-executed clock or power supply shutdown operation are stored in the memory;

When the current instruction count value is the start instruction count value, the step of switching the power supply or the clock corresponding to the target instruction unit according to the determined idle information is performed.
The method of claim 8, wherein the method further comprises:

When the current instruction count value is greater than or equal to the sum of the start instruction count value and the idle length in the memory, the start instruction count value and the idle length are removed from the memory.
The method according to any one of claims 1 to 9, wherein the target instruction unit includes at least one of the following: a load instruction unit, a store-back instruction unit, an arithmetic logic instruction unit, and a matrix operation instruction unit.
A control device of a signal processor, the control device of the signal processor includes a determination unit and a control unit; wherein,

The determining unit is configured to determine the idle information of the target instruction unit corresponding to the unexecuted instruction sequence based on the unexecuted instruction sequence of preset length; wherein, the idle information includes the idle length of continuous no operation;

The control unit is configured to perform switching operations on the power supply or the clock corresponding to the target instruction unit according to the determined idle information.
The control device according to claim 11, wherein the control unit is configured to switch the power supply corresponding to the target command unit according to the idle length corresponding to the target command unit; and according to the target command unit For the corresponding idle length, a switch operation is performed on the clock corresponding to the target instruction unit.
The control device according to claim 11, wherein the control unit is configured to switch the power supply corresponding to the target command unit according to the idle length and the first delay value corresponding to the target command unit; and According to the idle length corresponding to the target command unit and the second delay value, the clock corresponding to the target command unit is switched on and off; wherein, the first delay value represents the time required for the target command unit to restore power supply The instruction delay, the second delay value represents the instruction delay required by the target instruction unit to recover the clock.
The control device according to claim 13, wherein the control device of the signal processor further comprises a calculation unit configured to calculate a first difference between the idle length and the first delay value;

The control unit is further configured to compare the first difference with a first preset threshold; if the first difference is greater than or equal to the first preset threshold, The power supply corresponding to the target command unit performs a shutdown operation.
The control device according to claim 14, wherein the calculation unit is further configured to calculate a second difference between the idle length and the second delay value;

The control unit is further configured to compare the second difference with a second preset threshold; if the first difference is less than the first preset threshold and the second difference If the value is greater than or equal to the second preset threshold value, a shutdown operation is performed on the clock corresponding to the target instruction unit.
The control device according to claim 11, wherein the control device of the signal processor further comprises a buffer unit;

The determining unit is further configured to determine an instruction count value, start from the instruction count value and count, and obtain an unexecuted instruction sequence of a preset length;

The cache unit is configured to store the start instruction count value and the idle length corresponding to the target instruction unit of the clock or power supply shutdown operation to be performed in the memory;

The control unit is further configured to perform the switching operation of switching the power supply or the clock corresponding to the target instruction unit according to the determined idle information when the current instruction count value is the start instruction count value. step.
The control apparatus according to claim 16, wherein the control apparatus of the signal processor further comprises a discarding unit configured to be greater than or equal to the start instruction count value in the memory and the When the free length is the sum, the start instruction count value and the free length are removed from the memory.
A signal processing device comprising a memory and a processor; wherein,

the memory for storing executable instructions capable of being executed on the processor;

The processor is configured to execute the method according to any one of claims 1 to 10 when executing the executable instructions.
A chip comprising a memory and a processor; wherein,

the memory for storing executable instructions capable of being executed on the processor;

The processor is configured to cause the signal processing device on which the chip is installed to execute the method according to any one of claims 1 to 10 when the executable instructions are executed.
A computer storage medium, wherein the computer storage medium stores a computer program which, when executed by at least one processor, implements the method according to any one of claims 1 to 10.