CN101504567B - CPU, CPU instruction system and method for reducing CPU power consumption - Google Patents
CPU, CPU instruction system and method for reducing CPU power consumption Download PDFInfo
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- CN101504567B CN101504567B CN2009100768138A CN200910076813A CN101504567B CN 101504567 B CN101504567 B CN 101504567B CN 2009100768138 A CN2009100768138 A CN 2009100768138A CN 200910076813 A CN200910076813 A CN 200910076813A CN 101504567 B CN101504567 B CN 101504567B
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Abstract
The invention provides a CPU instruction system, which comprises an instruction memory, an instruction storage manager, an instruction reading component, a data cache and a clock control module. The instruction storage manager is used for managing an access request pointing to the instruction memory, taking out a corresponding instruction from the instruction memory according to the access request, and writing the instruction into the data cache of the instruction reading component; the instruction reading component is used for reading an instruction to be executed from the instruction memory through the instruction storage manager; the data cache is used for caching the instruction to be executed; and the clock control module positioned in the instruction storage manager is used for judging whether an access request aiming at the instruction memory exists in a next clock period, if so, outputting a clock signal to the instruction memory in the next clock period, otherwise, prohibiting the clock signal from being output to the instruction memory in the next clock period. By reducing the power consumption of a storage part in a CPU apparatus during running, the CPU instruction system reduces the power consumption of the whole CPU apparatus.
Description
Technical field
The present invention relates to cpu instruction control field, particularly relate to the method for a kind of CPU, a kind of cpu instruction system and a kind of CPU of reduction power consumption.
Background technology
CPU uses very extensive, and for example, CPU is applied among the various SOC (System On Chip, SOC(system on a chip)) as important devices.CPU relies on instruction to come computing and control system, and every money CPU has just stipulated a series of order set that match with its hardware circuit when design.Generally speaking; This order set comprises command memory, instruction fetch unit and instruction storage manager; Instruction storage manager is responsible for instruction is read from command memory; Send into the instruction fetch unit, control building block execution such as arithmetic unit or Load/Store (load) parts then.
In chip design and using, the CPU power consumption is the problem that must consider, and how reducing its power consumption also is that prior art is thirsted for an improved direction always.For example, publication number is the method that the Chinese patent of CN101162405 just discloses a kind of dynamic reduction CPU power consumption.This method can dynamically be adjusted the instruction operation speed of CPU according to the CPU occupation rate.In the CPU operational process; If being lower than the lower limit of setting, the occupation rate of CPU just the instruction operation speed of CPU is reduced; If being higher than the higher limit of setting, the occupation rate of CPU just the instruction operation speed of CPU is improved; Wherein the adjustment of the instruction operation speed of CPU is mainly through switch data Cache interface and instruction high speed storage interface, and changes that propagation delay time realizes.
Above-mentioned improvement project is carried out to CPU integral body; The improvement angle that so whether also has other? The CPU device is done further segmentation; It possibly comprise control section, arithmetic section and storage area; So whether can certain or a plurality of parts of CPU device be improved, perhaps does the operational process to certain or a plurality of parts improve, with the power consumption of further reduction CPU? Because in practical design with in using; Those skilled in the art are low more good more for the pursuit of power consumption, and any method that can reduce power consumption all needs.
Thereby, need the urgent technical matters that solves of those skilled in the art to be exactly at present: the power consumption that how can further reduce the CPU device.
Summary of the invention
Technical matters to be solved by this invention provides a kind of CPU device that can further reduce the solution of CPU device power consumption and use this solution; Reducing the power consumption that storage area is in operation in the CPU device, thereby reduce the power consumption of whole C PU device.
In order to solve the problems of the technologies described above, the embodiment of the invention discloses a kind of cpu instruction system, comprising:
Command memory is used for storage instruction;
Instruction storage manager is used to manage the access request of pointing to said command memory; And from command memory, take out corresponding instruction according to said access request, write in the data buffer of instruction fetch unit;
The instruction fetch unit is used for reading from command memory through said instruction storage manager the instruction of required execution;
Data buffer is arranged in said instruction fetch unit, is used for the said instruction that needs execution of buffer memory;
Also comprise:
Clock control module is arranged in said instruction storage manager, is used for judging the next clock period, and whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory; If do not have, then forbid that in the next clock period clock signal exports said command memory to;
Said instruction storage manager also comprises:
Caching management module is used to judge whether the memory capacity of said data buffer is full, if full, then ends to send the access request of pointing to said command memory.
Preferably, when said clock control module control clock signal exported command memory to, the data enable signal that clock control module also is used to control to this command memory was an effective status;
When said clock control module forbade that clock signal exports command memory to, the data enable signal that clock control module also is used to control to this command memory was a disarmed state.
Preferably, said data buffer is the data fifo buffer.
The embodiment of the invention also discloses a kind of CPU, comprising:
Data-carrier store is used to store data;
Data storage manager is used to manage the access request of pointing to said data-carrier store;
Command memory is used for storage instruction;
Instruction storage manager is used to manage the access request of pointing to said command memory; And from command memory, take out corresponding instruction according to said access request, write in the data buffer of instruction fetch unit;
Controller is used for control and coordinates each functional part operation;
Arithmetical unit is used to accomplish various arithmetic sum logical operations;
Also comprise:
Be arranged in first clock control module of said instruction storage manager, be used for judging the next clock period, whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory; If do not have, then forbid that in the next clock period clock signal exports said command memory to;
Said instruction storage manager also comprises:
Caching management module is used to judge whether the memory capacity of said data buffer is full, if full, then ends to send the access request of pointing to said command memory.
Preferably, described CPU also comprises:
Be arranged in the second clock control module of said data storage manager, be used for judging the next clock period, whether the access request to said data-carrier store is arranged; If have, then at next clock period clock signal to said data-carrier store, otherwise, forbid that in the next clock period clock signal exports said data-carrier store to.
The embodiment of the invention also discloses a kind of method of the CPU of reduction power consumption, this CPU comprises command memory, and described method comprises:
Receive the access request of pointing to said command memory;
Judge in the next clock period whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory; And from said command memory, take out the pairing instruction of said access request, write in the data buffer of instruction fetch unit;
If do not have, then forbid that in the next clock period clock signal exports said command memory to;
Described method also comprises:
Whether the memory capacity of judging said data buffer is full, if full, then ends to send the access request of pointing to said command memory.
Preferably, said CPU also comprises data-carrier store, and described method also comprises:
Receive the access request of pointing to said data-carrier store;
Judge in next clock period whether the access request to said data-carrier store is arranged;
If have, then at next clock period clock signal to said data-carrier store, otherwise, forbid that in the next clock period clock signal exports said data-carrier store to.
Compared with prior art, the present invention has the following advantages:
The inventor of this patent has selected order set to improve from whole C PU device; To the cpu instruction memory device; In cpu chip, increase controller clock signal; When identifying the access request that do not have the directional order memory device or access request and ended maybe can not be performed for various reasons, stop to provide clock signal to this instruction storage device.Because in COMS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor (CMOS)) circuit, dynamic power consumption is directly proportional with clock; Stop to provide clock signal so carve at one's leisure, just can remove the energy consumption of instruction storage device this moment, the ratio that accounts for whole C PU device power consumption owing to the power consumption of cpu instruction system is higher, so the present invention can reduce the CPU device power consumption preferably.
Description of drawings
Fig. 1 is the structural drawing of a kind of cpu instruction system embodiment 1 of the present invention;
Fig. 2 is the structural drawing of a kind of cpu instruction system embodiment 2 of the present invention;
Fig. 3 is the structural drawing of a kind of CPU device embodiment 1 of the present invention;
Fig. 4 is the structural drawing of a kind of CPU device embodiment 2 of the present invention;
Fig. 5 is the process flow diagram of the method embodiment 1 of a kind of CPU of reduction power consumption of the present invention;
Fig. 6 is the process flow diagram of the method embodiment 2 of a kind of CPU of reduction power consumption of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing and embodiment the present invention done further detailed explanation.
In fact the process that cpu instruction is carried out is exactly the cyclic process of taking out instruction, analysis instruction and execution command.Particularly; When CPU carries out an instruction, get the instruction fetch unit to it from command memory earlier, for improving the efficient that instruction is carried out; The instruction of data buffer with this required execution of buffer memory is set in the said instruction fetch unit; In this case, will instruct and get the data buffer, promptly accomplish the process of instruction fetch from command memory.Then, the instruction fetch unit can be deciphered or test order code, and produces corresponding operating control signal, so that start specified action.Such as an internal memory read/write operation, an arithmetic logical operation operation, or an I/O operation etc.
For cpu instruction is taken out from command memory; Generally need be by CPU clock signal (Clock Signal) to command memory; Clock signal normally is made up of the square wave of one-period property, i.e. every (time cycle) pulsed electric signal of sending at interval at regular intervals.In the prior art, because instruction execution frequency is higher, thereby clock signal is continued to be carried on the instruction storage device; But in reality; A kind of situation that possibly occur does, the current instruction that need not carry out does not promptly produce the access request of directional order memory device; If at this moment still clock signal to command memory, the power consumption of obviously too wasting CPU.
In addition, under the situation that adopts data buffer, a kind of situation that also might occur does; Since buffer memory finite capacity (being generally the instruction of storage 4-8 bar), when the memory capacity of data buffer has expired, then need be after executing an instruction in the data buffer; Could continue from command memory, to take out next bar instruction, at this moment, even produced the access request of directional order memory device; On command memory, load clock signal, but the instruction fetch operation meeting produces mistake; And the memory capacity that need wait until data buffer is when having residue, and this instruction fetch operation just is achieved.Obviously,, still produce the clock signal of access request and lasting load instructions storer, also can cause the power consumption of CPU excessive if in the term of execution of long instruction.
In brief; In the instruction fetch process, in the current access request that does not have the directional order memory device, or this access request is when being ended maybe can not to be performed for various reasons; If the clock signal and the data enable signal of this instruction storage device all are effective; Promptly this moment, this instruction storage device was at the energy that consumes CPU, that is to say that this instruction storage device just is in the state of power wastage.
Inventor just because of this patent has noticed this point; Therefore; One of core idea of the proposition embodiment of the invention of novelty: to the cpu instruction memory device; In cpu chip, increase controller clock signal, when identifying the access request that do not have the directional order memory device or access request and ended maybe can not be performed, stop to provide clock signal to this instruction storage device.Because in COMS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor (CMOS)) circuit, dynamic power consumption is directly proportional with clock; Stop to provide clock signal so carve at one's leisure, just can remove the energy consumption of instruction storage device this moment, to reach the purpose that reduces power consumption.
With reference to figure 1, show the structural drawing of a kind of cpu instruction system embodiment 1 of the present invention,
Specifically can comprise:
Instruction fetch unit 103 is used for reading from command memory through said instruction storage manager the instruction of required execution;
Said cpu instruction system also comprises:
The important improvement part of present embodiment just is in instruction storage manager, to have increased clock control module.In the present embodiment, instruction storage manager is used to manage the access request of pointing to said command memory; Concrete; When the clock control module of instruction storage manager was judged in the next clock period; When the access request that is directed against said command memory is arranged; Then, the pairing instruction of said access request can be taken out from command memory, and write in the data buffer of instruction fetch unit at next clock period clock signal to said command memory; When said clock control module judgement is directed against the access request of said command memory in the next clock period; For example; The instruction that need not carry out, perhaps, the visit that causes is for various reasons ended; The situation that instruction can't be carried out forbids that then clock signal exports said command memory to.Simple situation is exactly in reality, to command memory, has line to introduce clock signal, and control this line and close, the input of interrupt clock signal, thus remove the energy consumption of instruction storage device at this moment, can reach the effect that reduces power consumption.
In concrete the realization, when the memory capacity of data buffer has expired,, but still can't this instruction be got in the data buffer in fact even produced the access request of directional order memory device; That is to say that the access request of this moment does not produce effect, should be ended.In view of this design, with reference to figure 2, the present invention proposes a kind of structural drawing of cpu instruction system embodiment 2, specifically can comprise:
Instruction fetch unit 203 is used for reading from command memory through said instruction storage manager the instruction of required execution;
Wherein, said instruction storage manager 202 also comprises:
The important improvement part of present embodiment just is in instruction storage manager, to have increased clock control module and caching management module.In the present embodiment, instruction storage manager is used to manage the access request of pointing to said command memory; Concrete; When the clock control module of instruction storage manager was judged in the next clock period; When the access request that is directed against said command memory is arranged; Then, the pairing instruction of said access request can be taken out from command memory, and write in the data buffer of instruction fetch unit at next clock period clock signal to said command memory; When said clock control module judgement is directed against the access request of said command memory in the next clock period; Comprise when having expired by the memory capacity of caching management module judgment data buffer; The situation of the access request of pointing to said command memory is sent in termination, forbids that then clock signal exports said command memory to.Simple situation is exactly in reality, to command memory, has line to introduce clock signal, and control this line and close, the input of interrupt clock signal, thus remove the energy consumption of instruction storage device at this moment, can reach the effect that reduces power consumption.
Certainly, those skilled in the art are ended according to the visit that various reasons in the reality causes, and the access request that the situation equipment corresponding module that instruction can't be carried out sends the directional order storer with termination all is feasible, and the present invention need not this to limit.
In a kind of preferred embodiment of the present invention, said data buffer can be FIFO (FirstInput First Output, first in first out) data buffer.This data buffer employing writes data in proper order, calls over the mode of data, and its data address adds 1 automatically by the internal read write pointer and accomplishes; When FIFO is full maybe will expire the time, the signal that the status circuit of FIFO can be seen off continues write data in FIFO and causes and overflow (overflow) with the write operation that stops FIFO; And empty or will be empty the time as FIFO, the signal that the status circuit of FIFO can be seen off continues sense data from FIFO and causes read (underflow) of invalid data with the read operation that stops FIFO.
In embodiments of the present invention, preferred, when said clock control module control clock signal exported command memory to, the data enable signal that clock control module also is used to control to this command memory was an effective status; Promptly when access request is arranged, guarantee that clock signal and the data enable signal to command memory all is effective.
When said clock control module forbade that clock signal exports command memory to, the data enable signal that clock control module also is used to control to this command memory was a disarmed state; Promptly when not having access request, guarantee that clock signal and the data enable signal to this command memory all is invalid.
In concrete the realization; Said command memory can be Cache (cache memory) or TCM (tight coupling physical store module); TCM is the RAM (RandomAccess Memory random memory) of a fixed size, closely is coupled to CPU core, and the performance suitable with cache is provided.Certainly, it all is feasible that those skilled in the art select any memory device according to actual needs for use, and the present invention need not this to limit.
With reference to figure 3, show the structural drawing of a kind of CPU device embodiment 1 of the present invention, specifically can comprise:
Data-carrier store 301 is used to store data;
Instruction fetch unit 305 is used for reading from command memory through said instruction storage manager the instruction of required execution;
This CPU device also comprises:
Be arranged in first clock control module 3041 of said instruction storage manager 304, be used for judging the next clock period, whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory 303; If do not have, then forbid that in the next clock period clock signal exports said command memory to.
As another preferred embodiment of the present invention, said instruction storage manager 304 can also comprise:
As another preferred embodiment of the present invention, said data storage manager 302 can also comprise: second clock control module 3021, be used for judging the next clock period, and whether the access request to said data-carrier store is arranged; If have, then at next clock period clock signal to said data-carrier store 302, otherwise, forbid that in the next clock period clock signal exports said data-carrier store to.
What embodiment shown in Figure 3 adopted is Harvard architecture; With data and instruction separate storage with call, promptly CPU comprises data channel (data-carrier store 301 with data storage manager 302) and instruction path (command memory 303 and instruction storage manager 304).
In the present embodiment, data storage manager is used to manage the access request of pointing to said data-carrier store.Concrete; Data storage manager receives access request, at first judges according to these requests it points to which data-carrier store in the cpu data storer, if there are a plurality of access request to compete same storer; Then arbitrate, find out the highest access request of priority; The highest visit of processing priority afterwards conducts interviews (comprising read) to this storer.Judge in the next clock period when the second clock control module of data storage manager, when the access request to said data-carrier store is arranged, then at next clock period clock signal to said data-carrier store; Otherwise forbid that clock signal exports said data-carrier store to; Simple situation is exactly in reality, to data-carrier store, has line to introduce clock signal; Controlling this line closes; The input of interrupt clock signal, thus the energy consumption of data storage device at this moment removed, can reach the effect that reduces power consumption.
CPU device shown in Figure 3 can be applied in the various embedded system developments.For example, it can be applied in the ARM embedded system, and the ARM architecture is the CPU of RISC (compacting instruction set processor) structure.Certainly, the present invention is not limited to risc architecture, and CISC (complicated order set processor) also is feasible.
In the ARM embedded system; Data storage manager (MMU, Memory ManagementUnit) can be accomplished the mapping (because in ARM, having adopted the page virtual memory management) to amount of physical memory of control and the virtual memory space of memory access authority.Can receive all access request just because of data storage manager to data-carrier store; And have abilities such as control of authority, arbitration management; So based on these information; In data storage manager, increase a functional module, just can realize clock signal control function to each data-carrier store.
Preferably, when the said first clock control module control clock signal exported command memory to, the data enable signal that said first clock control module also is used to control to this command memory was an effective status; Promptly when access request is arranged, guarantee that clock signal and the data enable signal to command memory all is effective.
When said first clock control module forbade that clock signal exports command memory to, the data enable signal that said first clock control module also is used to control to this command memory was a disarmed state; Promptly when not having access request, guarantee that clock signal and the data enable signal to this command memory all is invalid.
When said second clock control module control clock signal exported data-carrier store to, the data enable signal that said second clock control module also is used to control to this data-carrier store was an effective status; Promptly when access request is arranged, guarantee that clock signal and the data enable signal to data-carrier store all is effective.
When said second clock control module forbade that clock signal exports data-carrier store to, the data enable signal that said second clock control module also is used to control to this data-carrier store was a disarmed state; Promptly when not having access request, guarantee that clock signal and the data enable signal to this data-carrier store all is invalid.
With reference to Fig. 4, show the structural drawing of a kind of CPU device embodiment 2 of the present invention, it adopts present stage risc architecture realization relatively more commonly used.
The difference of RISC and CISC (complicated order set processor) is: RISC needn't be provided with microprogram control memory as CISC, can lead to shirtsleeve operation (for example, generally only getting final product through Load and Store operational access) and accomplish the instruction execution.General, the memory address of visiting in every instruction can not surpass 1, and the operation of access memory can not mix with arithmetical operation, and most of instruction can be accomplished in a clock period; And, can realize the parallel work-flow of instructing through adopting the instruction pipelining operation.It all is feasible that the present invention adopts above-mentioned two kinds of structures.
CPU embodiment shown in Figure 4, its structure member is more detailed, specifically can comprise:
Data-carrier store 401 is used to store data;
Command memory 402 is used for storage instruction;
Data storage manager 403 is used to manage the access request of pointing to said data-carrier store;
Instruction storage manager 404 is used to manage the access request of pointing to said command memory; And from command memory 402, take out corresponding instruction according to said access request, write in the data buffer 4051 of instruction fetch unit 405;
Instruction fetch unit 405 is used for reading the instruction of required execution through instruction storage manager 404 from command memory 402, and puts into data buffer 4051; Said instruction fetch unit can also be used for instruction is deciphered or tested, and produces corresponding operating control signal, so that start specified action;
Data buffer 4051 is arranged in said instruction fetch unit, is used for the said instruction that needs execution of buffer memory;
Load/Store parts 406 are used to send loading or storage instruction, read or write required data through data storage manager 303 from data-carrier store 301;
Arithmetic unit 407 is used to accomplish various arithmetic sum logical operations; Performed computing meeting and the instruction of required execution and/or the data of being read and write are relevant;
Control assembly 408 is used for control and coordinates each functional part operation; Because controller is the basic element of character in the CPU device, belong to the technology of knowing of this area, and its function can change along with the variation of miscellaneous part.The present invention does not almost improve this, so just repeated no more at this;
This CPU device also comprises:
Be arranged in first clock control module 4041 of said instruction storage manager 404, be used for judging the next clock period, whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory 303; If do not have, then forbid that in the next clock period clock signal exports said command memory to.
Be arranged in the caching management module 4042 of said instruction storage manager 404, be used to judge whether the memory capacity of said data buffer is full,, then end to send the access request of pointing to said command memory if full.
Be arranged in the second clock control module 4031 of said data storage manager 403, be used for judging the next clock period, whether the access request to said data-carrier store is arranged; If have, then at next clock period clock signal to said data-carrier store, otherwise, forbid that in the next clock period clock signal exports said data-carrier store to.
Embodiment shown in Figure 4 also comprises instruction bus 410 and data bus 411, and the access request of said directional order storer can be sent to instruction storage manager through instruction bus 410 for the CPU external unit; The access request of the said data-carrier store of said sensing can be sent to data storage manager through data bus 411 for the CPU external unit.For example, for DMA (DirectMemory Access, direct memory access (DMA)), it can temporarily take data bus, directly sends the access request to data-carrier store to data storage manager.Certain said instruction bus and data bus this two only are logical partitionings, and in fact, if the bus time-sharing multiplex, the two is same physically.
Certainly, the access request for pointing to said data-carrier store also has a kind of situation to be, initiates by CPU is inner, then in risc architecture, all can send to data storage manager through loading Load/ storage Store parts.Accomplish corresponding read-write operation by data storage manager then,, then call arithmetic unit and accomplish and get final product if relate to computing.Access request can comprise usually: address information, the control information of read or write; For write operation, can also comprise the required data that write.
In fact, because CPU inner structure more complicated, segmentation is gone down and is also had the place that does not much relate to, but because its most function can belong to controller, so the present invention has not just detailed one by one.For example, can go round and begin again, carry out down without any confusion for guaranteeing instruction, CPU must use instruction counter to guarantee when executing present instruction, can know the address of next bar instruction.Instruction counter work divides two kinds of situation usually, and the one, order is carried out, and the 2nd, shift and carry out.Before program begins to carry out, the start address of program is sent into instruction counter.When execution command, instruction fetch unit or controller are with the content of automatic modify instruction counter, so that make the address of next the bar instruction that always will carry out of its maintenance.Because the great majority instruction is all carried out in order, gets final product so the process of revising just simply adds 1 usually.When running into transfer instruction such as JMP and instruct; The address of successor instruction (being the content of instruction counter) can not be as obtaining in order usually; But add a displacement addition of shifting forward or backward according to the address of present instruction with obtain, the address of the direct transfer that perhaps provides according to transfer instruction obtains.
Since between data-carrier store and CPU, exist the differentiation on the operating speed, thus possibly also need use address register to keep address information, till the read/write operation of internal memory is accomplished.And address wire and data line great majority are time-sharing multiplexs, so want also that addressed memory is temporary transient preserves relevant address date.When CPU and data-carrier store carry out message exchange (reading and writing data), all to use address register.
With reference to figure 5, show the process flow diagram of the method embodiment 1 of a kind of CPU of reduction power consumption of the present invention, this CPU comprises command memory, specifically can comprise:
The access request of said command memory is pointed in step 501, reception;
With reference to figure 6, show the process flow diagram of a kind of method embodiment 2 of the CPU of reduction power consumption, this CPU comprises command memory, specifically can comprise:
The access request of said command memory is pointed in step 601, reception;
Step 606, termination are sent the access request of pointing to said command memory, and are jumped to step 603.
In reality, said CPU device can also comprise data-carrier store, and in this case, the embodiment of the invention preferably can also may further comprise the steps:
Receive the access request of pointing to said data-carrier store;
Judge in next clock period whether the access request to said data-carrier store is arranged;
If have, then at next clock period clock signal to said data-carrier store, otherwise, forbid that in the next clock period clock signal exports said data-carrier store to.
Preferably, in embodiments of the present invention, when control clock signal exports said command memory to, also comprise: control is effective status to the data enable signal of this command memory; When forbidding that clock signal exports said command memory to, also comprise: control is disarmed state to the data enable signal of this command memory.
In a word, be able to smooth execution for guaranteeing instruction, in the prior art, the clock signal in any moment and data enable signal all are constant effective, thereby the power consumption of CPU is bigger.Only consider to reduce the CPU power consumption and those skilled in the art are general from the angle that changes the instruction execution priority; Promptly under the condition of same CPU power consumption; How to execute instruction as much as possible; Thereby improve the utilization factor of CPU, reduce the CPU power consumption indirectly, this design often needs all order set to be made more greatly, more complicatedly changed.And the present invention looks for another way, and has directly reduced the power consumption of data storage device, and is minimum to the change of CPU structure and operational process, reached the purpose that reduces the CPU power consumption also.
Need to prove; For aforesaid each method embodiment, for simple description, so it all is expressed as a series of combination of actions; But those skilled in the art should know; The present invention does not receive the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in the instructions all belongs to preferred embodiment, and related action and module might not be that the present invention is necessary.
In addition, each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
More than the method for a kind of CPU provided by the present invention, a kind of cpu instruction system and a kind of CPU of reduction power consumption has been carried out detailed introduction; Used concrete example among this paper principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.
Claims (7)
1. a cpu instruction system is characterized in that, comprising:
Command memory is used for storage instruction;
Instruction storage manager is used to manage the access request of pointing to said command memory; And from command memory, take out corresponding instruction according to said access request, write in the data buffer of instruction fetch unit;
The instruction fetch unit is used for reading from command memory through said instruction storage manager the instruction of required execution;
Data buffer is arranged in said instruction fetch unit, is used for the said instruction that needs execution of buffer memory;
Also comprise:
Clock control module is arranged in said instruction storage manager, is used for judging the next clock period, and whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory; If do not have, then forbid that in the next clock period clock signal exports said command memory to;
Said instruction storage manager also comprises:
Caching management module is used to judge whether the memory capacity of said data buffer is full, if full, then ends to send the access request of pointing to said command memory.
2. cpu instruction as claimed in claim 1 system is characterized in that,
When said clock control module control clock signal exported command memory to, the data enable signal that clock control module also is used to control to this command memory was an effective status;
When said clock control module forbade that clock signal exports command memory to, the data enable signal that clock control module also is used to control to this command memory was a disarmed state.
3. cpu instruction as claimed in claim 2 system is characterized in that said data buffer is the data fifo buffer.
4. a CPU is characterized in that, comprising:
Data-carrier store is used to store data;
Data storage manager is used to manage the access request of pointing to said data-carrier store;
Command memory is used for storage instruction;
Instruction storage manager is used to manage the access request of pointing to said command memory; And from command memory, take out corresponding instruction according to said access request, write in the data buffer of instruction fetch unit;
Controller is used for control and coordinates each functional part operation;
Arithmetical unit is used to accomplish various arithmetic sum logical operations;
Also comprise:
Be arranged in first clock control module of said instruction storage manager, be used for judging the next clock period, whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory; If do not have, then forbid that in the next clock period clock signal exports said command memory to;
Said instruction storage manager also comprises:
Caching management module is used to judge whether the memory capacity of said data buffer is full, if full, then ends to send the access request of pointing to said command memory.
5. CPU as claimed in claim 4 is characterized in that, also comprises:
Be arranged in the second clock control module of said data storage manager, be used for judging the next clock period, whether the access request to said data-carrier store is arranged; If have, then at next clock period clock signal to said data-carrier store, otherwise, forbid that in the next clock period clock signal exports said data-carrier store to.
6. method that reduces the CPU power consumption, this CPU comprises command memory, it is characterized in that, described method comprises:
Receive the access request of pointing to said command memory;
Judge in the next clock period whether the access request to command memory is arranged; If have, then at next clock period clock signal to said command memory; And from said command memory, take out the pairing instruction of said access request, write in the data buffer of instruction fetch unit;
If do not have, then forbid that in the next clock period clock signal exports said command memory to;
Said method also comprises:
Whether the memory capacity of judging said data buffer is full, if full, then ends to send the access request of pointing to said command memory.
7. method as claimed in claim 6, this CPU also comprises data-carrier store, it is characterized in that, also comprises:
Receive the access request of pointing to said data-carrier store;
Judge in next clock period whether the access request to said data-carrier store is arranged;
If have, then at next clock period clock signal to said data-carrier store, otherwise, forbid that in the next clock period clock signal exports said data-carrier store to.
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| CN106815155A (en) * | 2015-12-01 | 2017-06-09 | 英飞凌科技奥地利有限公司 | Data are accessed via different clocks |
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| US8347132B2 (en) * | 2009-01-07 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for reducing processor power consumption |
| US9824056B2 (en) | 2009-11-05 | 2017-11-21 | Rambus Inc. | Handshake signaling for interface clock management |
| TWI581092B (en) * | 2016-03-30 | 2017-05-01 | 威盛電子股份有限公司 | Memory apparatus and energy-saving controlling method thereof |
| CN108052458A (en) * | 2017-12-21 | 2018-05-18 | 中国电子科技集团公司第四十七研究所 | A kind of Cache dynamic configuration devices and method based on application |
| CN116627865B (en) * | 2023-04-26 | 2024-02-06 | 安庆师范大学 | Method and device for accessing computer with multiple storage devices |
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| CN1688965A (en) * | 2002-10-11 | 2005-10-26 | 皇家飞利浦电子股份有限公司 | VLIW processor with power saving |
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| CN106815155A (en) * | 2015-12-01 | 2017-06-09 | 英飞凌科技奥地利有限公司 | Data are accessed via different clocks |
| CN106815155B (en) * | 2015-12-01 | 2019-12-13 | 英飞凌科技奥地利有限公司 | Accessing data via different clocks |
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