CN112835842B - Terminal sequence processing method, circuit, chip and electronic terminal - Google Patents
Terminal sequence processing method, circuit, chip and electronic terminal Download PDFInfo
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Abstract
The embodiment of the application provides an end sequence processing method, a circuit, a chip and an electronic device, wherein the end sequence processing method is applied to an end sequence processing circuit, the end sequence processing circuit is positioned outside a data access unit, the end sequence processing circuit acquires source data from a memory, the data access unit acquires target data from the end sequence processing circuit, and the end sequence processing method comprises the following steps: determining an end-sequence processing mode for processing the source data into the target data; determining the data access width when the data access unit acquires the target data; and carrying out end-sequence processing on the source data according to the data access width and the end-sequence processing mode to obtain the target data. The embodiment of the application performs the end sequence processing on the end sequence processing circuit outside the data access unit, so that the data access unit does not need to use an extra clock cycle to execute the end sequence processing, thereby reducing the consumption of the clock cycle of the data access unit.
Description
Technical Field
The embodiment of the application relates to the technical field of circuits, in particular to an end sequence processing method, a circuit, a chip and an electronic terminal.
Background
In various application scenarios, such as smart wristband/watch swipe display, or a large amount of fragmented access, the data access unit on the chip needs to perform an endian conversion process to access the external memory to obtain the target data. The endian conversion process is implemented in the data access unit based on the software layer, which results in that the data access unit needs to use an additional instruction cycle to execute the endian conversion process, resulting in a larger consumption of clock cycles.
Disclosure of Invention
Accordingly, one of the technical problems to be solved by the embodiments of the present application is to provide an end sequence processing method, a circuit, a chip and an electronic device, which are used for overcoming or alleviating the above-mentioned drawbacks in the prior art.
In a first aspect, an embodiment of the present application provides an endian processing method, applied to an endian processing circuit, where the endian processing circuit is located outside a data access unit, the endian processing circuit obtains source data from a memory, and the data access unit obtains target data from the endian processing circuit, where the endian processing method includes:
determining an end-sequence processing mode for processing the source data into the target data;
Determining the data access width when the data access unit acquires the target data;
and carrying out end-sequence processing on the source data according to the data access width and the end-sequence processing mode to obtain the target data.
Optionally, in an embodiment of the present application, performing the end processing on the source data to obtain the target data according to the data access width and the end processing mode includes:
Determining an endian processing logic according to the data access width and the endian processing mode;
and carrying out end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data.
Optionally, in an embodiment of the present application, the endian processing logic is at least one of 4-byte endian processing logic, 2-byte endian processing logic, and single-byte endian processing logic.
Optionally, in an embodiment of the present application, if the data access width of the data access unit when obtaining the target data is a single byte, the endian processing circuit obtains the data access width of the source data from the memory to be a single byte;
And performing end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data, including: and according to the single-byte endian processing logic, endian processing is carried out on the source data to obtain the target data, so that the endian of the target data is the same as the endian of the source data.
Optionally, in an embodiment of the present application, if the data access width of the data access unit when obtaining the target data is 2 bytes, the endian processing circuit obtains the data access width of the source data from the memory to be 2 bytes;
And performing end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data, including: and according to the 2-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 2 bytes in the target data is the same as or opposite to the endian between 2 bytes in the source data.
Optionally, in an embodiment of the present application, if the data access width of the data access unit when obtaining the target data is 4 bytes, the endian processing circuit obtains the data access width of the source data from the memory to be 4 bytes;
And performing end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data, including: and according to the 4-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 4 bytes in the target data is the same as or opposite to the endian between 4 bytes in the source data, or the endian between the first 2 bytes in the target data is opposite to the endian between the first 2 bytes in the source data, and the endian between the last 2 bytes in the target data is opposite to the endian between the last 2 bytes in the source data.
Optionally, in an embodiment of the present application, the determining an endian processing mode for processing the source data into the target data includes: and determining an end sequence processing mode for processing the source data into the target data according to the mode variable value acquired from the end sequence processing mode configuration register.
Optionally, in an embodiment of the present application, the number of the endian processing modes is plural, and correspondingly, a plurality of endian processing mode identifiers are stored in the endian processing mode configuration register, and one endian processing mode identifier has one mode variable value, so that one mode variable value corresponds to one endian processing mode.
Optionally, in an embodiment of the present application, the determining the source data to be processed into the target data includes: and according to the endian processing configuration data, configuring the mode variable value corresponding to each endian processing mode in the endian processing mode configuration register.
Optionally, in an embodiment of the present application, the endian processing mode configuration register is configured on the data access unit.
Optionally, in an embodiment of the present application, the memory is a memory supporting a serial peripheral interface of a 4-wire operation mode, and the source data is transferred to the end-sequence processing circuit through the serial peripheral interface.
Optionally, in an embodiment of the present application, before the determining to process the source data into the endian processing mode of the target data, the determining includes: and judging whether the memory is in a memory mapping mode, if so, determining an end sequence processing mode for processing the source data into the target data.
Optionally, in an embodiment of the present application, the data access unit includes at least one of a central processing unit, a micro control unit, and a direct memory access controller.
In a second aspect, an embodiment of the present application provides an endian processing circuit, where the endian processing circuit is located outside a data access unit, where the endian processing circuit obtains source data from a memory, and where the data access unit obtains target data from the endian processing circuit, where the endian processing circuit is configured to execute the endian processing method according to any one of the embodiments of the present application to perform endian processing on the source data to obtain the target data.
In a third aspect, an embodiment of the present application provides a chip, including: the terminal sequence processing circuit is located outside the data access unit, the terminal sequence processing circuit obtains source data from the memory, the data access unit obtains target data from the terminal sequence processing circuit, and the terminal sequence processing circuit is used for executing the terminal sequence processing method according to any embodiment of the application to conduct terminal sequence processing on the source data to obtain the target data.
In a fourth aspect, an embodiment of the present application provides an electronic terminal, which includes the chip according to any one of the embodiments of the present application.
The endian processing scheme provided by the embodiment of the application is applied to an endian processing circuit, the endian processing circuit is positioned outside a data access unit, the endian processing circuit obtains source data from a storage device, the data access unit obtains target data from the endian processing circuit, and the endian processing method comprises the following steps:
Determining an end-sequence processing mode for processing the source data into the target data; determining the data access width when the data access unit acquires the target data; and according to the data access width and the endian processing mode, performing endian processing on the source data to obtain the target data, namely performing endian processing on an endian processing circuit outside the data access unit, so that the data access unit does not need to use an extra clock cycle to perform endian processing, and the consumption of the clock cycle of the data access unit is reduced.
Drawings
Some specific embodiments of the application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the accompanying drawings:
FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of an end sequence processing method according to an embodiment of the application;
FIG. 3 is a schematic flow chart of an end sequence process according to an embodiment of the present application;
Fig. 4 is a schematic diagram of another application scenario according to an embodiment of the present application;
fig. 5 is a flow chart of the end sequence processing method for the application scenario of fig. 4 according to the present application.
Detailed Description
It is not necessary for any of the embodiments of the application to be practiced with all of the advantages described above.
In order to better understand the technical solutions in the embodiments of the present application, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which are derived by a person skilled in the art from embodiments of the application, shall fall within the scope of protection of the embodiments of the application.
The following further describes specific implementations of embodiments of the present application in conjunction with the accompanying drawings of embodiments of the present application.
FIG. 1 is a schematic diagram of an application scenario according to an embodiment of the present application; in this application scenario, as shown in fig. 1, the electronic terminal includes a chip and a memory, where the chip includes a data access unit and an endian processing circuit, where the endian processing circuit is located outside the data access unit, and the endian processing circuit obtains source data from the memory and performs endian processing on the source data to obtain target data, and the data access unit obtains the target data from the endian processing circuit.
Alternatively, in a specific application, the data access unit may be a CPU (central processing unit ), MCU (micro control unit, microcontroller Unit) or DMA (direct memory access ) controller.
Alternatively, in a specific application, the memory is for example a FLASH device, such as for example a memory of a serial peripheral interface supporting a 4-wire operation mode, or also called QSPI (Quad SERIAL PERIPHERAL INTERFACE, serial peripheral interface for 4-wire operation mode) memory.
In this embodiment, the endian mainly indicates a byte order of the stored data. The endian may also be referred to as endian, and endian. The motifs may include Big motifs (Big-Endian) and small motifs (Little-Endian). In the big endian, the high-order bytes are placed at the low address of the memory and the low-order bytes are placed at the high address of the memory. In the small endian, the low order bytes are placed at the low address of the memory and the high order bytes are placed at the high address of the memory.
In a specific application, the endian processing circuit is a circuit generated by a hardware programming language (VHDL, verilog, etc.), which may be specifically a SoC (System-on-a-Chip) Chip.
In a specific application, the source data is not particularly limited, and may be any data, such as pixel data or picture data or word-matrix data.
Alternatively, in a specific application, the data access width is N times of 8 bits, where N is greater than or equal to 1, such as 8 bits (corresponding to a width of one byte, abbreviated as a single byte), 16 bits (corresponding to a width of 2 bytes, corresponding to a width of half a word, or referred to as half a word), 32 bits (corresponding to a width of 4 bytes, corresponding to a width of one word, or referred to as a single word), and so on. It should be noted here that the data access width of a specific value is merely an example and is not uniquely defined.
FIG. 2 is a schematic flow chart of an end sequence processing method according to an embodiment of the application; as shown in fig. 2, the endian processing method includes:
s201, determining an end sequence processing mode for processing the source data into the target data;
Optionally, in a specific application, the step S201 may specifically include: and determining an end sequence processing mode for processing the source data into the target data according to the mode variable value acquired from the end sequence processing mode configuration register. Optionally, in a specific application, the number of the endian processing modes is multiple, correspondingly, multiple endian processing mode identifiers are stored in the endian processing mode configuration register, and one endian processing mode identifier has one mode variable value, so that one mode variable value corresponds to one endian processing mode, and therefore mutual exclusion relation is formed between mode variable values corresponding to different endian processing modes, and switching of the endian processing modes can be rapidly achieved.
For example, if there are three endian processing modes, respectively Mode0, mode1, mode2, and if the obtained Mode variable value is 0, determining that the endian processing Mode is Mode 0; and if the obtained Mode variable value is 1, determining that the end sequence processing Mode is Mode1, and if the Mode variable value is 2, determining that the end sequence processing Mode is Mode2. Specifically, 3 endian processing Mode identifiers xip_mode_endian_type_0, xip_mode_endian_type_1, xip_mode_endian_type_2 are stored in the endian processing Mode configuration register, when the Mode variable value of xip_mode_endian_type_0 is 0, the corresponding endian processing Mode is considered to be Mode0, and conversely, when the Mode variable value of xip_mode_endian_type_0 is other values, the corresponding endian processing Mode is considered to be xip_mode_endian_type_0 is not considered to be Mode 0; when the Mode variable value of xip_mode_endian_type_1 is 1, then xip_mode_endian_type_1 is considered to be true, then the corresponding endian processing Mode is Mode1, conversely, when the Mode variable value of xip_mode_endian_type_1 is other value, then xip_mode_endian_type_1 is considered to be false, then the corresponding endian processing Mode is not Mode 1; when the Mode variable value of xip_mode_endian_type_2 is 2, xip_mode_endian_type_2 is considered to be true, the corresponding endian processing Mode is Mode2, and conversely, when the Mode variable value of xip_mode_endian_type_2 is other value, xip_mode_endian_type_2 is considered to be false, and the corresponding endian processing Mode is not Mode2. It can be seen that the Mode variable value of xip_mode_endian_type_0 is 0, the Mode variable value of xip_mode_endian_type_1 is 1, and the Mode variable value of xip_mode_endian_type_2 is 2 form mutually exclusive relationships, so that fast and convenient switching among the endian processing Mode0, the endian processing Mode1 and the endian processing Mode2 can be facilitated. Optionally, in a specific application, the endian processing mode configuration register is configured on the data access unit, so that the data access unit can conveniently and quickly obtain a mode variable value from the endian processing mode configuration register and send the mode variable value to the endian processing circuit, so that the endian processing circuit determines an endian processing mode for processing the source data into the target data according to the mode variable value, which is equivalent to building a quick entry for data interaction between the data access unit and the endian processing circuit.
For example, when the data access unit is a CPU, the endian processing mode configuration register is configured on the CPU; when the data access unit is an MCU, the endian processing mode configuration register is configured on the MCU, so that a rapid entry for data interaction between the CPU and the endian processing circuit is built.
Optionally, in a specific application, the determining the source data to be processed into the target data in an end-sequence processing mode includes: according to the endian processing configuration data, the mode variable value corresponding to each endian processing mode is configured in an endian processing mode configuration register, so that the method is convenient to be applicable to specific endian processing modes in different application scenes by changing the mode variable value in the endian processing mode configuration register, or quick switching of the endian processing modes is realized according to different stages of data requirements of a data access unit in the same application scene.
For example, when the Mode variable value of xip_mode_endian_type_0 is configured to be 0, then xip_mode_endian_type_0 is considered to be true, and then the corresponding endian processing Mode is Mode0; when the Mode is required to be switched from Mode0 to Mode 1, modifying the Mode variable value of xip_mode_endian_type_0 to be non-0, and modifying the Mode variable value of xip_mode_endian_type_1 to be 1, considering xip_mode_endian_type_1 to be true, and enabling the corresponding end sequence processing Mode to be Mode 1, so that the fast switching from Mode0 to Mode 1 is realized.
S202, determining the data access width when the data access unit acquires the target data;
S203, according to the data access width and the endian processing mode, performing endian processing on the source data to obtain the target data with the target endian.
Optionally, in a specific application, the memory is a QSPI memory, and the endian processing circuitry obtains source data from the QSPI memory via an AHB (ADVANCED HIGH-performance Bus).
Specifically, fig. 3 is a schematic flow chart of an end sequence process according to an embodiment of the present application; as shown in fig. 3, step S203 may include:
s213, determining an endian processing logic according to the data access width and the endian processing mode;
Optionally, in a specific application, the endian processing logic includes at least one of 4 byte endian processing logic, 2 byte endian processing logic, and single byte endian processing logic, so that when the data access width is 8 bits, 16 bits, and 32 bits, the endian processing is performed on the source data to obtain the requirement of the data access unit for obtaining the target data, for example, when the CPU is based on the ARM structure, most of application scenarios of the CPU can be effectively satisfied, and the CPU can be suitable for most of application scenarios only by configuration once, thereby saving design cost of endian processing.
S223, according to the end sequence processing logic, performing end sequence processing on the source data to obtain the target data.
Optionally, in a specific application, if the data access width of the data access unit when obtaining the target data is a single byte, the endian processing circuit obtains the data access width of the source data from the memory to be a single byte, so as to ensure that the bit width of the source data read from the memory by the endian processing circuit is a single byte each time, and the bit width of the target data read from the endian processing circuit by the data access unit is a single byte, that is, the bit widths of the source data read by the endian processing circuit and the target data read by the data access unit are the same, thereby avoiding the waste of the data access width.
Further, according to the endian processing logic, performing endian processing on the source data to obtain the target data, including: and according to the single-byte endian processing logic, endian processing is carried out on the source data to obtain the target data, so that the endian of the target data is the same as the endian of the source data. For example, when the source data is processed in an endian manner, the endian of the source data is kept unchanged, so that the endian of the target data is the same as the endian of the source data, or the source data is output according to the endian. If the end sequence of the source data is a big end sequence, the end sequence of the target data is also a big end sequence; if the end sequence of the source data is a small end sequence, the end sequence of the target data is also a small end sequence. Specifically, if the source data read from the memory by the endian processing circuit at a time is AA, the source data participating in the one-time endian processing is AA (i.e., the corresponding data access width is single byte), and the target data obtained after the endian processing is AA. If the source data of the next endian processing is BB, the target data obtained after the endian processing is BB.
Optionally, in a specific application, if the data access width of the data access unit when obtaining the target data is 2 bytes, the endian processing circuit obtains the data access width of the source data from the memory to be 2 bytes, so as to ensure that the bit width of the source data read from the memory by the endian processing circuit is 2 bytes each time, and the bit width of the target data read from the endian processing circuit by the data access unit is 2 bytes, that is, the bit widths of the source data read by the endian processing circuit and the target data read by the data access unit are the same, thereby avoiding the waste of the data access width.
Further, according to the endian processing logic, performing endian processing on the source data to obtain the target data, including: and according to the 2-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 2 bytes in the target data is the same as or opposite to the endian between 2 bytes in the source data. For example, when the source data is processed in an endian manner, the endian of the source data is kept unchanged, so that the endian of the target data is the same as the endian of the source data, or the source data is output according to the endian. If the end sequence of the source data is a big end sequence, the end sequence of the target data is also a big end sequence; if the end sequence of the source data is a small end sequence, the end sequence of the target data is also a small end sequence. Specifically, the source data read from the memory by the endian processing circuit at a certain time is AABB, namely, the corresponding data access width is 2 bytes, the source data participating in the one-time endian processing is AABB, and the target data obtained after the endian processing is AABB; if the source data processed by the next end sequence is CCDD, the target data obtained after the end sequence processing is CCDD; it follows that the endianness of the source data and the target data are identical. For example, when the source data is processed in an end-sequence manner, the end-sequence of the source data is processed in an inverse-sequence manner (or end-sequence conversion) so that the end-sequence of the target data is opposite to the end-sequence of the source data, or the source data is output in an inverse-sequence manner. If the end sequence of the source data is a large end sequence, the end sequence of the target data is a small end sequence; if the end sequence of the source data is a small end sequence, the end sequence of the target data is a large end sequence. Specifically, if the source data read from the memory by the endian processing circuit at a certain time is AABB, the source data participating in one-time endian processing is AABB, and the target data obtained after the endian processing is BBAA; if the source data processed by the next endian processing is CCDD, the target data obtained after the endian processing is DDCC, so that the endian of the source data and the target data is opposite.
Optionally, in a specific application, if the data access width of the data access unit when obtaining the target data is 4 bytes, the endian processing circuit obtains the data access width of the source data from the memory to be 4 bytes, so as to ensure that the bit width of the source data read from the memory by the endian processing circuit is 4 bytes each time, and the bit width of the target data read from the endian processing circuit by the data access unit is 4 bytes, that is, the bit widths of the source data read by the endian processing circuit and the target data read by the data access unit are the same, thereby avoiding the waste of the data access width.
Further, according to the endian processing logic, performing endian processing on the source data to obtain the target data, including: and according to the 4-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 4 bytes in the target data is the same as or opposite to the endian between 4 bytes in the source data, or the endian between the first 2 bytes in the target data is opposite to the endian between the first 2 bytes in the source data, and the endian between the last 2 bytes in the target data is opposite to the endian between the last 2 bytes in the source data. For example, when the source data is processed in an endian manner, the endian of the source data is kept unchanged, so that the endian of the target data is the same as the endian of the source data, or the source data is output according to the endian. If the end sequence of the source data is a big end sequence, the end sequence of the target data is also a big end sequence; if the end sequence of the source data is a small end sequence, the end sequence of the target data is also a small end sequence. Specifically, when the source data read from the memory by the endian processing circuit at a certain time is AABBCCDD (i.e., the corresponding data access width is 4 bytes), the source data participating in the one-time endian processing is AABBCCDD, and the target data obtained after the endian processing is also AABBCCDD; if the source data processed by the next end sequence is EEFFGGHH, the target data obtained after the end sequence processing is EEFFGGHH; it follows that the endianness of the source data and the target data are identical. For example, when the source data is processed in the end sequence, the end sequence of the source data is processed in the reverse sequence, so that the end sequence of the target data is opposite to the end sequence of the source data, or the source data is output in the reverse sequence. If the end sequence of the source data is a large end sequence, the end sequence of the target data is a small end sequence; if the end sequence of the source data is a small end sequence, the end sequence of the target data is a large end sequence. Specifically, if the source data read from the memory by the endian processing circuit at a time is AABBCCDD (i.e., the corresponding data access width is 4 bytes), the source data participating in the one-time endian processing is AABBCCDD, and the target data obtained after the endian processing is DDCCBBAA; if the source data processed by the next endian processing is EEFFGGHH, the target data obtained after the endian processing is HHGGFFEE, so that the endian of the source data and the target data are opposite. Or specifically, if the source data read from the memory by the endian processing circuit at a time is AABBCCDD (i.e. the corresponding data access width is 4 bytes), the source data participating in the one-time endian processing is AABBCCDD, and the target data obtained after the endian processing is BBAADDCC; if the source data of the next endian processing is EEFFGGHH, the target data obtained after the endian processing is FFEEHHGG, so that it can be seen that the endian between the first 2 bytes in the target data is opposite to the endian between the first 2 bytes in the source data, and the endian between the last 2 bytes in the target data is opposite to the endian between the last 2 bytes in the source data.
Fig. 4 is a schematic diagram of another application scenario according to an embodiment of the present application; as shown in fig. 4, in this embodiment, the memory is taken as a QSPI memory, for which, the chip includes a QSPI controller in addition to a data access unit and an endian processing circuit, and therefore, the endian processing circuit is preferably disposed in the QSPI controller, so as to reduce difficulty in circuit design. In addition, in fig. 4, source data and target data are transmitted through the AHB, and the above-mentioned endian processing mode configuration register is provided on the data access unit, and an endian processing configuration table is stored on the data access unit. In addition, as described above, three types of endian processing modes are described, which are respectively denoted as Mode0 (for example, also referred to as a first endian processing Mode), mode1 (for example, also referred to as a second endian processing Mode), and Mode2 (for example, also referred to as a third endian processing Mode), and the endian processing modes are described in the following table two.
FIG. 5 is a flow chart of the end sequence processing method for the application scenario of FIG. 4 according to the present application; as shown in fig. 5, it includes:
S501, configuring the mode variable value corresponding to each endian processing mode and endian processing logic corresponding to each endian processing mode in an endian processing mode configuration register according to endian processing configuration data;
in this embodiment, the manner in which the source data is in the QSPI is shown in table one.
List one
In table one, offset address indicates an offset address, SAVED DATA indicates source data stored in each offset address, and the bit width of data stored in each offset address is 8 bits.
In this embodiment, the endian processing configuration data may be specifically represented by an endian processing configuration table, as shown in table two.
Watch II
In table two, AHB Size represents a data access width, HSIZE represents a variable representing the data access width, and if the variable is 8, represents the data access width as 8 bits (i.e., single byte), if the variable is 16 (i.e., 2 bytes), represents the data access width as 16 bits, and if the variable is 32 (i.e., 4 bytes), represents the data access width as 32 bits. 0x00000000, 0x00000001, 0x00000002, 0x00000003 denote an alignment address for realizing alignment of data bits, i.e., data bits of single byte data, data bits of 2 byte data, data bits of 4 byte data. The data access width is 8 bits, and the aligned addresses are 0x 000000000000, 0x00000001, 0x00000002, 0x00000003; the data access width is 16 bits, and the aligned addresses are 0x00000000 and 0x00000002; the data access width is 32 bits, and the aligned addresses are 0x00000000 and 0x00000004.
Referring to the above table two, if the data access width is single byte (i.e. hsize=8), when the source data is processed in an end sequence, the end sequence processing logic corresponding to the end sequence processing modes Mode0, mode1 and Mode2 is single byte end sequence processing logic; if the data access width is 2 bytes (i.e. hsize=16), when the source data is processed in an endian Mode, the endian processing logic corresponding to the endian processing modes Mode0, mode1 and Mode2 is 2 bytes endian processing logic; if the data access width is a single word (i.e., hsize=32), then when the source data is processed in an endian Mode, the endian processing logic corresponding to the endian processing modes Mode0, mode1, mode2 is 4-byte endian processing logic. In particular, the examples of the endian processing logic are described in detail in the above embodiments.
S502, judging whether the memory is in a memory mapping mode;
In this embodiment, the data access unit, the endian processing circuit, and the QSPI memory are all connected through an AHB, so that in order to implement data transmission, the memory may be in a memory mapping mode, so as to implement mapping of a physical address space of the QSPI memory onto the AHB, so that the endian processing circuit may read source data from the QSPI memory.
If yes, go to step S503, otherwise, end. Here, in other embodiments, if it is determined that the memory is not in the memory mapping mode, the process may return to step S502 to perform the re-determination until the memory is in the memory mapping mode.
S503, determining an end sequence processing mode for processing the source data into the target data according to the mode variable value obtained from the end sequence processing mode configuration register;
In this embodiment, 2 bits are provided in the endian processing Mode configuration register to configure the Mode variable value, for example, if the Mode variable value is 0, it indicates that the endian processing Mode is Mode 0; if the Mode variable value is 1, it indicates that the endian processing Mode is Mode 1, and if the Mode variable value is 2, it indicates that the endian processing Mode is Mode 2.
Stored in the endian processing mode configuration register are 3 endian processing mode identifications xip_mode_endian_type_0, xip_mode_endian_type_1, xip_mode_endian_type_2, each of which has one of the mode variable values, as previously described, such that one of the mode variable values corresponds to one of the endian processing modes. When the Mode variable values are 0, 1 and 2, respectively, xip_mode_endian_type_0, xip_mode_endian_type_1 and xip_mode_endian_type_2 are true, respectively, that is, the end sequence processing modes are Mode0, mode1 and Mode2, respectively.
In other embodiments, mode0 may also be set to a default endian processing Mode. When the Mode variable value equal to 1 or 2 does not exist, the endian processing Mode is indicated to be a default endian processing Mode0, and when the Mode variable value equal to 1 or 2 exists, the endian processing Mode is indicated to be not the default endian processing Mode0, and is actually the endian processing Mode1 or Mode2.
S504, determining the data access width when the data access unit acquires the target data;
optionally, in a specific application, different data access width identifiers are configured for different data access widths, that is, the data access width identifiers are mutually exclusive, so that the data access width can be quickly determined according to the value of the data access width identifier. For example, if the data access width is 8 bits, 16 bits, or 32 bits, the configured data access width identifiers are hsize_byte, hsize_half_word, and hsize_word, respectively, and if hsize_byte=1, the data access width is 8 bits, that is, a single byte; if hsize_half_word=1, it indicates that the data access width is 16 bits, i.e., half word; if hsize_word=1, it means that the data access width is 32 bits, i.e., a single word.
S505, determining an endian processing logic according to the data access width and the endian processing mode;
in this embodiment, the description of the endian processing logic is detailed in the above embodiment.
S506, performing end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data;
In the present embodiment, the detailed description of step S506 can be found in the description of the above embodiments. In the above embodiment, the mode variable value can be modified through the register instruction, so that the flexible and convenient switching of the endian processing mode is realized, and the requirements of various application scenes are met.
It should be noted here that the specific values of the above-mentioned endian processing configuration data are merely examples, and are not limited to uniqueness. Such as 64 bits, 128 bits, etc., of data access width. The number of the end sequence processing modes can be more than 3, so that the configuration of various possible end sequence processing modes and end sequence processing logic can be realized in the same end sequence configuration data table, flexible switching can be performed in various scenes, and the cost of end sequence processing design is reduced.
In addition, in the above embodiment, only one memory is described as an example, but it is described herein that there is no limitation on the number and type of memories, i.e., one data access unit may access a plurality of memories of the same or different types, such as QSPI memories, PSRAMs (Pseudo static randomaccess memory, pseudo static random access memories).
The scheme of the present application will be described below with reference to a great reduction in clock consumption, taking as an example an application in a typical scenario.
For example, for the screen brushing of intelligent bracelet/wrist-watch, the picture that the screen brushing used is stored in QSPI memory, and the terminal sequence processing circuit is directly transmitted to the screen and is shown after finishing terminal sequence processing to the source data, is equivalent to P2P transmission, can make design scheme and the software architecture of product become succinct more, has reduced user's development degree of difficulty and development cost, in addition, makes CPU's data calculation and screen brushing processing ability become more powerful. Assuming that the length width color depth of the screen is 454×454×16bits, since 8 bits=1 Bytes, the data amount of 1 screen is 412232Bytes.
If the QSPI memory operates at 48Mhz in a 4-wire mode (i.e., 4bits per SCLK transfers, i.e., 2 clock cycles per byte (also referred to as 2 SCLK)), the maximum theoretical limit speed is 48 x 4/8=24 MByte/Sec.
In addition, assuming that the endian processing circuit reads source data from the QSPI memory, reading 1 byte data is referred to as 1 bean data, and it takes 2 SCLKs.
In addition, in addition to consuming the above 2SCLK, if the endian processing circuit reads the source data from the QSPI memory according to SIOO (Sent Instruction Only Once, only one read command) mode and performs endian processing, the entire clock consumption includes: OVERHEAD clock consumption (also called indirect clock consumption) and read data consumption (also called DATA PHASE consumption), OVERHEAD clock consumption is OVERHEAD SLCK, the number of OVERHEAD SLCK is 14 SCLKs in total, wherein the following are sequentially from front to back in time sequence: 2SCLK (read instruction transfer consumes), 6 SCLK (addressing stage consumes, also known as ADDRESS PHASE consumes), 6 SCLK (waiting stage consumes, also known as Dummy Phase).
(1) Based on the scheme provided by the application, if hsize=8, since 1 bet data is 1 byte data, 4 bet data is read from the QSPI memory, and as described above, since reading one byte data consumes 2sclk,4 byte data is taken together: 4 x2 sclk=8sclk, the clock consumption for data Phase is 8SCLK, since the whole process will consume: OVERHEAD the sum of clock consumption (14 SCLK) and DATA PHASE consumption (4 x2 SCLK), 22SCLK total, then:
the access efficiency was (4*2)/(14+4×2) =36.4%;
the theoretical transmission speed in case of hsize=8 is 24Mbyte/Sec 36.4% =8.73 MB/Sec;
The theoretical time consumption for transmitting a screen data is (412232/(1024×1024)) ×1000/8.73=45 ms.
(2) Based on the scheme provided by the application, if hsize=32, since 1 bet data is 4-Byte data, then reading 4 bet data from the QSPI memory is 16Byte, as described above, since reading one-Byte data consumes 2sclk, 16-Byte data is total: the clock period consumed by 16×2sclk= 32SCLK,Data Phase is 8SCLK,OVERHEAD SLCK for 14 SCLKs, and similar to the calculation method of hsize=8, the whole process is consumed: 14sclk+16 x2 sclk=46 SCLK, then:
The access efficiency was (16×2)/(14+2×16) =69.6%;
The theoretical transmission speed in case of hsize=32 is 24Mbyte/Sec 69.6% =16.7 MB/Sec;
the theoretical time consumption for transmitting a screen data is: (412232/(1024 x 1024)) =1000/16.7=23.5 ms;
As can be seen, the access efficiency is higher when hsize=32 than when hsize=8, and the theoretical time consumption for transmitting one screen of data when hsize=32 is shorter than the theoretical time consumption for transmitting one screen of data when hsize=8. That is, the wider the data access width, the higher the access efficiency, and the shorter the theoretical consumed time for transmitting one screen of data. Here, the case when hsize=16 is omitted.
If hsize=32, the conventional endian processing method (i.e. software layer) performs the endian processing and then swipes the screen to the screen, the conventional endian processing method consumes more time theoretically to complete the data access, compared to the case of implementing hsize=32 in the scheme of the present application, and the detailed analysis is as follows.
Since in the conventional scheme, the source data read from the memory is first buffered to the RAM, and limited by the size of the RAM, the data stored in the mass memory needs to be decomposed into N blocks for storage.
Reading first block data into a RAM, performing end sequence processing on the first block data to obtain corresponding target data, transmitting the corresponding target data to a screen buffer area, and displaying the target data on a screen;
and by pushing, reading in the second block of data, … and the Nth block, sequentially performing end sequence processing to respectively obtain corresponding target data, transmitting the corresponding target data to a screen buffer area, and displaying on a screen until all the data blocks are brushed into the screen for displaying.
Since the total is 16 bytes if 4Beat data is read when the data is read. The process of finishing screen brushing can be decomposed into: reading to RAM, processing end sequence, writing to screen buffer, then:
Read out to the clock period consumed by RAM: 14+4×4×2=46 SCLK (see above examples for details);
clock period consumed by the software layer for end-sequence processing: about 2-3 SCLKs;
writing to the clock period consumed by the screen cache: 4 x 2 = 32SCLK;
the average time for 16-byte processing to complete is about 80SCLK, and the full-screen processing to complete is about (412232/16) 80= 2061160SCLK. (ignoring here the system scheduling, loop processing and call pop time of the software layer).
The minimum theoretical time spent transmitting a screen of data is:
2061160/48000000 = 42.9ms. Wherein 48000000 is the operating frequency of the QSPI memory of 48Mhz.
It can be seen that this 42.9ms is much greater than the 23.5ms mentioned above. In other words, after the scheme of the application is applied, the screen-brushing frame rate of the watch/bracelet is greatly improved, so that the product which can be blocked by the original sliding is not blocked any more, and the sliding effect is smoother.
Therefore, in the above example, there are multiple endian processing modes, and each endian processing mode can provide different endian processing logic, and the corresponding endian processing is completed on the endian processing circuit outside the data access unit, so that the data access unit is not required to waste additional clock cycles to perform data endian processing, thereby saving the clock consumption of the data access unit. In addition, the end sequence processing device is independent of the data access unit to carry out end sequence processing, so that software codes for carrying out end sequence processing are not required to be distributed on the data access unit, the storage space of the data access unit is saved, the software design difficulty of the data access unit is reduced, and the BUG introduced into the data access unit is reduced. Furthermore, the source data can be directly transmitted to the end sequence processing circuit without configuring a RAM for buffering the source data, so that the data access speed and the access efficiency are improved.
Thus, particular embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may be advantageous.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from the other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.
Claims (14)
1. An endian processing method, characterized in that it is applied to an endian processing circuit, where the endian processing circuit is located outside a data access unit, the endian processing circuit obtains source data from a memory, and the data access unit obtains target data from the endian processing circuit, and the endian processing method includes:
determining an end-sequence processing mode for processing the source data into the target data;
Determining the data access width when the data access unit acquires the target data;
according to the data access width and the endian processing mode, performing endian processing on the source data to obtain the target data;
The determining to process the source data into an endian processing mode of the target data includes: determining an endian processing mode for processing the source data into the target data according to the mode variable value obtained from the endian processing mode configuration register;
The number of the endian processing modes is multiple, correspondingly, a plurality of endian processing mode identifiers are stored in the endian processing mode configuration register, one endian processing mode identifier is provided with one mode variable value, so that one mode variable value corresponds to one endian processing mode, and mutual exclusion relations are formed among the mode variable values corresponding to different endian processing modes.
2. The endian processing method according to claim 1, wherein performing endian processing on the source data according to the data access width and the endian processing mode to obtain the target data includes:
Determining an endian processing logic according to the data access width and the endian processing mode;
and carrying out end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data.
3. The endian processing method of claim 2, wherein the endian processing logic is at least one of a 4 byte endian processing logic, a 2 byte endian processing logic, a single byte endian processing logic.
4. The endian processing method according to claim 3, wherein if the data access width at the time of the data access unit acquiring the target data is a single byte, the endian processing circuit acquires the data access width of the source data from the memory as a single byte;
And performing end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data, including: and according to the single-byte endian processing logic, endian processing is carried out on the source data to obtain the target data, so that the endian of the target data is the same as the endian of the source data.
5. The endian processing method according to claim 3, wherein if the data access width at the time of the data access unit acquiring the target data is 2 bytes, the endian processing circuit acquires the data access width of the source data from the memory is 2 bytes;
And performing end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data, including: and according to the 2-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 2 bytes in the target data is the same as or opposite to the endian between 2 bytes in the source data.
6. The endian processing method according to claim 3, wherein if the data access width at the time of the data access unit acquiring the target data is 4 bytes, the endian processing circuit acquires the data access width of the source data from the memory is 4 bytes;
And performing end-sequence processing on the source data according to the end-sequence processing logic to obtain the target data, including: and according to the 4-byte endian processing logic, performing endian processing on the source data to obtain the target data, so that the endian between 4 bytes in the target data is the same as or opposite to the endian between 4 bytes in the source data, or the endian between the first 2 bytes in the target data is opposite to the endian between the first 2 bytes in the source data, and the endian between the last 2 bytes in the target data is opposite to the endian between the last 2 bytes in the source data.
7. The endian processing method of claim 6, wherein the determining to process the source data into an endian processing mode of the target data, previously comprises: and according to the endian processing configuration data, configuring the mode variable value corresponding to each endian processing mode in the endian processing mode configuration register.
8. The endian processing method of claim 1, wherein the endian processing mode configuration register is configured on the data access unit.
9. The endian processing method of any of claims 1-8, characterized in that the memory is a memory supporting a 4-wire mode of operation serial peripheral interface through which the source data is transferred to the endian processing circuitry.
10. The endian processing method of any of claims 1-8, wherein the determining prior to processing the source data into the endian processing mode of the target data comprises: and judging whether the memory is in a memory mapping mode, if so, determining an end sequence processing mode for processing the source data into the target data.
11. The endian processing method of any of claims 1-8, wherein the data access unit comprises at least one of a central processor, a micro control unit, and a direct memory access controller.
12. An endian processing circuit, characterized in that the endian processing circuit is located outside a data access unit, the endian processing circuit obtains source data from a memory, the data access unit obtains target data from the endian processing circuit, and the endian processing circuit is used for executing the endian processing method according to any one of claims 1-11 to perform endian processing on the source data to obtain the target data.
13. A chip, comprising: the terminal sequence processing circuit is located outside the data access unit, the terminal sequence processing circuit obtains source data from a memory, the data access unit obtains target data from the terminal sequence processing circuit, and the terminal sequence processing circuit is used for executing the terminal sequence processing method of any one of claims 1-12 to perform terminal sequence processing on the source data to obtain the target data.
14. An electronic terminal comprising the chip of claim 13.
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