CN1797378A - Method of data interchange by using mode of direct memory access - Google Patents
Method of data interchange by using mode of direct memory access Download PDFInfo
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- CN1797378A CN1797378A CNA2004101025341A CN200410102534A CN1797378A CN 1797378 A CN1797378 A CN 1797378A CN A2004101025341 A CNA2004101025341 A CN A2004101025341A CN 200410102534 A CN200410102534 A CN 200410102534A CN 1797378 A CN1797378 A CN 1797378A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for making data exchange in a direct memory accessing (DMA) mode. And the method determines two data memory spaces by a processor and writes the address of a memory space in a transmission configuration word, a DMA controller uses the memory space appointed by the transmission configuration word to transmit data and sends out an interrupt signal to the processor after completing data transmission, the processor receives the interrupt signal and judges if all data is transmitted: if yes, ending data transmission and otherwise modifying the current memory space address in the transmission configuration word into the address of the other memory space to make data transmission. The invention gives full play to the DMA controller, occupying less processing time of the processor and reducing system power consumption.
Description
Technical field
The present invention relates to a kind of method of exchanges data, relate in particular to a kind of method that adopts the direct memory access mode to carry out exchanges data.
Background technology
The development trend of portable terminal requires portable terminal to have longer stand-by time and littler volume.Longer stand-by time requires portable terminal to satisfy lower power consumption in the design of chip, and software is more simplified, and efficient is higher; Littler volume needs the employed chip of portable terminal microminiaturized more.
The CPU of portable terminal (Central Processing Unit, central processing unit) adopts DMA (DirectMemory Access, the direct memory visit) mode writes and read operation peripheral hardware, dma mode is a kind of high-speed data transmission operation, permission is the direct read data between peripheral hardware and internal memory, promptly not by CPU, only need minimum CPU to intervene, whole data transfer operation carries out under the control of dma controller.CPU is except doing in the beginning of data transmission with when finishing some handle, and CPU can carry out other work in transmission course.Like this, in the most of the time, CPU and input and output all are in the state of parallel work-flow.DMA generally has a plurality of passages independent of each other, allows to carry out different access control, can carry out the DMA transmission of different content, and DMA can carry out data throughput with the speed of cpu clock, has the higher data throughput.
The method that adopts dma mode to carry out exchanges data between peripheral hardware and internal memory mainly contains two kinds at present, respectively it is described below:
First method is: CPU is responsible for configuration and initiates the DMA transmission, and CPU wants independent allocation one block RAM (Random Access Memory, random access memory) space for the data that receive or send.When internal memory sends data to peripheral hardware, be ready to data among the RAM by CPU, and start DMA and move, because the peripheral hardware register is slower to the relative RAM access rate of speed that peripheral hardware sends data, so after DMA had moved data among the RAM, CPU had time enough to be ready to new data to be sent.When internal memory receives the data that peripheral hardware sends, after the space among the RAM is filled, read away data by CPU.Because the speed of the relative RAM access data of speed of peripheral hardware register reception peripheral data is slower,, thereby avoided the covering of data so CPU can attend school away old data when new data arrive.
Technique scheme need take a large amount of RAM, and this is insufferable at the mobile terminal device that is used for price and sensitive power consumption.If the ram space that CPU distributes is bigger, system can read after this section RAM data are full of again, thus the delay that has increased system; If the ram space that CPU distributes is less, then can cause frequent the writing and sense data of CPU, taken the too much CPU processing time, cause the decline of system performance.That adopted in the technique scheme is the RAM of monolithic, covers for fear of data, and when sending, CPU is ready to the new data among the RAM after in the end the data of a RAM are read away and before the new peripheral hardware request comes; When receiving, CPU must attend school away old data when new data arrive, thereby the operating rate of CPU is had certain requirement, has increased the power consumption of system.
Second method is: by the method for hardware logic, use two independently RAM, carry out exchanges data between continual peripheral hardware and the internal memory by ping-pong operation.
Figure 1 shows that and adopt hardware logic to carry out the schematic diagram of ping-pong operation, " ping-pong operation " is a kind of disposal route that is used for data flow con-trol, its treatment scheme is: the data stream that CPU will send to peripheral hardware is assigned to two data buffer modules during with data stream etc. by the input traffic selected cell, the data buffering module can be any memory module, relatively Chang Yong storage unit is DPRAM (Dual Port RAM, dual port RAM), SPRAM (Single Port RAM, single port RAM), FIFO (First In First Out, first in first out) buffer etc.At first buffer circle, the data flow cache of importing is arrived data buffering module 1; At the 2nd buffer circle, switching by the input traffic selected cell, the data flow cache of input is arrived data buffering module 2, simultaneously the 1st cycle data of data buffering module 1 buffer memory passed through the selection of output stream selected cell, deliver to the dataflow computing processing module of peripheral hardware and carry out calculation process; In of the once more switching of the 3rd buffer circle by the input traffic selected cell, the data flow cache of input is arrived data buffering module 1, simultaneously the data in the 2nd cycle of data buffering module 2 buffer memorys are switched by the output stream selected cell, deliver to the dataflow computing processing module of peripheral hardware and carry out calculation process, so circulation.The maximum characteristics that adopt this method to carry out exchanges data are to reduce the time-delay of system.
Said method two is to adopt hardware logic to finish, therefore can't realize on-the-fly modifying of DMA moving data size and configuration information, for some application in the mobile communication, the data volume size of the every frame of possibility is also inequality, and hardware logic can't be applicable to this situation, and special in some general Peripheral Interface, the data rate difference of interface is very big, and method two can only provide the ram space of fixed size to move use for DMA, thereby has reduced the efficient of system.
Summary of the invention
The object of the present invention is to provide a kind of method that adopts the direct memory access mode to carry out exchanges data, to solve in the prior art when the carrying out exchanges data time-delay of system and power consumption is big, configuration information can't on-the-fly modify problem.
For addressing the above problem, the invention provides following technical scheme:
A kind of method that adopts the direct memory access mode to carry out exchanges data comprises step:
A, determine two blocks of data storage spaces, and wherein the address of a storage space writes the transmission configuration word by processor;
B, direct memory access controller utilize the storage space of transmission configuration word appointment to carry out data and transmit, and send look-at-me to processor after transmission finishes;
When C, processor receive described look-at-me, judge whether all data transmit to finish, if then finish, otherwise, memory space address current in the transmission configuration word is revised as another piece memory space address, change step B.
Described step C may further comprise the steps:
It is the interruption which direct memory access path triggers that C1, processor analyze, and judges whether loading error occurring of passage according to the state of the status register of this passage, and in this way, the end of transmission (EOT) of direct memory access path is not as being commentaries on classics step C2;
C2, processor judge whether current transmission is last transmission, and in this way, end of transmission (EOT) as not being, is revised as another piece memory space address with current memory space address, change step B.
The equal and opposite in direction of two storage spaces selecting for use in the described steps A, its space size determined by the slot time that interrupt to take place and the data volume of every time slot, and the slot time that interrupts generation is to round behind the ratio of duration of interrupt service routine and every time slot duration.
The duration t of described interrupt service routine
IsrNeed meet the following conditions simultaneously:
A, t
Isr≤ t
Trs, t wherein
TrsFor being assigned to the delay on the data transmission;
B, (t
Isr+ t
Isrrun) * s
Data* 2≤m
Data, t wherein
IsrrunBe the switching time of interrupt service routine execution and system task, s
DataBe the transfer rate of data, m
DataCan offer the ram space size of direct memory visit for current system;
c、
α ∈ [0.001,0.01] wherein, t
CpuDuration for each clock period of processor.
In described step C2, if current transmission be from outside be set to the DRP data reception process of internal memory, then whether triggered overtime interruption and judged whether current transmission is last transmission according to peripheral hardware; If current transmission is the data transmission procedure from the internal memory to the peripheral hardware, then judge according to end mark position information whether current transmission is last transmission.
Because the present invention has adopted above technical scheme, so have following beneficial effect:
The present invention is determined the size in the two block RAM spaces selected for use by CPU, can be according to the utilization factor of current C PU and internal memory, the operational resource of current concrete demands of applications and present system dynamically determines the distribution of resource, can maximumly bring into play system effectiveness, reach optimum resource distribution.
By revising the transmission configuration word configuration information that each DMA transmits can be set dynamically flexibly in the present invention, can stop the DMA transmission flexibly by being provided with of end mark position.
The present invention adopts two block RAM pieces to carry out DMA and transmits, fully played the usefulness of DMA, in the less processing time that has taken CPU, total system can be operated under the lower frequency, thereby reduced the power consumption of system, can make portable terminal have longer stand-by time.
Description of drawings
Fig. 1 carries out the schematic diagram of ping-pong operation for adopting hardware logic;
Fig. 2 carries out the process flow diagram of exchanges data for the present invention adopts dma mode;
Fig. 3 is the synoptic diagram of the present invention when carrying out Data Receiving;
Fig. 4 is the processing flow chart of the present invention when carrying out Data Receiving;
Fig. 5 is the synoptic diagram of the present invention when carrying out the data transmission;
Fig. 6 is the processing flow chart of the present invention when carrying out the data transmission.
Embodiment
Below in conjunction with Figure of description the specific embodiment of the present invention is described.
As shown in Figure 2, the present invention at first determines the two block RAM block spaces that need select for use by CPU, then the transmission configuration word is write in the dma controller, the transmission configuration word that dma controller writes according to CPU carries out data and transmits, after transmission finishes, dma controller sends a look-at-me to CPU, CPU is revised as another RAM block address with the RAM block address in the transmission configuration word in the dma controller, reconfigure the DMA passage according to amended transmission configuration word, carry out data and transmit, transmit the back dma controller that finishes and send a look-at-me to CPU; Dma controller whenever sends look-at-me one time, and the RAM block address in the transmission configuration word is just revised once, up to Data Transfer Done.
The space size of the two block RAM pieces that CPU is selected is determined by the slot time n that interrupts taking place and the data volume of every time slot.
The slot time n that interrupts taking place is the duration t of interrupt service routine
IsrWith every time slot duration t
SlotRatio after round.The duration t of just each interrupt service routine
IsrIn comprise duration of n time slot.
The duration t of interrupt service routine
IsrNeed satisfy following three conditions simultaneously:
(1) t
Isr≤ t
Trs, t wherein
TrsFor being assigned to the delay on the data transmission;
(2) (t
Isr+ t
Isrrun) * s
Data* 2≤m
Data, t wherein
IsrrunBe that interrupt service routine is carried out and the switching time of system task, it is that the transfer rate of data is s that the unit interval need be carried out data quantity transmitted
Data, m
DataCan offer the ram space size of direct memory visit for current system;
(3)
α ∈ [0.001,0.01] wherein, t
CpuDuration for each clock period of CPU.
In the above-mentioned formula (2) take advantage of 2 expressions to use ping-pong operations the time, use two block RAM districts, because the data rate s that moves
DataBe fixed value, therefore the equal and opposite in direction in two RAM districts that set.
α in the above-mentioned formula (3) represents that CPU work clock and DMA move the ratio in the time interval of operation generation.General optional α ∈ [0.001,0.01], the frequency of operation of DMA is identical with the frequency of operation of CPU, and the CPU frequency of operation is f
Cpu, then the time of per clock period of CPU is t
Cpu, wherein
For example CPU is determined that the process of two selected block RAM block space sizes describes below:
For example in gsm system after the prevention at radio-frequency port analog to digital conversion, 120ms has 26 frames, 8 time slots of every frame, and every time slot data volume is 156.25Symbol, every Symbol information 16 bit quantizations, t
SlotSize be 0.577ms.
Suppose the f of work clock system of CPU
CpuBe 100MHz, the interval m of available RAM
DataBe 100kbit, the transmission delay t of system assignment
TrsBe 6ms, t
IsrrunTime be approximately 100us.
Message transmission rate s
DataFor:
According to above-mentioned formula (1) t
Isr≤ t
Trs, can get t
Isr≤ 6ms;
According to above-mentioned formula (2) (t
Isr+ t
Isrrun) * s
Data* 2≤m
Data, can get (t
IsrTherefore+100us) * 4.3Mb/s≤100kb can get t as calculated
Isr≤ 10.6ms;
According to above-mentioned formula (3)
With α ∈ [0.001,0.01], can get 0.01ms/t
Isr∈ [0.001,0.01] therefore can get t as calculated
Isr∈ [1ms, 10ms];
Therefore can draw t
IsrSpan be [1ms, 6ms], be the duration t of interrupt service routine according to the slot time n that interrupt to take place again
IsrWith every time slot duration t
SlotRatio, can get n*0.577ms ∈ [1ms, 6ms], n is an integer, thereby the span that can draw n is [2,10].
Therefore can select when n=8, promptly every frame (8 time slots) is initiated a DMA and is moved.The data of per 1 frame storage are 8*156.25*16=20kb, because the present invention's employing is two block RAMs, therefore needing two blocks of data spaces be the RAM of 20Kb, can satisfy above-mentioned equation respectively.
Receive data and two aspects of internal memory transmission data from internal memory respectively below, analyze and adopt the present invention to carry out the process of exchanges data, suppose that the present invention carries out " ping-pong operation " when switching between two RAM pieces, RAM piece 1 can be used during " ping " state, " pang " RAM piece 2 can be used during state.
(1) internal memory receives data procedures
Figure 3 shows that data stream and control stream when Data Receiving is carried out in interior existence, wherein solid line is represented data stream, and dotted line is represented control stream, and control stream expression CPU is to the configuration information of peripheral hardware and DMA, DMA feeds back to the interrupting information of CPU etc., and data stream represents that DMA moves into internal memory to data from peripheral hardware.
Figure 4 shows that the processing flow chart of the present invention when carrying out Data Receiving, its processing procedure is as follows:
Under the control of CPU, the data that peripheral hardware will transmit are written in the data register of peripheral hardware, and CPU is written to the internal register of dma controller with a DMA transmission configuration word, comprises information such as source address, destination address and data volume control in the transmission configuration word.Source address in the transmission configuration word is the data register of peripheral hardware, destination address is a RAM piece 1, dma controller carries out data according to the data volume control DMA passage that defines in the transmission configuration word and transmits, the size of defined data volume equals the size in RAM piece 1 space, behind Data Transfer Done, dma controller sends a look-at-me to CPU, and whether this secondary data of reflection transmits successful in the status register of respective channel.
After CPU receives the look-at-me that dma controller sends, at first analyzing is the interruption which DMA passage triggers, judge according to the state of channel status register whether the interruption that current DMA passage triggers is loading error occurring then, if, the end of transmission (EOT) of DMA passage then, and the status information of wrong DMA passage fed back to upper layer software (applications), do further processing by upper layer software (applications); If not, check then whether peripheral hardware has triggered overtime interruption, if overtime interruption is arranged, then the DMA of passage transmission can finish, and the status information that will correctly transmit feeds back to upper layer software (applications), does further processing by upper layer software (applications); If there is not overtime interruption, then judge current state and be " ping " state according to the destination address of this DMA passage, CPU reads data in the RAM piece 1, after having read data, with current status modifier be " pang " state, and reconfigure current DMA passage, and this DMA passage destination address is arranged to the address of RAM piece 2, begin RAM piece 2 is read.
When new data arrived the data register of peripheral hardware, the DMA passage can transmit once more, up to this end of transmission (EOT).When not receiving data in the time that the data register of peripheral hardware is being set, then trigger overtime Interrupt Process, can finish data transmission remaining at present in the data register of peripheral hardware this moment, and close peripheral hardware and this DMA passage.
(2) internal memory sends data procedures
Figure 5 shows that data stream and control stream when internal memory sends data, wherein solid line is represented data stream, and dotted line is represented control stream.Control stream expression CPU is to the configuration information of peripheral hardware and DMA, and DMA feeds back to the interrupting information of CPU etc., and data stream represents that DMA moves peripheral hardware to data from internal memory.
Figure 6 shows that the processing flow chart of the present invention when carrying out the data transmission, its processing procedure is as follows:
CPU is written to a DMA transmission configuration word internal register of dma controller, comprise information such as source address, destination address and data volume control in the transmission configuration word, source address in the transmission configuration word is a RAM piece 1, destination address is the data register of peripheral hardware, dma controller carries out data according to the data volume control DMA passage that defines in the transmission configuration word and transmits, behind Data Transfer Done, dma controller sends a look-at-me to CPU.
After CPU receives the look-at-me of dma controller triggering, analysis is the interruption which passage of DMA triggers, judge then whether the interruption that triggers when prepass is loading error occurring, if, then the DMA of passage transmission can finish, and the status information of wrong passage fed back to upper layer software (applications), do further processing by upper layer software (applications); If not, then judge by the end mark position information of checking passage whether current DMA transmission is last transmission, if last transmission, then the DMA of passage transmission can finish, and the status information that will correctly transmit feeds back to upper layer software (applications), does further processing by upper layer software (applications); If not last transmission, then judge current state and be " ping " according to the source address of this DMA passage, after current data to be sent are finished by the transmission of DMA passage, with current status modifier be " pang " state, and data to be sent are put in the RAM piece 2, reconfigure the DMA passage, the source address of this DMA passage is arranged to RAM piece 2, open amended DMA passage, the data in the RAM piece 2 are sent.
Zone bit information is arranged in the internal memory by CPU, in interrupt service routine, all check earlier at every turn, in each interrupt service routine, CPU can judge that current transmission also needs the table tennis of how many times DMA to move, when finding that next time DMA moves when being last, CPU becomes the end mark position with the zone bit information setting in the internal memory, when last DMA move finish after, triggered interruption, and entered interrupt service routine, subsequently just according to whole the moving that be through with of current end mark position.Suppose that the data that need to transmit are 4 * 16 * 16 * 8 bits, each DMA moves and finishes 16 * 16 * 8 bits, then need 4 DMA to move, when moving end and having triggered interruption for the 3rd time, just be provided with the end mark position, when the 4th is moved end and triggered interruption, in the interrupt service routine of the 4th, the discovery end mark is set up, and just no longer initiates new moving, and has finished all operations of moving.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Claims (9)
1, a kind of method that adopts the direct memory access mode to carry out exchanges data is characterized in that comprising step:
A, determine two blocks of data storage spaces, and wherein the address of a storage space writes the transmission configuration word by processor;
B, direct memory access controller utilize the storage space of transmission configuration word appointment to carry out data and transmit, and send look-at-me to processor after transmission finishes;
When C, processor receive described look-at-me, judge whether all data transmit to finish, if then end data transmits, otherwise, memory space address current in the transmission configuration word is revised as another piece memory space address, change step B.
2, employing direct memory access mode according to claim 1 is carried out the method for exchanges data, it is characterized in that: the equal and opposite in direction of two storage spaces in the described steps A.
3, employing direct memory access mode according to claim 1 is carried out the method for exchanges data, it is characterized in that described step C may further comprise the steps:
It is the interruption which direct memory access path triggers that C1, processor analyze, and judges whether loading error occurring of passage according to the state of the status register of this passage, and in this way, the end of transmission (EOT) of direct memory access path is not as being commentaries on classics step C2;
C2, processor judge whether current transmission is last transmission, and in this way, end of transmission (EOT) as not being, is revised as another piece memory space address with current memory space address, change step B.
4, employing direct memory access mode according to claim 2 is carried out the method for exchanges data, it is characterized in that: the size of described two storage spaces is determined by the slot time that interrupts taking place and the data volume of every time slot.
5, employing direct memory access mode according to claim 4 is carried out the method for exchanges data, it is characterized in that: the slot time that described interruption takes place is to round behind the ratio of duration of interrupt service routine and every time slot duration.
6, employing direct memory access mode according to claim 5 is carried out the method for exchanges data, it is characterized in that: the duration t of described interrupt service routine
IsrNeed meet the following conditions simultaneously:
A, t
Isr≤ t
Trs, t wherein
TrsFor being assigned to the delay on the data transmission;
B, (t
Isr+ t
Isrrun) * s
Dta* 2≤m
Data, t wherein
IsrrunBe the switching time of interrupt service routine execution and system task, s
DataBe the transfer rate of data, m
DataCan offer the ram space size of direct memory visit for current system;
7, employing direct memory access mode according to claim 1 and 2 is carried out the method for exchanges data, it is characterized in that: comprise source address, destination address and data volume control information in the described transmission configuration word.
8, employing direct memory access mode according to claim 3 is carried out the method for exchanges data, it is characterized in that: in described step C2, if current transmission be from outside be set to the DRP data reception process of internal memory, then whether triggered overtime interruption and judged whether current transmission is last transmission according to peripheral hardware.
9, employing direct memory access mode according to claim 3 is carried out the method for exchanges data, it is characterized in that: in described step C2, if current transmission is the data transmission procedure from the internal memory to the peripheral hardware, then judge according to end mark position information whether current transmission is last transmission.
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| CN101276315B (en) * | 2007-03-30 | 2011-06-22 | 财团法人工业技术研究院 | Direct memory access controller for dynamically regulating transmission data width and method thereof |
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