JP2011039964A - Endian conversion circuit, endian conversion method and microcontroller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an endian conversion circuit that can perform efficient endian conversion. <P>SOLUTION: The endian conversion circuit has: a data holding part 11 in which address command of a lowest level bit of an address signal is performed as a 'Don't care' bit; and an endian conversion part 12. The endian conversion part 12 performs endian conversion to writing data to the data holding part 11 or reading data d1 from the data holding part 11 based on the lowest level bit value of the address signal accessing the data holding part 11. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an endian conversion circuit, an endian conversion method, and a microcontroller.

  Little endian, big endian, and the like are known as a method of arranging data of a plurality of bytes on a memory. Endian means the order in which recording / transfer is performed at the time when numerical data having a data amount of 2 bytes or more is recorded or transferred, and divided into one byte. The method of recording / transmitting in order from the most significant byte is called big endian, and the method of recording / transmitting in order from the least significant byte is called little endian.

  In order to transfer and process a plurality of bytes of data between a processor such as a CPU (Central Processing Unit) using a different endian method, a communication macro or a memory macro, it is necessary to perform endian conversion.

One endian conversion method is performed by a program.
For example, when the CPU receives data from a communication macro having an endian system different from its own endian system, the CPU executes an endian conversion program to perform endian conversion. Even when data is transferred to the communication macro, the CPU transfers the data after converting the input / output macro to the endian system in advance.

JP-A-8-305628 JP 2001-26150 A JP 2004-355432 A

However, in the conventional technique, it is necessary for the processor to execute the endian conversion program to convert the data sequence, and there is a problem that the operation efficiency of the processor is deteriorated.
In view of the above points, an object of the present invention is to provide an endian conversion circuit, an endian conversion method, and a microcontroller that can perform endian conversion efficiently.

In order to achieve the above object, the following endian conversion circuit is provided.
The endian conversion circuit includes a data holding unit for which an address command is issued using the least significant bit of the address signal as a don't care bit, and the data holding unit based on the value of the least significant bit of the address signal accessing the data holding unit. And an endian conversion unit that performs endian conversion on the data written to the unit or read data from the data holding unit.

In order to achieve the above object, the following microcontroller is provided.
The microcontroller writes a data holding unit that processes the least significant bit of the address signal as a don't care bit and information on whether to perform endian conversion in the least significant bit of the address signal that accesses the data holding unit, A processor that accesses the data holding unit; and an endian conversion unit that performs endian conversion on write data to the data holding unit or read data from the data holding unit based on the least significant bit of the address signal; Have.

  According to the disclosed endian conversion circuit, endian conversion method, and microcontroller, endian conversion can be performed efficiently.

It is a figure which shows the structure of an example of an endian conversion circuit. It is a figure which shows the mode of the endian conversion at the time of the write access to a data holding part. It is a figure which shows the mode of the data reading from a data holding part when an even-numbered address is designated. It is a figure which shows the mode of the data writing to a data holding part when an even-numbered address is designated. It is a figure which shows the structure of an example of a microcontroller. It is a figure which shows an example of the endian conversion circuit provided in the communication macro. It is a flowchart which shows the flow of a process of the microcontroller at the time of data reading. It is a flowchart which shows the flow of a process of the microcontroller at the time of data writing. It is a figure which shows a mode that endian conversion is performed at the time of data writing.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating a configuration of an example of an endian conversion circuit.

For the endian described below, for example, a system in which 4 bytes of data 1234ABCD _H are arranged as “12 _H 34 _H AB _H CD _H ” from the upper byte is set to big endian, and “CD _H AB _H 34 _H 12 _H ” is set from the lower byte. The arrangement method is a little endian. The subscript H indicates that the numerical value is a hexadecimal number.

The endian conversion circuit 10 includes a data holding unit 11 and an endian conversion unit 12.
The data holding unit 11 is, for example, a buffer or memory such as a first-in first-out (FIFO) circuit. The data holding unit 11 has a function of temporarily holding data, for example, when a communication macro (not shown) and data transfer between processors are performed.

  In the example of FIG. 1, a state in which data d1 of 4 bytes and 1 word is stored in little endian in the data holding unit 11 is shown. The first byte of data d1 is stored at address 1000, the second byte is stored at address 1001, the third byte is stored at address 1002, and the fourth byte is stored at address 1003.

  The address signal given to the data holding unit 11 is output from, for example, a processor in the chip. In the present embodiment, it is assumed that full address access is possible without rounding the lower bits of the address signal output from the processor. However, the data holding unit 11 ignores the least significant bit of the address during word access or halfword access. That is, the data holding unit 11 does not perform full address decoding, and the least significant bit of the address is processed as a don't care bit. On the other hand, the least significant bit of the address is input to the endian conversion circuit 10 as information indicating whether or not to perform endian conversion.

  The endian conversion unit 12 can be realized using a selector, for example. The endian conversion unit 12 determines whether an address signal for accessing the data holding unit 11 specifies either an even address or an odd address of the data holding unit 11. Specifically, the endian conversion unit 12 detects the least significant bit of the address signal and determines whether the address signal specifies an even address (the least significant bit is 0) or an odd address (the least significant bit is 1). ) Is specified. The endian conversion unit 12 performs endian conversion on the write data to the data holding unit 11 or the read data from the data holding unit 11 when the address signal is either an even address or an odd address.

  The endian conversion circuit 10 can determine whether or not to perform endian conversion on the basis of an address signal for each word (or halfword) of data transferred from the processor or communication interface (not shown) to the data holding unit 11.

Hereinafter, the operation of the endian conversion circuit 10 will be described.
In the following example, the endian conversion unit 12 performs endian conversion when an odd address of the data holding unit 11 is specified by an address signal, and does not perform endian conversion when an even address is specified. Will be described.

  For example, when the endian conversion circuit 10 is provided between a communication macro that handles data in little endian and a processor that handles data in big endian, the endian conversion circuit 10 performs the following operation.

  For example, when a processor reads data d1 held in the data holding unit 11 in little endian by a communication macro, the processor designates the address 1001 or 1003 of the data holding unit 11 by an address signal and performs read access. . At this time, since the address signal is an odd address, the least significant bit is 1, and the endian conversion unit 12 performs endian conversion. That is, the endian conversion unit 12 converts the data d1 in the little endian data sequence into the data d1a in the big endian data sequence.

As a result, even a big endian processor having a data arrangement opposite to that of the little endian can be processed as data d1a having the same contents as the data d1.
Next, the operation of the endian conversion circuit 10 when performing endian conversion at the time of write access to the data holding unit 11 will be described.

FIG. 2 is a diagram illustrating a state of endian conversion at the time of write access to the data holding unit.
For example, when data d1a is written from the big endian processor to the data holding unit 11 used as a buffer for transfer in little endian, the endian conversion unit 12 performs the following operation.

  When the address signal at the time of write access designates an odd address such as address 1001 or address 1003, the endian conversion unit 12 converts the data d1a of the big endian data sequence from the processor side into little endian. Then, the first byte of data d1a is stored at address 1000 of data holding unit 11, the second byte at address 1001, the third byte at address 1002, and the fourth byte at address 1003.

As a result, even a little endian communication macro can be processed as data d1 having the same contents as data d1a.
Although the case where the data holding unit 11 handles data in little endian and the processor handles data in big endian has been described above, endian conversion can also be performed in the same manner when this is the opposite. That is, even when the data holding unit 11 handles data in big endian and the processor handles data in little endian, the endian conversion unit 12 does not convert one data to endian when the address signal specifies an odd address. Convert and transfer to the other.

  The endian conversion unit 12 does not perform endian conversion when the address signal at the time of read access or write access to the data holding unit 11 specifies an even address.

For example, when both the communication macro and the processor handle data in little endian, the operations shown in FIGS. 3 and 4 are performed.
FIG. 3 is a diagram showing how data is read from the data holding unit when an even address is designated.

  At the time of read access, if an even address (the least significant bit is 0) is specified by the address signal, the endian conversion unit 12 does not perform endian conversion, and the data d1 in the little endian sequence of the data holding unit 11 is used as it is. Forward.

  Similarly, when both the communication macro and the processor handle data in big endian, the endian conversion unit 12 reads the big endian array data held in the data holding unit 11 as it is without performing endian conversion. Good.

FIG. 4 is a diagram illustrating a state of data writing to the data holding unit when an even address is designated.
When an even address is specified by an address signal at the time of write access, the endian conversion unit 12 does not perform endian conversion and writes data d1a in a little endian sequence from the processor side to the data holding unit 11.

  Similarly, when both the communication macro and the processor handle data in big endian, the endian conversion unit 12 may write the little endian sequence data from the processor side into the data holding unit 11 without performing endian conversion. .

  As described above, in the endian conversion circuit 10 of the present embodiment, whether or not to perform endian conversion is determined depending on whether the address signal accessing the data holding unit 11 specifies an even address or an odd address. Yes. As a result, it is possible to easily determine whether or not endian conversion is necessary, and it is possible to efficiently perform endian conversion without adding a hardware configuration such as a register or a switch for setting whether or not endian conversion is necessary. In addition, data swapping by the program becomes unnecessary, and the program efficiency is improved.

  In the above description, the endian conversion unit 12 performs endian conversion when an odd address is specified in the address signal, and does not perform endian conversion when an even address is specified. It is not limited to. The endian conversion unit 12 may perform endian conversion when an even address is specified by an address signal, and may not perform endian conversion when an odd address is specified.

  In the above description, the endian conversion unit 12 determines whether the endian conversion is performed by determining whether the address signal is an even address or an odd address, but further considers the access size. May be. Although details will be described later, endian conversion is not necessary when byte-by-byte access is performed. Therefore, endian conversion is disabled, and endian conversion is performed when accessing multiple bytes (for example, halfword or word). You may make it validate.

Next, a case where the endian conversion circuit as described above is applied to a microcontroller will be described as an example.
(Second Embodiment)
FIG. 5 is a diagram illustrating a configuration of an example of a microcontroller.

For the endian described below, for example, a system in which 4 bytes of data 1234ABCD _H are arranged as “12 _H 34 _H AB _H CD _H ” from the upper byte is set to big endian, and “CD _H AB _H 34 _H 12 _H ” is set from the lower byte. The arrangement method is a little endian. The subscript H indicates that the numerical value is a hexadecimal number.

  The microcontroller 20 includes a processor 21, a RAM (Random Access Memory) 22, a flash memory 23, a bus converter 24, a bus bridge 25, peripheral circuits 26 and 27, and communication macros 28 and 29.

  The processor 21 is, for example, a CPU or a DSP (Digital Signal Processor), and controls each part of the microcontroller 20. Further, when accessing the later-described data holding unit of the communication macros 28 and 29, for example, the processor 21 performs full address access without rounding the lower bits of the address. However, the data holding unit 11 ignores the least significant bit of the address during word access or halfword access. That is, the data holding unit 11 does not perform full address decoding, and the least significant bit of the address is processed as a don't care bit. On the other hand, the least significant bit of the address is input to the endian conversion circuit 10 as information indicating whether or not to perform endian conversion.

The RAM 22 stores programs being executed by the processor 21 and data being calculated.
The flash memory 23 stores an OS (Operation System) executed by the processor 21, various programs, and various data.

  The bus converter 24 functions as an interface with the processor 21, the RAM 22, the flash memory 23, and the internal bus bs, and has, for example, a 32-bit and 16-bit conversion function.

The bus bridge 25 connects the internal bus bs1 and the peripheral bus bs2.
The peripheral circuits 26 and 27 are an interrupt controller, a watchdog timer, and the like, and are connected to the peripheral bus bs2.

The communication macros 28 and 29 are interface circuits for performing communication with the outside of the microcontroller 20. The communication macros 28 and 29 are interface circuits such as USB (Universal Serial Bus), UART (Universal Asynchronous Receiver Transmitter), I ² C bus, CAN (Controller Area Network) bus, and IE (Inter Equipment) bus. . The endian conversion circuit 10 as shown in FIG. 1 is provided in the communication macros 28 and 29, for example.

In FIG. 5, two communication macros 28 and 29 are shown, but one or three or more may be used.
FIG. 6 is a diagram illustrating an example of the endian conversion circuit provided in the communication macro.

  The communication macro 28 has a data holding unit 281 and an endian conversion unit 282, which function as an endian conversion circuit as shown in FIG. That is, the data holding unit 281 corresponds to the data holding unit 11 in FIG. 1, and the endian conversion unit 282 corresponds to the endian conversion unit 12 in FIG. However, in the configuration shown in FIG. 6, the endian conversion unit 282 includes an access size detection unit 282b in addition to the endian conversion selector 282a that performs endian conversion.

  The access size detection unit 282b determines whether or not to cause the endian conversion selector 282a to perform endian conversion based on the address signal for accessing the data holding unit 281 and the access size to the data holding unit 281. The access size detection unit 282b does not need to perform endian conversion when byte-by-byte access is performed. Therefore, the endian conversion is invalidated, and the endian conversion is validated when a plurality of bytes are accessed. The access size detection unit 282b may be outside the endian conversion unit 282.

  In the following description, an example will be described in which the endian conversion selector 282a performs endian conversion when the address signal specifies an odd address (the least significant bit is 1) of the data holding unit 281. In this case, the access size detection unit 282b is realized using, for example, an OR circuit 282b1 and an AND circuit 282b2, as shown in FIG.

  Two input signals indicating whether the access is a word access or a halfword access are input from the processor 21 to the OR circuit 282b1. In the case of word access or halfword access, the OR circuit 282b1 receives a signal of 1, 0, and the OR circuit 282b1 outputs 1. In the case of byte access, the two inputs of the OR circuit 282b1 are both 0, and the OR circuit 282b1 outputs 0.

  The least significant bit of the address signal is input to one input terminal of the AND circuit 282b2, and the output signal of the OR circuit 282b1 is input to the other input terminal. When the output of the OR circuit 282b1 is 1, the output of the AND circuit 282b2 is determined by the least significant bit of the address signal. That is, the AND circuit 282b2 outputs 1 when the least significant bit is 1, and outputs 0 when the least significant bit is 0. On the other hand, when the output of the OR circuit 282b1 is 0, the output of the AND circuit 282b2 becomes 0 regardless of the value of the least significant bit of the address signal, and the endian conversion becomes invalid.

Note that the endian conversion unit 282 may be provided outside the communication macro 28.
Hereinafter, the operation of the microcontroller 20 will be described by taking as an example the case where the communication macro 28 is an interface circuit that communicates with the PC 30 via USB.

First, the operation of the microcontroller 20 at the time of data reading will be described.
FIG. 7 is a flowchart showing a flow of processing of the microcontroller at the time of data reading.

First, the communication macro 28 receives USB data from the PC 30 and holds it in the data holding unit 281 (step S1). 6, the first byte is 01 _H, 2 byte is 23 _H, 3 byte is 45 _H, 4 th byte 4 bytes of 67 _H data d10 is a sequence of little endian, the data holding unit 281 It shows a state held at addresses 100 to 103. The subscript H indicates that the numerical value is a hexadecimal number.

  Next, the processor 21 performs read access to the data holding unit 281 (step S2). For example, the processor 21 accesses the data holding unit 281 for each byte or for each of a plurality of bytes (word or halfword). When performing word access or halfword access, the processor 21 inputs 1 to one input terminal of the OR circuit 282b1 of the access size detection unit 282b shown in FIG.

  Further, when performing the word access or the half word access, the processor 21 uses an odd address to the data holding unit 281 of the communication macro 28 that holds data in a little endian sequence when the processor 21 adopts the big endian. Access with. For example, when reading one word of data d10 at addresses 100 to 103, the processor 21 designates address 101 or address 103 by an address signal and performs read access.

  On the other hand, when performing the word access or the halfword access, the processor 21 uses an even address for the data holding unit 281 of the communication macro 28 that holds the data in the little endian sequence when the processor 21 adopts the little endian. Access with. For example, when reading one word of data d10 at addresses 100 to 103, the processor 21 designates address 100 or address 102 by an address signal and performs read access.

  Next, the endian conversion unit 282 determines whether or not the access size from the processor 21 is a multibyte (word or halfword) access (step S3). If the endian conversion unit 282 determines that multi-byte access has occurred, the endian conversion unit 282 determines whether the least significant bit of the address signal is 1 (step S4).

  Specifically, the access size detection unit 282b determines that the access is a multiple byte when 1 is input to at least one of the two input terminals of the OR circuit 282b1. On the other hand, when 0 is input to both of the two input terminals of the OR circuit 282b1, the access size detection unit 282b determines that access is for each byte. In the latter case, the access size detection unit 282b invalidates endian conversion regardless of the least significant bit of the address signal. Thus, in the case of byte access, 1-byte data at the address specified by the processor 21 is read without endian conversion (step S5).

  Even when the least significant bit is determined to be 0 in the process of step S4, the endian conversion unit 282 performs the process of step S5. For example, when the processor 21 performs word access designating address 100 or address 102, the endian conversion unit 282 reads data d10 for one word at addresses 100 to 103 without endian conversion, and sends the data to the processor 21. Send. When the processor 21 performs a halfword access designating the address 100, the endian conversion unit 282 reads the halfword data at the addresses 100 and 101 without performing endian conversion and transmits the data to the processor 21. .

  On the other hand, if the least significant bit is determined to be 1 in the process of step S4, the endian conversion unit 282 performs endian conversion on the data held in the data holding unit 281 by the endian conversion selector 282a and reads the data ( Step S6). For example, when the processor 21 performs word access designating address 101 or address 103, the endian conversion unit 282 converts the data d10 for one word at addresses 100 to 103 into a big endian sequence as shown in FIG. Convert to data d10a. Then, the endian conversion unit 282 reads the endian converted data d10a and transmits it to the processor 21.

Next, the operation of the microcontroller 20 when data is written from the processor 21 will be described.
FIG. 8 is a flowchart showing a flow of processing of the microcontroller at the time of data writing.

FIG. 9 is a diagram showing how endian conversion is performed when data is written.
First, the processor 21 performs data write access to the data holding unit 281 (step S10). At this time, the processor 21 performs, for example, write access for each byte or write access for each of a plurality of bytes (for example, a word or a halfword) with respect to the data holding unit 281. When performing word access or halfword access, the processor 21 inputs 1 to one input terminal of the OR circuit 282b1 of the access size detection unit 282b.

  Further, when performing the word access or the half word access, the processor 21 uses an odd address for the data holding unit 281 of the communication macro 28 that holds data in a little endian sequence when the processor 21 adopts the big endian. Access with. For example, when writing data of one word at addresses 100 to 103, the processor 21 designates address 101 or address 103 by an address signal and performs write access.

  On the other hand, when performing the word access or the halfword access, the processor 21 uses an even address for the data holding unit 281 of the communication macro 28 that holds the data in the little endian sequence when the processor 21 adopts the little endian. Access with. For example, when writing one word data at addresses 100 to 103, the processor 21 designates address 100 or address 102 by an address signal and performs write access.

  Next, the endian conversion unit 282 determines whether or not the access size from the processor 21 is a multi-byte (word or halfword) access (step S11). If the endian conversion unit 282 determines that multi-byte access has occurred, it determines whether the least significant bit of the address signal is 1 (step S12).

  Specifically, the access size detection unit 282b determines that the access is a multiple byte when 1 is input to at least one of the two input terminals of the OR circuit 282b1. On the other hand, when 0 is input to both of the two input terminals of the OR circuit 282b1, the access size detection unit 282b determines that access is for each byte. In the latter case, the access size detection unit 282b invalidates endian conversion regardless of the least significant bit of the address signal. Thereby, in the case of byte access, 1-byte data from the processor 21 side is written to the address of the data holding unit 281 specified by the processor 21 without endian conversion (step S13).

  Even when the least significant bit is determined to be 0 in the process of step S12, the endian conversion unit 282 performs the process of step S13. For example, when the processor 21 performs word access designating the address 100 or address 102 of the data holding unit 281, the endian conversion unit 282 does not endianly convert the data d10 a for one word to the addresses 100 to 103. Write to. When the processor 21 performs a halfword access designating 100 addresses, the endian conversion unit 282 writes halfword data at addresses 100 and 101 without endian conversion.

  On the other hand, when the least significant bit is determined to be 1 in the process of step S12, the endian conversion unit 282 performs endian conversion on the data transmitted from the processor 21 side and writes the data to the data holding unit 281 (step S14). ). For example, when the processor 21 performs a word access designating the address 101 or 103 of the data holding unit 281, the endian conversion unit 282 converts the data d10a for one word into a little endian sequence as shown in FIG. Convert to data d10. Then, the endian conversion unit 282 writes the endian converted data d10 at addresses 100 to 103 of the data holding unit 281. Then, the communication macro 28 transmits the written data d10 as USB data to the PC 30 (step S15).

  As described above, in the microcontroller 20 according to the present embodiment, whether or not to perform endian conversion is determined depending on whether the address signal accessed to the data holding unit 281 specifies an even address or an odd address. . As a result, it is possible to easily determine whether or not endian conversion is necessary, and endian conversion can be performed efficiently.

  For example, when there are a plurality of communication macros 28 and 29 having different endians, the processor 21 can determine whether or not to perform endian conversion for each of the communication macros 28 and 29 only by specifying even or odd addresses.

  In the above description, the endian conversion unit 282 performs endian conversion when an odd address is specified in the address signal, and does not perform endian conversion when an even address is specified. It is not limited. The endian conversion unit 282 may perform endian conversion when an even address is specified by an address signal, and may not perform endian conversion when an odd address is specified. In this case, the endian conversion selector 282a performs endian conversion when the least significant bit of the address signal is 0. The access size detection unit 282b may have a circuit configuration that fixes the output signal input to the endian conversion selector 282a to 1 in the case of byte access.

Further, it may be set whether or not to perform endian conversion for each word or for each half word by an address signal.
As described above, the endian conversion circuit, the endian conversion method, and the microcontroller according to the present invention have been described based on the embodiments. However, these are merely examples, and the present invention is not limited to the above description.

The following additional notes are further disclosed with respect to the plurality of embodiments described above.
(Supplementary note 1) A data holding unit in which an address command is performed with the least significant bit of the address signal as a don't care bit;
An endian conversion unit that performs endian conversion on write data to the data holding unit or read data from the data holding unit based on the value of the least significant bit of the address signal that accesses the data holding unit; ,
An endian conversion circuit comprising:

  (Additional remark 2) It has an access size detection part which detects the access size at the time of the writing to the said data holding part or the reading from the said data holding part, and the said access size detection part is when the said access size is multiple bytes The endian conversion circuit according to appendix 1, wherein the endian conversion is enabled.

  (Additional remark 3) The said endian conversion circuit of Additional remark 2 characterized by the said access size detection part validating the said endian conversion, when the said access size is a word or a halfword.

(Supplementary Note 4) Determine whether an address signal for accessing the data holding unit that processes the least significant bit of the address signal as a don't care bit specifies an even address or an odd address of the data holding unit,
An endian conversion method in which an endian conversion unit performs endian conversion on write data to the data holding unit or read data from the data holding unit based on the determination result.

  (Supplementary Note 5) The access size at the time of writing to the data holding unit or at the time of reading from the data holding unit is detected, and the endian conversion is enabled when the access size is a plurality of bytes. The endian conversion method according to appendix 4.

(Supplementary note 6) The endian conversion method according to supplementary note 5, wherein the endian conversion is enabled when the access size is a word or a halfword.
(Appendix 7) A data holding unit that processes the least significant bit of the address signal as a don't care bit;
Information on whether or not to perform endian conversion is written in the least significant bit of the address signal that accesses the data holding unit, and a processor that accesses the data holding unit;
A microcontroller comprising: an endian conversion unit for performing endian conversion on write data to the data holding unit or read data from the data holding unit based on the least significant bit of the address signal .

  (Additional remark 8) It has the access size detection part which detects the access size from the said processor at the time of the writing to the said data holding part or the reading from the said data holding part, The said access size detection part is the said access size The microcontroller according to appendix 7, wherein the endian conversion is validated when is a plurality of bytes.

  (Additional remark 9) The said access size detection part validates the said endian conversion, when the said access size is a word or a halfword, The microcontroller of Additional remark 8 characterized by the above-mentioned.

  (Supplementary Note 10) The microcontroller according to any one of Supplementary Notes 7 to 9, wherein the endian conversion unit is arranged in a communication macro that performs communication processing.

10 Endian conversion circuit 11 Data holding unit 12 Endian conversion unit d1, d1a Data

Claims (6)

A data holding unit in which an address command is performed using the least significant bit of the address signal as a don't care bit;
An endian conversion unit that performs endian conversion on write data to the data holding unit or read data from the data holding unit based on the value of the least significant bit of the address signal that accesses the data holding unit; ,
An endian conversion circuit comprising:   An access size detection unit that detects an access size at the time of writing to the data holding unit or at the time of reading from the data holding unit; and the access size detection unit is configured to detect the endian when the access size is a plurality of bytes. 2. The endian conversion circuit according to claim 1, wherein the conversion is enabled. Determine whether the address signal that accesses the data holding unit that processes the least significant bit of the address signal as a don't care bit specifies an even address or an odd address of the data holding unit,
An endian conversion method in which an endian conversion unit performs endian conversion on write data to the data holding unit or read data from the data holding unit based on the determination result.   4. The access size at the time of writing to the data holding unit or at the time of reading from the data holding unit is detected, and the endian conversion is validated when the access size is a plurality of bytes. Endian conversion method. A data holding unit that processes the least significant bit of the address signal as a don't care bit;
Information on whether or not to perform endian conversion is written in the least significant bit of the address signal that accesses the data holding unit, and a processor that accesses the data holding unit;
Based on the least significant bit of the address signal, an endian conversion unit that performs endian conversion on write data to the data holding unit or read data from the data holding unit;
A microcontroller comprising:   An access size detecting unit that detects an access size from the processor at the time of writing to the data holding unit or at the time of reading from the data holding unit; and the access size detecting unit has an access size of a plurality of bytes. 6. The microcontroller according to claim 5, wherein the endian conversion is enabled.

Images