JP2005148904A - Ring buffer controller and ring buffer control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and accurately detect the full/empty of a ring buffer, without increasing the control sequence. <P>SOLUTION: A write pointer generating part 105 increments the value of a write pointer(WP) and updates the WP. A readout pointer generating part 107 increments the value of a readout pointer(RP) and updates the RP. The writing pointer generating part 105 and the readout pointer generating part 107 manage the pointers with the number of bits obtained, by adding 1 bit to the number of address bits to be decided by the size of a ring buffer 104, and inverts the added bits when the address bits are counted up from the final address of the ring buffer 104, and returned to the leading address. A comparison arithmetic part 110 compares the WP with the RP and detects the full/empty of the ring buffer 104. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a ring buffer control device and a ring buffer control method for controlling a state of a ring buffer on a system for calculating a remaining amount of the ring buffer from a pointer value.

  Conventionally, in the memory control system, a memory control system called a ring buffer system that manages a memory buffer using two address pointers of a write pointer (WP) and a read pointer (RP) is known.

  WP increments after data write access to the memory, and RP increments after data read access from the memory. The variable range of both the WP and RP pointers corresponds to the buffer memory area. The initial address of the buffer area is set as an initial value. If the final address of the buffer area is exceeded after increment, the initial value is returned.

In the ring buffer method, using these pointer values, it is determined whether the entire area of the buffer is being used (full) and whether the entire area of the buffer is unused (empty). If WP = RP after writing, it is determined to be full, and if WP = RP after reading, it is determined to be empty.
JP-A-5-289847

  However, in the conventional method, when a read event occurs after the buffer becomes full (WP = RP) by writing but reading cannot be performed for some reason, RP is not incremented after the read event. Therefore, WP = RP remains. In this case, the write control unit regards WP = RP after the read event, and determines that this is empty even though it is actually full.

  The same applies to the reverse case. If the write event occurs after the buffer becomes empty (WP = RP) by reading, but writing cannot be performed for some reason, WP is not incremented after the write event. Therefore, WP = RP remains. In this case, the read control unit regards WP = RP after the write event, and determines that this is full although it is actually empty.

  As a countermeasure against such a situation, there is a method of calculating the difference between the WP value and the RP value and determining that the buffer is full when, for example, WP-RP = 1, that is, when the remaining amount is 1. However, this method requires a function of subtracting the WP value from the RP value, and has a problem that the buffer area cannot be used completely.

  As another method, when a flag is newly added to the register and WP = RP is obtained after writing is completed, the write control unit rewrites the flag to “end of writing”, and WP = RP is obtained after reading is completed. In such a case, there is a method in which the read control unit rewrites the same flag to “read complete”. This makes it possible to distinguish whether writing or reading is completed and WP = RP, or writing or reading is not performed and WP = RP is maintained. However, this method has a problem that the control sequence such as reading and writing access to the added flag register increases.

  SUMMARY An advantage of some aspects of the invention is that it provides a ring buffer control device and a ring buffer control method capable of easily and accurately determining the fullness and emptyness of a ring buffer. .

  A ring buffer control device according to the present invention is a ring buffer control device for controlling transfer of data using a ring buffer, and a write pointer generating means for generating a write pointer indicating a ring buffer address for storing transfer data next time; Read pointer generation means for generating a read pointer indicating the ring buffer address of the transfer data to be read next time, and the write pointer generation means and the read pointer generation means each have a first address bit used in the ring buffer. Generating a pointer to which a second address bit not used in the ring buffer is added, and updating the pointer when the first address bit of the pointer is at the final address of the ring buffer; Before address bit At the same time back to the start address of the ring buffer employs a configuration for inverting the second address bits.

  The ring buffer control device of the present invention performs an exclusive OR (EXOR) operation of the write pointer and the read pointer, and the operation result is that the first address bit is zero and the second address bit is 1. In some cases, it is detected that the remaining amount of the ring buffer is zero, and in the case where both the first address bit and the second address bit are zero, a comparison for detecting that the usage amount of the ring buffer is zero. A configuration including arithmetic means is adopted.

  The ring buffer control device of the present invention is a ring buffer control device that transfers data from a transmission means that is a data transfer source to a reception means that is a data transfer destination using a ring buffer, wherein the comparison operation means includes: When the operation result is that the first address bit is zero and the second address bit is 1, a first interrupt signal is output to the transmitting means to warn of an overflow of a ring buffer, and the first address bit and the A configuration is adopted in which when the second address bits are both zero, a second interrupt signal indicating completion of data transfer is output to the receiving means.

  With these configurations, it is possible to efficiently use the ring buffer without leaving it, and it is possible to easily detect the fullness and emptyness of the ring buffer without increasing the control sequence.

  An inter-processor communication device according to the present invention is a communication device that transfers data between a first processor and a second processor using a dual port memory, and is used for data transfer from the first processor to the second processor. A first ring buffer control device according to claim 3, and a second ring buffer control device according to claim 3 used for data transfer from the second processor to the first processor, wherein the first ring buffer is used. The first interrupt signal of the control device and the second interrupt signal of the second ring buffer control device are input to the first processor, and the first interrupt signal of the second ring buffer control device and the first ring buffer control device The second interrupt signal is input to the second processor.

  With this configuration, the first processor and the second processor can easily and accurately detect the fullness or emptyness of the ring buffer by the interrupt signal without managing the comparison of the write pointer and the read pointer of the ring buffer. Moreover, such an apparatus can be realized with a small-scale hardware configuration.

  In the ring buffer control method of the present invention, a pointer is generated by adding a second address bit not used in the ring buffer to a first address bit used in the ring buffer, and the first address bit of the pointer is the ring buffer. When the pointer is updated at the last address, the first address bit of the pointer is returned to the head address of the ring buffer and the second address bit is inverted at the same time.

  According to this method, the ring buffer can be used efficiently without being left over, and the full and empty of the ring buffer can be easily detected without increasing the control sequence.

  According to the present invention, it is possible to efficiently use a ring buffer without leaving it, and to easily detect the fullness and emptyness of the ring buffer without increasing the control sequence.

  The essence of the present invention is that the write pointer and read pointer of the ring buffer are set to the number of bits obtained by adding 1 bit to the number of address bits determined from the buffer size, and when the pointer is incremented when the pointer is at the final address of the ring buffer, the pointer is changed. It is to prevent erroneous detection of the full or empty of the ring buffer by inverting the additional bit at the same time as moving to the head address of the ring buffer.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a ring buffer control device according to the first embodiment of the present invention.

  The ring buffer control device 100 includes a write control unit 101, a read control unit 102, a data bus 103, a ring buffer 104, a write pointer generation unit 105, a write pointer holding unit 106, a read pointer generation unit 107, and a read A pointer holding unit 108, a switching unit 109, and a comparison calculation unit 110 are mainly configured.

  The write control unit 101 writes data to the ring buffer 104 via the data bus 103 when a write event occurs. In addition, when the write event ends, the write control unit 101 notifies the write pointer generation unit 105 of the end of the write event.

  The read control unit 102 reads data from the ring buffer 104 via the data bus 103 when a read event occurs. When the read event ends, the read control unit 102 notifies the read pointer generation unit 107 of the end of the read event.

  The ring buffer 104 writes or reads data on the data bus 103 to the address output from the switching unit 109.

  When receiving a write event end notification from the write control unit 101, the write pointer generation unit 105 increments the value of the write pointer (WP) to update the WP, and outputs the WP to the write pointer holding unit 106 and the switching unit 109. Details of the operation of the write pointer generator 105 will be described later.

  The write pointer holding unit 106 holds the write address output from the write pointer generation unit 105 and outputs it to the comparison operation unit 110.

  When the read pointer generation unit 107 receives a read event end notification from the read control unit 102, the read pointer generation unit 107 updates the RP by incrementing the value of the read pointer (RP), and outputs it to the read pointer holding unit 108 and the switching unit 109. Details of the operation of the read pointer generation unit 107 will be described later.

  The read pointer holding unit 108 holds the read address output from the read pointer generation unit 107 and outputs it to the comparison operation unit 110.

  The switching unit 109 switches between the WP value (write address) output from the write pointer generation unit 105 and the RP value (read address) output from the read pointer generation unit 107 and outputs it to the address bus of the ring buffer. To do.

  The comparison operation unit 110 performs a comparison operation between the write address and the read address, and outputs the result to the write control unit 101 and the read control unit 102. Details of the operation of the comparison calculation unit 110 will be described later.

  Hereinafter, operations of the write pointer generation unit 105, the read pointer generation unit 107, and the comparison calculation unit 110, which are main parts of the present invention, will be described in detail with reference to FIGS.

  FIG. 2 shows the bit structure of the pointer and ring buffer.

  The write pointer and the read pointer have a configuration in which a bit (hereinafter referred to as “additional bit”) 201 having a 1-bit width is added to the upper part of the ring buffer address. For example, if the bit width of the address of the ring buffer is 10 bits, the bit width of the write pointer and the read pointer is 11 bits.

  FIG. 3 shows the ring buffer address corresponding to the pointer transition.

  The operations of the write pointer generator 105 and the read pointer generator 107 are the same. The ring buffer address portion of the WP and RP pointers excluding the additional bit 201 is incremented sequentially with the initial address 301 of the ring buffer as an initial value, and counts up to the final address 302 of the ring buffer. When the pointer reaches the final address 302, it is returned to the head address 301 of the ring buffer at the next count. At this time, the additional bit 201 is inverted.

  A specific example will be described. For example, as shown in FIG. 3, the ring buffer address has a 10-bit configuration in which the start address 301 is 000h and the final address 302 is 2FFh. As shown in FIG. 2, the pointer has an 11-bit configuration in which an additional bit 201 is added to the higher order. It is assumed that the initial value of the additional bit 201 is 0.

  When the value of the pointer is the final address 302 of the ring buffer, that is, 2FFh, in the next count, the lower 10 bits of the pointer are set to 000h which is the head address 351 of the ring buffer, and the additional bit 201 is inverted to 1. To do. That is, the pointer value is 400h. As the count proceeds further, the lower 10 bits of the pointer eventually becomes 2FFh of the final address 352 of the ring buffer, and becomes 6FFh together with the additional bit 201 (value is 1). In this case, in the next count, the lower 10 bits of the pointer are set to 000h which is the head address of the ring buffer, and the additional bit 201 is inverted to 0. That is, the pointer value is 000h.

  As a result, the pointer value is added from 000h to 2FFh, then becomes 400h, then added to 6FFh, and returned to 000h. At this time, since the ring buffer address is the lower 10 bits of the pointer, the corresponding ring buffer addresses are all from 000h to 2FFh.

  By managing the pointers in this way, it is possible to easily distinguish between full and empty ring buffers.

  The ring buffer becomes full when the lower 10 bits of the read address (RP value) and the write address (WP value) are equal and only the additional bit of the upper 1 bit is different. That is, for example, when RP = 1AAh, WP = 5AAh, or when RP = 5AAh, WP = 1AAh. Here, the ring buffer addresses corresponding to the pointer values 1AAh and 5AAh are both 1AAh.

  On the other hand, the ring buffer becomes empty when the read address and the write address are equal. That is, for example, when WP = 18Bh, RP = 18B, or when WP = 58Bh, RP = 58Bh. Here, the ring buffer addresses corresponding to the pointer values 18Bh and 58Bh are both 18Bh.

  Here, the comparison operation unit 110 calculates an exclusive OR (EXOR) between the bits of WP and RP. If the calculation result is 000h, the ring buffer is empty. If the result is 400h, the ring buffer is full. Otherwise, it can be said that both writing and reading are possible.

  By such processing, even when a read event occurs after the buffer becomes full by writing (WP and RP differ only in the upper 1 bit), but the read operation cannot be performed for some reason, the RP is read after the read event. Is not incremented but WP = RP. Therefore, in this case, it is not determined that it is empty (WP = RP).

  The same applies to the reverse case, and if the write event occurs after the buffer becomes empty (WP = RP) by reading, but the write cannot be performed for some reason, the WP is not incremented after the write event. = RP remains. Therefore, in this case, it is not determined that the full state (WP and RP differ by only the most significant 1 bit).

  If the initial value of the additional bits is 1, the ring buffer full and empty conditions are switched. That is, it is full when WP = RP, and it is empty when WP and RP differ by only the most significant 1 bit.

  Further, when the comparison operation unit 110 is configured by hardware, a write pointer and a read pointer can be input to the registers, and the full or empty of the ring buffer can be detected by the EXOR operation of the two registers. It is not necessary to have a small circuit scale.

  Further, in order to prevent erroneous detection of full and empty, it is not necessary to perform processing that does not use a part of the ring buffer area as a margin, and the entire ring buffer area can be used efficiently.

  In addition, if the bit width of the pointer is predetermined and the bit width of the ring buffer address is smaller than that, such as a general-purpose processor, if a higher bit that was not used conventionally is used, a flag is newly added. There is no problem that the control sequence for access such as writing to and reading from the flag register increases.

(Embodiment 2)
FIG. 4 is a block diagram showing a configuration of a ring buffer control device in inter-CPU communication using a dual port RAM. In the ring buffer control device 400 shown in FIG. 4, the same components as those in the ring buffer control device 100 shown in FIG.

  The ring buffer control device 400 shown in FIG. 4 is different from the comparison operation unit 110 in FIG. 1 in the operation of the comparison operation unit 401. Further, the transmission CPU 402 of the ring buffer control device 400 shown in FIG. 4 includes the function of the write control unit 101 and the function of the write pointer generation unit 105 of FIG. The reception CPU 403 of the ring buffer control device 400 shown in FIG. 4 includes the functions of the read control unit 102 and the read pointer generation unit 107 of FIG. The dual port RAM (DPRAM) 404 in FIG. 4 uses a part of the storage area as the ring buffer 104 in FIG.

  The transmission CPU 402 writes data to the DPRAM 404 when a write event occurs. When the write event ends, the transmission CPU 402 updates the WP by incrementing the value of the write pointer (WP), and outputs the WP to the write pointer holding unit 106 and the comparison operation unit 401.

  The reception CPU 403 reads data from the DPRAM 404 when a read event occurs. When the read event ends, the reception CPU 403 updates the RP by incrementing the value of the read pointer (RP), and outputs the RP to the read pointer holding unit 108 and the comparison calculation unit 401.

  The comparison operation unit 401 compares the WP held in the write pointer holding unit 106 with the RP held in the read pointer holding unit 108, and outputs an interrupt signal to the transmission CPU 402 or the reception CPU 403 depending on the comparison result. When WP = RP, the ring buffer is empty, and the comparison operation unit 401 outputs an interrupt signal indicating empty to the reception CPU 403. When WP and RP differ only by an additional bit (1 bit), the ring buffer is full, and the comparison operation unit 401 outputs an interrupt signal indicating full to the transmission CPU 402.

  With such a configuration, as shown in the first embodiment, WP and RP are managed by the number of bits obtained by adding 1 bit to the address bits necessary for managing the ring buffer.

  As a result, the sending CPU and the receiving CPU can easily and accurately detect the fullness or emptyness of the ring buffer by the interrupt signal, without comparing and managing the write pointer and the read pointer of the ring buffer provided on the DPRAM. . Moreover, such an apparatus can be realized with a small-scale hardware configuration.

  The present invention is suitable for use in a communication apparatus that performs efficient data transfer using a small buffer.

1 is a block diagram showing a configuration of a ring buffer control device according to a first embodiment of the present invention. The figure which shows the bit structure of the pointer and ring buffer address which concern on the said embodiment The figure which shows the address of the ring buffer corresponding to the transition of the pointer which concerns on the said embodiment The block diagram which shows the structure of the ring buffer control apparatus which concerns on Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Write control part 102 Read control part 103 Data bus 104 Ring buffer 105 Write pointer production | generation part 106 Write pointer holding part 107 Read pointer production | generation part 108 Read pointer holding part 109 Switching part 110, 401 Comparison calculating part 402 Transmission CPU
403 receiving CPU
404 DPRAM

Claims (5)

A ring buffer control device for controlling transfer of data using a ring buffer,
Write pointer generation means for generating a write pointer indicating a ring buffer address for storing transfer data next time,
Read pointer generation means for generating a read pointer indicating a ring buffer address of transfer data to be read next time,
The write pointer generation unit and the read pointer generation unit generate a pointer in which a second address bit not used in the ring buffer is added to a first address bit used in the ring buffer, respectively, and the first address bit of the pointer When the pointer is updated when is at the last address of the ring buffer, the first address bit of the pointer is returned to the head address of the ring buffer, and at the same time, the second address bit is inverted. Ring buffer controller.   An exclusive OR (EXOR) operation of the write pointer and the read pointer is performed, and when the operation result is that the first address bit is zero and the second address bit is 1, the remaining amount of the ring buffer is Comparing operation means for detecting zero and detecting that the amount of use of the ring buffer is zero when both the first address bit and the second address bit are zero is provided. The ring buffer control device according to claim 1. A ring buffer control device for transferring data from a transmission means as a data transfer source to a reception means as a data transfer destination using a ring buffer,
The comparison operation means outputs a first interrupt signal that warns the transmission means of an overflow of a ring buffer when the operation result is that the first address bit is zero and the second address bit is 1. 3. The ring buffer control device according to claim 2, wherein when the first address bit and the second address bit are both zero, a second interrupt signal indicating completion of data transfer is output to the receiving means. A communication device for transferring data between a first processor and a second processor using a dual port memory,
The first ring buffer control device according to claim 3, which is used for data transfer from the first processor to the second processor;
A second ring buffer control device according to claim 3, which is used for data transfer from the second processor to the first processor.
A first interrupt signal of the first ring buffer controller and a second interrupt signal of the second ring buffer controller are input to the first processor;
An inter-processor communication device, wherein a first interrupt signal of the second ring buffer control device and a second interrupt signal of the first ring buffer control device are input to the second processor.   A pointer is generated by adding a second address bit not used in the ring buffer to a first address bit used in the ring buffer, and the pointer is located when the first address bit of the pointer is at the final address of the ring buffer. In the ring buffer control method, when the first address bit of the pointer is returned to the head address of the ring buffer, the second address bit is inverted at the same time.

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