JP2000082009A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data processor which can switch endians during operation in a system where a big endian and a little endian are both prevent. SOLUTION: The processor has an arithmetic control means 110 which recognizes the byte order of a word in 1st, word order and is provided with an alignment means which is connected to the arithmetic control means 110 and can selectively switch the byte order of an output word to an input word between 1st word order and 2nd word order, and instructs the 1st word order or 2nd word order to the alignment means. Interruption control means 180 and 181 varies the value of a flag means 182 182 after saving the value of the flag means 182 in response to a specific interruption to the arithmetic control means, and reloads the saved value to the flag means 182 in response to a recovery from the interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus capable of processing data having different definitions with respect to the byte order in a word, which is one of information processing units, and for example, a CPU (Central Processing) formed on a semiconductor chip. Uni
t: Central processing unit) and DSP (Digital Signal Processo)
r: a digital signal processing device) and a technology effective when applied to a data processing system in which both big-endian and little-endian formats are used in combination.

[0002]

2. Description of the Related Art Big endian and little endian are known as a method of storing data in a memory or a form in which a processor transfers data between a register and a memory. For example, when storing 32-bit data at the address 4n (n is an integer of 0 or more) on the memory, the 32-bit data is divided into four for each byte (8 bits), and the uppermost byte of the data is allocated to the address 4n , 4n + 1 address, 4n
+2 address, 4n + 3 address in the order of big endian, from the least significant byte of data to 4n address, 4n
A method of storing addresses in the order of n + 1, 4n + 2, and 4n + 3 is called little endian. That is, the endian is a rule for determining the byte order in a word. When the byte address that matches the word address indicates the least significant byte of the word, it is little endian. Big endian is when the byte address that matches with points to the most significant byte of the word. The endian affects data in the same word in units of words and bytes. Which endian is adopted is selected depending on the architecture of the microprocessor or the data processor.

[0003] In recent years, hand-held personal computers (hereinafter, referred to as hand-held PCs) and personal digital assistants (hereinafter, referred to as PDAs) are equipped with operating systems (hereinafter, referred to as OSs) used in desktop personal computers and notebook personal computers. Is becoming mainstream. Since a system that performs such OS processing normally uses little endian, the data processing device to be used also needs to exchange data with a memory in the system in little endian. In systems such as digital mobile phones and personal handy phone systems (PHS), digital signal processing such as voice coding and decoding is processed by a digital signal processor (hereinafter referred to as DSP) that can execute multiply-accumulate operations at high speed. Then, processing such as a communication protocol and key operation is performed by a microcomputer. Since a system that performs such communication processing often uses big endian, a data processing device to be used also needs to exchange data with a memory in the system in big endian.

As an example of a document describing endian, refer to “Latest Microprocessor Technology (Nikkei B)
P company, published on May 10, 1996). There is a recent RISC (Redundancy Instructi
It is stated that the endian can be switched in the operation mode in the "on set computer" architecture.

[0005]

However, the above-mentioned prior art does not show how to switch the endian in accordance with the operation mode. For example, switching between big endian and little endian using a predetermined external pin of a microprocessor can be considered. In particular, the present inventor has studied switching between big endian and little endian while the processor is operating in a system in which both big endian and little endian formats are mixed. In the future, handheld PC and P
DA is expected to become more and more sophisticated, and the data processing device that is the core of the system is not only OS processing,
Various processes need to be performed. For example, a handheld PC or PDA having a data communication function. In this system, OS processing using little endian and communication processing using big endian need to be simultaneously installed in the system. At this time, if processing such as power-on reset is required every time switching between big endian and little endian, a system initialization program and various initial settings for power-on reset are performed every time switching between big endian and little endian. That is, when the communication processing and the OS processing are frequently switched, the processing amount increases.

An object of the present invention is to provide a data processing apparatus capable of dynamically switching the recognition of word order for information of a plurality of words as one of information processing units even during operation.

A more specific object of the present invention is to provide a data processing apparatus and a data processing system capable of performing endian switching even during operation of a system in a system in which both big endian and little endian formats are mixed. It is to provide a system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the data processing device (100) has operation control means (110, 111), and in terms of its architecture, stores information of a plurality of words, which is one of information processing units, in the first word.
Recognize in word order. For example, recognition of byte order in a word is performed in a first word order. The first word order is, for example, a big endian format. Regarding this architecture of the arithmetic control means, in terms of adaptation to a system including both big-endian and little-endian formats, first, a multi-word output for the multi-word input information connected to the arithmetic control means Alignment means (202 to 204) are provided which can selectively switch the word order of information in the first word order or the second word order. The second word order is, for example, a little endian format. Since the format conforming to the first word order, such as big endian, has the same format as the original architecture of the arithmetic control means, the alignment means may be made to select the first word order for the format of input data and output data. In order to convert data in a format conforming to the second word order such as little endian into a data format that can be supported by the original architecture of the arithmetic control means, the alignment means sets the second word order to the first word order. What is necessary is to convert the word order and supply it to the arithmetic and control unit, and to select the state where the output of the arithmetic and control unit is converted to the second word order. The selected state of the alignment means is determined by the value of the flag means (182).
The operation on the flag means uses interrupt control. That is, in response to a predetermined interrupt to the arithmetic control means, for example, a request for a subroutine process using data in a format conforming to the second word order such as little endian, the value of the flag means is saved, Change the value of the flag means, branch to the subroutine processing,
The saved value is returned to the flag means in response to the return from the interrupt. As described above, for example, in a system in which the OS processing using the little endian format and the communication processing using the big endian format are mixed, it is possible to dynamically switch the endian during the operation of the system.

The arithmetic control means includes a central processing unit (1) having an arithmetic logic unit and executing a fetched instruction.
10) and a product-sum operation device (111) that performs a product-sum operation under the control of the central processing unit can be formed on a single semiconductor substrate and employed. For example, the central processing unit performs OS processing, and the product-sum operation unit performs communication processing.

In a specific embodiment, the data processing device further includes a cache memory (112) and a work memory (1).
13, 114), a cache controller (115) for controlling the cache memory and the work memory in response to an instruction execution state of the central processing unit, a built-in peripheral circuit (118), and a response to an instruction from the cache controller. A bus state controller (1) for controlling access to the outside of the data processing device or the built-in peripheral circuit.
16). The alignment means may be provided in the cache controller. This alignment means is connected to the first bus (14) to which the cache memory, work memory, and bus state controller are connected.
2, 143, 144) and a second bus (220, 134B, 134) connected to the central processing unit and the product-sum operation unit.
C). In this aspect, the arithmetic control unit recognizes information of a plurality of words, which is one of the information processing units, in the first word order due to its architecture, but the first word order is stored in the cache memory, the work memory, and the external memory. And the information in the second word order can be mixed and arranged.

In another specific embodiment, the alignment means (202A, 203A) is arranged in the bus state controller (116A). At this time, the alignment means can be arranged between a third bus (151) to which the cache controller is connected and a fourth bus (163, 157) to be connected to the built-in peripheral circuit and the external bus. . In this aspect, the arithmetic and control unit may need to access the work memory or the like without passing through the alignment unit at all. Therefore, in this aspect, the cache memory and the work memory must be accessed in the first word order. The information in the first word order and the information in the second word order can be mixedly arranged on the external memory of the data processing device.

The data processing device is provided with a handheld P together with an external memory for storing program information and data information for the arithmetic control means of the data processing device.
A data processing system such as C or PDA can be configured.

[0015]

FIG. 1 shows a microprocessor 100 which is an example of a data processing apparatus according to the present invention, and one data processing system to which the microprocessor 100 is applied.

The microprocessor 100 is not particularly limited, but employs a reduced instruction set (for example, a 16-bit fixed-length instruction set) as a RISC processor.
PU 110 and DS capable of performing multiply-accumulate operations at high speed by executing operations and data load / store in parallel
It has P111.

The CPU 100 decodes the fetched instruction with an instruction decoder, and calculates address information and data information using a general-purpose register and an arithmetic and logic unit (ALU) according to the decoded result. The DSP 111 uses the DS
It has a decoder for decoding the P instruction, a multiplier, an arithmetic and logic unit (ALU), a data register file dedicated to the product-sum operation, and the like. Although not particularly limited, the CPU 110 controls access to data necessary for the operation of the DSP 111. D
The SP 111 inputs the data read from the memory under the access control of the CPU 110 and performs a signal processing operation. The operation result data output from the DSP 111 is a CP
It is stored in a memory or the like by the access control of U110.

The CPU 110 has a general-purpose register having a bit number of 32 bits or an integer multiple thereof,
The inside of the PU 110 is connected to a 32-bit data bus 133, and the register file and the arithmetic and logic unit
Data operation and address operation can be performed in bit units. At this time, the CPU 110 has an architecture that employs big endian in the byte order for 32 bits (1 word: 4 bytes). Therefore, in the data transfer between the internal general-purpose register and the external memory, the CPU 110 performs the data transfer and the data recognition so that the byte address matching the word address points to the most significant byte of the word.

The microprocessor 100 is compatible with a system in which both the big-endian format and the little-endian format are mixed, and is configured such that the endian can be switched dynamically during the operation of the microprocessor 110. Changing the byte order (word order) for endian switching is performed by the cache controller (CC
N) Perform 115. The cache controller 115 has system address buses (CAB, XAB, YAB) 120 to 12 in addition to the CPU 110 and the DSP 111.
2. System data bus (CDB, XDB, YDB) 1
42 to 144, and the internal address bus (IAB) 15
0 and the internal data bus (IDB) 151 are connected. The system address buses 120 to 122 and the system data buses 142 to 144 include a cache memory 112 for storing cache entries, a DSP 111
And an X memory 113 and a Y memory 114 used as a work memory of the CPU 110 are connected. A bus state controller (BSC) 116 is connected to the internal buses 150 and 151, and the BSC 116 is connected to a peripheral address bus (PAB) 165 and a peripheral data bus (P
DB) 157 controls the activation of a bus cycle optimal for accessing the peripheral circuits 117 and 118 connected to the external circuits. The external memory is connected to an external address bus (EAB) 162 and an external data bus (EDB) 163. The activation of an external bus cycle optimal for accessing an external circuit such as 101 is controlled.

FIG. 2 shows an example of the CCN 115.
The address comparison circuit 205 inputs the address output 132 of the CPU 110, and determines whether the access address is an address related to a cache hit or a cache miss with respect to the cacheable address area, or whether the access address is an address assigned to the internal memory. Is determined. As a result of the determination, if access to the peripheral bus or the external bus is required, a bus cycle for that is activated via the BSC 116. As a result of the determination, the cache memory 11
2. When accessing the X memory 113 and the Y memory 114, those memories are accessed via the built-in memory access circuit 206.

The CCN 115 has an endian switching circuit 201 and data rearranging circuits 202 to 204 for switching the endian. One of the input / output interface portions of the data rearranging circuits 202 to 204 is connected to the CPU 110 and the DSP 111 via buses 220, 134B, and 134C.
The other input / output interface part of the bus 204
Through 219 to the system data buses 142 to 144 and the internal data bus 154. The manner of rearrangement by the data rearrangement circuits 202 to 204 is controlled by a signal 215 output from the endian switching circuit 201.

FIG. 3 shows data rearranging circuits 202 to 20.
4, a detailed example is shown. In FIG. 3, the data bus 142 is 32 bits, and the signal line 142 is a byte unit.
A (most significant byte) to 142D (least significant byte) are shown. The data bus 143 is 16 bits, and shows signal lines 143A (upper byte) and 143B (lower byte) in byte units. The data bus 144 is also 16 bits, and the signal lines 144A (upper byte) and 144B (lower byte) in byte units are shown. The bus 220 is indicated by signal lines 220A (most significant byte) to 220D (least significant byte) in byte units, and the bus 134B is signal lines 134B-A (high byte) and 134B-B (low byte) in byte units. The bus 134C is indicated by a signal line 134C-
A (high byte), 134C-B (low byte). Reference numerals 301 to 308 denote selectors.

As described above, since the architecture of the CPU 110 is big-endian, the byte order on the bus 220 is 220A, 220B, 2
The order is 20C, 220D. Therefore, bus 14
When the big endian data of 2,143,144 is taken into the buses 220, 134B, 134C, or
When supplying big endian data to the buses 142, 143, 144, the buses 142, 143, 144
Of the buses 220, 134B and 134C so that the upper and lower levels of the buses 220, 134B and 134C correspond to each other.
What is necessary is just to control the selection state of 01-308. For example, 22
What is necessary is just to connect 0A to 142A, 220B to 142B, 220C to 142C, and 220D to 142D. This connection state (big endian selection state) is selected by the logical value “1” of the control signal 215. On the other hand, when the little endian data of the buses 142, 143, 144 is taken into the buses 220, 134B, 134C, or when the little endian data is supplied to the buses 142, 143, 144, the buses 142, 143, 144 are used. 1
44 and the buses 220, 134B, 134
The selectors 301 to 301 are arranged so that the upper and lower parts of C are reversed.
The selection state of 308 may be controlled. For example, 220A is 142D, 220B is 142C, 220C is 142
B and 220D may be connected to 142A. This connection state (little endian selected state) is controlled by the control signal 215.
Is selected by the logical value "0".

The logical value of the control signal 215 generated by the endian switching circuit 201 is determined by the signal 1
71. The signal is output from the interrupt control circuit (INTC) 117 shown in FIG.

In FIG. 1, an interrupt control circuit 117 includes an interrupt setting register 180, an interrupt determination circuit 181, an endian flag 182, and a flag state saving circuit 183.
Having. The signal 171 is the value of the endian flag 182.

The interrupt setting register 180 stores the BSC11
6, a register that can be written and read using PAB 156 and PDB 157. The CPU 110 sets the vector number of an interrupt (big-endian interrupt) request corresponding to processing using a big-endian data format. Is done. The endian flag 182 is set to a logical value “0” when the microprocessor 100 operates in the little endian selection state, and a logical value “1” when the microprocessor 100 operates in the big endian selection state.

An interrupt vector generation circuit 184 connected to the outside of the microprocessor 100 converts various interrupt requests 175 to the microprocessor 100 into an interrupt vector 173 and inputs the interrupt vector 173 to an interrupt determination circuit 181 inside the INTC 117. Interrupt determination circuit 18
1 is a comparison between the big endian interrupt vector number stored in the interrupt setting register 180 and the interrupt request vector number 173 generated by the interrupt vector generation circuit 184, and if the interrupt is a big endian interrupt, Then, the value of the endian flag 182 before the occurrence of the interrupt is saved in the flag state saving circuit 183, and “1” is set in the endian flag 182, and at the same time, the fact that the interrupt process has occurred is notified to the CPU 110 through the signal line 172. Endian flag 18
When 2 is set to the logical value “1”, the control signal 215 of the logical value “1” is transmitted to the data rearranging circuits 202 to 204 inside the CCN 115 through the endian flag signal 171.
To switch the data rearrangement circuits 202 to 204 to the big endian selection state. The big endian interrupt processing is completed, and the interrupt processing execution end signal 174 is output from the CPU 110 to the flag state saving circuit 1.
When input to the flag 74, the flag value saved in the flag state saving circuit 183 before the occurrence of the interrupt is stored in the endian flag 182. The value of the endian flag 182 is transmitted through the endian flag signal 171 to the CCN 115.
The data is transmitted to the internal data rearrangement circuit, and the data rearrangement circuit in the CCN 115 is changed to the state before the occurrence of the interrupt, ie,
Return to the little endian selection state. The flag state saving circuit 183 has a plurality of holding circuits before an interrupt occurs, and can cope with a new interrupt occurring during execution of the interrupt processing. The interrupt determination circuit can also perform a known interrupt control according to the interrupt priority level and the mask level.

For example, the little endian selected state can be used for OS processing, and the big endian selected state can be used for communication processing as a subroutine. At this time, data information and program information used for the OS processing are little endian. Communication data is assumed to be big endian. In such a case, if an interrupt of the big endian communication processing occurs while executing the little endian OS processing as described above,
When the value of the endian flag 182 of the INTC 117 is set to the logical value “1” by the endian switching circuit 201 and input to the endian switching circuit 201 through the signal line 171, the endian switching control signal 215 changes to the logical value “1”. And input to the data rearrangement circuits 202, 203, and 204. Each of the data rearranging circuits 202, 203, and 204 is switched from the little endian selection state to the big endian selection state in response to the logical value "1" of the endian switching control signal 215. Thus, data transfer between the register and the memory of the CPU 110 can be performed in big endian. When the interrupt routine of the communication process is completed, the value of the endian flag 182 is cleared to the logical value “0”, the information is input to the endian switching circuit 201 through the signal line 171, and the endian switching control signal 215 is set to the logical value “0”. Becomes
OS processing can be executed by switching from the big endian system to the little endian system. If another little endian interrupt occurs while executing little endian OS processing, the endian switching circuit 201 sends the endian flag 1 of the INTC 117 to the endian switching circuit 201.
Since the value of 82 does not change while maintaining the logical value “0”, the endian switching control signal 215 also maintains the logical value “0”, so that the processing is executed in the little endian system.
In this case, the value of the endian flag 182 does not change with the logical value “0” even when the interrupt processing is completed.
The next processing is also executed in the little endian system. As described above, since the state of the endian flag 182 before the occurrence of the interrupt is held, the endian can be correctly switched even if multiple interrupts occur.

The switching timing of the endian flag 182 is after the switching to the big endian selection state is completed after all the evacuation processing by interruption is completed. This is because if the endian is switched before the save processing is completed, the format of the processed data after restoration will not be constant. When switching to the little endian selection state, the endian switching process must be completed before the return process.

Next, the overall operation of the microprocessor 100 will be described in more detail. As described above, in the system of FIG. 1, the OS processing for performing data processing using data information and instruction information conforming to the little endian format, and the data processing using the data information and instruction information conforming to the big endian format are used. Communication processing that performs processing is mixed. In this system, OS processing is normally performed in accordance with little endian. When an interrupt occurs in communication processing, the data format is switched to big endian, and when returning from the interrupt, the data format is switched to little endian. CPU1
10 fetches an instruction from the cache memory 112 or the external memory 101, decodes the instruction with an internal instruction decoder, and controls each unit in the microprocessor 100 so that processing such as operation and memory access is executed according to the instruction. I do. The DSP 111 operates when an instruction decoded by the CPU 110 is an instruction that uses a multiplier or an ALU in the DSP 111. The general-purpose register of the CPU 110 also serves as an address pointer when the DSP 111 accesses the memory, and the X memory 113 and the Y memory 114
The address at the time of access using the XDB 143 and the YDB 144 is output to the XAB 121 and the YAB 122 through the CCN 115.

The memory access operation of the microprocessor 100 during execution of the little endian processing such as the OS processing is as follows. The CPU 110 outputs a memory address storing an instruction to be fetched from an address output 132 from an internal program counter or the like from an address output 132.
Output to CN115. CPU 110 in CCN 115
It is determined from the address received from the CPU whether the instruction to be fetched by the CPU 110 is stored in the cache memory 112. As a result of the determination, the CPU 110
The instruction to be fetched by the cache memory 112
If the instruction is stored in the cache memory 112, the address of the cache memory 112 in which the instruction is stored is output from the address output 136 to the CAB 120. Cache memory 112
Sends the instruction stored in the address portion received from the address input 137 to the CDB through the data input / output 145.
142. The instruction output to CDB 142 is C
The data input / output 133 passes through the CN 115 to the CPU 11
0 and decoded by the instruction decoder. Also,
As a result of the determination by the CCN 115, if the instruction to be fetched by the CPU 110 is not stored in the cache memory 112, the CCN 115 issues an external memory access request to the BSC 116 and simultaneously outputs an address from the address output 152 to the IAB 150. I do. BSC
116 receives the address from address input 153,
When the address indicates the external memory 101, the address output 164, the external address bus 162, the address input 1
Address through the external memory 1
When "02" is indicated, an address is supplied through the address output 164, the external address bus 162, and the address input 166. The external memory 101 transmits an instruction stored at a given address to the data input / output 168 and the external data bus 1.
63, input to the BSC 116 through the data input / output 167. The BSC 116 inputs the command received from the external memory 101 to the CCN 115 through the data input / output 155, the IDB 151, and the data input / output 154. CCN1
At 15, the little endian instructions are rearranged in big endian format by the internal data rearranging circuit in byte units as described above, and input to the CPU 110 through the data input / output 133. The CPU 110 decodes an instruction with an internal instruction decoder, and
00 is operated as instructed.

As a result of the instruction fetch and decoding, if the instruction is an instruction indicating memory access to a general-purpose register in the CPU 110, and if the instruction transfers data from the external memory 101 to the general-purpose register, the operation is performed in the same manner as the instruction fetch operation. It operates and data is input to a general-purpose register in the CPU 110. As a result of the instruction decode, if the instruction is to transfer data from the general-purpose register to the external memory 101, C
The address output from the address output 132 of the PU 110 and the write data output from the data input / output 133 are received by the CCN 115, and the data of the address to be written by the CPU 110 is stored in the cache memory 112.
It is determined whether it is stored in. If it is determined that the address to be written is stored in the cache memory 112, the address output 13 is output to the CAB 120.
6 and the write data output to the CDB 142 by the data rearranging circuit in the CCN 115 so that the data is rearranged into little endian data. Cache memory 112 has address input 1
37, and receives write data from the data input / output 145, and stores the write data in the specified address portion in the little endian system. If the address to be written is not stored in the cache memory 112 as a result of the determination by the CCN 115, the data is stored in the cache memory 112 by the same operation as described above, and at the same time, the CCN 115
An external memory access request is issued to 16. The CCN 115 outputs the address from the address output 152 to the IAB 150, and simultaneously outputs the address from the data input / output 154 to the IDB 151.
The data rearrangement circuit in the CN 115 outputs the write data that has been rearranged to be little endian data. The BSC 116 receives the address from the address input 153 and the write data from the data input / output 155, and outputs the address output 16 to the external address bus 162.
4 and the write data to the external data bus 163 through the data input / output 167. At the same time, a control signal 170 necessary for memory access is given to the external memory 101, whereby the external memory 101 receives an address from the address input 165, receives write data from the data input / output 168, and writes data to the designated address. Store.

As a result of instruction fetch and decoding, if the instruction is an instruction indicating data transfer to / from X memory 113 of a general-purpose register in CPU 110, the X memory address accessed from CPU 110 is output from address output 132 to CCN 115, The CCN 115 outputs the address to the CAB 120 through the address output 136 without performing the address determination. The X memory 113 receives the address from the address input 138, and stores, through the CDB 142 and the data input / output 146, the data that has been rearranged to the specified address by the data rearranging circuit in the CCN 115 so as to be little endian data. Or output little-endian data to exchange data with general-purpose registers in the CPU 110. When the instruction is an instruction indicating data transfer to / from the Y memory 114 of the general-purpose register in the CPU 110, the Y memory 114 operates in the same manner as in the case of the X memory access.
The address output to the CPU 20 is received from the address input 139, data is exchanged with the CDB 142 through the data input / output 149, and data is exchanged with the general-purpose register in the CPU 110.

As a result of the instruction fetch and decoding, if the instruction is an instruction indicating a memory access of a data register in the DSP 111 and the memory address to be accessed specifies the external memory 101, the memory access of the general-purpose register of the CPU 110 is performed. The memory access is executed by the same operation, and data is exchanged from the CCN 115 through the data input / output 134. When the memory address to be accessed specifies the X memory 113 or the Y memory 114, the CCN 115 does not perform the address determination and the CAB
The address is output from the address output 136 to 120.
The X memory 113 or the Y memory 114 receives an address from the address input 138 or the address input 139, and outputs the CDB1 through the data input / output 146 or 147.
The data rearranged by the data rearrangement circuit in the CCN 115 so as to be the data of the little endian system is stored in the address designated from 42, and the CDB 14
For example, data is read from the address designated as 2. When the memory of the data register in the DSP 111 is accessed using the CDB 142, the CCN 115 exchanges data for memory access through the data input / output 134.

If the result of the instruction decode indicates that the instruction indicates a parallel memory access using the X bus and the Y bus,
Two types of addresses, an X address and a Y address, are simultaneously output from the address output 132 of the CC 110 to the CCN 115. The CCN 115 does not perform the address determination on the two received addresses, and performs XAB through the X address output 130.
YAB 122 through Y address output 122
Output the respective address. X memory 113 stores X
The address is received from the address input 140, and XDB1 is received.
42, the write data received by the data rearranging circuit in the CCN 115 through the X data input / output 148 is rearranged so that the data becomes little endian data, and is stored in a specified location, or from the specified location. XDB1 through X data input / output 148
43. The Y memory 114 receives the address from the Y address input 141 and receives the write data from the YDB 143 through the Y data input / output 149, in which the data rearrangement circuit in the CCN 115 rearranges the data so that the data becomes little endian data. , And outputs data to the YDB 144 through the Y data input / output 149 from the specified location. At this time, the access to the X memory 113 and the access to the Y memory 114 are performed simultaneously. C
The CN 115 is connected to the DSP 111 through the data input / output 134.
To exchange data with

In the memory access operation of the microprocessor 100 during execution of the big endian processing such as the communication processing, except that the data rearrangement circuit in the CCN 115 does not rearrange the data in units of bytes, The operation is performed in the same manner as during the endian processing.

The operation of the CCN 115 during the execution of the OS process will be described in more detail. Since OS processing is being executed, INT
The endian flag 182 in C117 is “0”, and the endian switching circuit 201 is set to little endian by the signal line 171. Address output 132 from CPU 110 for instruction fetch
The address received through the address comparison circuit 20
5 is input. The address comparison circuit 205 determines whether an instruction to be fetched from the received address is stored in the cache memory 112.
As a result of the determination, if the instruction is stored in the cache memory 112, the address is sent to the internal memory access circuit 206 through the address output 210. The built-in memory access circuit 206 calculates an access control signal 211, an address output 136, a CAB 120,
The address is output to the cache memory 112 through the address input 137. The cache memory 112 stores the instruction stored at the received address in the data input / output 1
45, the CDB 142, and the data input / output 217, and input to the C bus access data rearranging circuit 202. C
The bus access data rearranging circuit 202 is controlled by the control signal 215 from the endian switching circuit 201.
The instructions in little endian format are rearranged in big endian format and selector 2 is passed through data input / output 220.
07. The selector 207 selects an output to the CPU 110 and, through the data input / output 133,
Input to U110. If the result of the determination by the address comparison circuit 205 indicates that the instruction to be fetched is not stored in the cache memory 112, the address comparison circuit 205 sends an external memory access request signal 214 to the BSC 116, and at the same time, outputs the IAB 1
The address is output to 50. CCN115 is BSC11
The instruction sent by accessing the external memory at 6 is input to the C bus access data rearranging circuit 202 through the data input / output 154 and the CDB 142. Similarly, the C bus access data rearranging circuit 202 rearranges the instructions in little endian format into big endian format and outputs the instructions to the selector 207 through the data input / output 217. The selector 207 selects an output to the CPU 110 and sends an instruction to the CPU 11 through the data input / output 133.
Enter 0.

As a result of the instruction fetch and decoding, if the instruction is to transfer data from the external memory 101 to the general-purpose register in the CPU 110, the same operation as in the above-described instruction fetch is performed. As a result of the instruction decoding, the CPU 11
If the instruction is to execute data transfer from the general-purpose register in 0 to the external memory 101, the data output from the CPU 110 through the data input / output 133 is the selector 207.
The data is output to the C bus access data rearranging circuit 202 through the data input / output 220. The C bus access data rearranging circuit 202 rearranges the data from the big endian format to the little endian format and outputs the data to the CDB 142 via the data input / output 217. At this time, the address comparison circuit 205 determines whether the address output from the CPU 110 through the address output 132 for memory access is stored in the cache memory 112, and if the address is stored in the cache memory 112, The data is output to the memory access circuit 206 through the address output 210. The built-in memory access circuit 206 receives the access control signal 211 and the address output 1
36, the CAB 137, and the address are output to the cache memory 112 through the address input 137. The cache memory 112 stores a CD in the portion designated by the address.
The little endian format data on B142 is stored. As a result of the determination, if the data is not stored in the cache memory 112,
At the same time as sending data to the external memory 101, the external access request signal 214 is sent to the BSC 116, an address is output from the address output 152 to the IAB 150, little endian data is output to the IDB 151 through the data input / output 154, and the data is output to the external memory 101. Is stored.

As a result of the instruction decoding, if the instruction is a data transfer instruction between the general-purpose register in the CPU 110 and the X memory 113 or the Y memory 114, the address output from the address output 132 of the CPU 110 to the address comparison circuit 205 is , And is input to the built-in memory access circuit 206 through the address output 210. X
In the case of accessing the memory 113, the X memory 113 sends the access control signal 21
2 and an address through address output 136, CAB 120 and address input 138, and data input / output 1
46, exchange little-endian data through the CDB 142. When accessing the Y memory 114, the Y memory 114 receives an access control signal 213 and an address output 13 from the built-in memory access circuit 206.
6, receives an address through the CAB 120 and the address input 139, and exchanges little-endian data through the data input / output 147 and the CDB 142.
The operation of the data rearrangement circuit 202 is the same as when data is transferred between the general-purpose register in the CPU 110 and the external memory 101 or 102.

As a result of the instruction decoding, when the instruction is a data transfer instruction between the dedicated data register in the DSP 111 and the external memory 101 or 102, the selector 207 sets the
1 except that the data input / output 134A is selected.
The operation is the same as when the data transfer instruction between the general-purpose register in the CPU 110 and the external memory 101 or 102 is executed. Also, when the instruction is a data transfer instruction between the dedicated data register in the DSP 111 and the X memory 113 or the Y memory 114, except that the selector 207 selects the data input / output 134A of the DSP 111,
The operation is the same as when a data transfer instruction between the general-purpose register in the U110 and the X memory 113 or the Y memory 114 is executed.

If the result of the instruction decode indicates that the instruction indicates a parallel memory access using the X bus and the Y bus,
The X address and the Y address received from the address 110 through the address output 132 are input to the address comparison circuit 205. The address comparison circuit 205 does not judge the address and inputs the address to the internal memory access circuit 206 through the address output 210. Built-in memory access circuit 20
Reference numeral 6 denotes an access control signal 212, an X address output 130, an XAB 121, and an X address input 140
Send the address through. At the same time, the access control signal 213, the Y address output 131, and the YAB1 are sent to the Y memory 114.
22, the address is sent through the Y address input 141.
X memory 113 has X data input / output 148, XDB 14
3. Data is exchanged with the X bus access data rearranging circuit 203 through the X data input / output 218 using the little endian system. At the same time, the Y memory 114 stores the Y data input / output 149, the YDB 144, and the Y data input / output 21.
9, the data rearranging circuit for Y bus access 20
4 and exchange data in little endian format. The X memory access data rearranging circuit 203 and the Y bus access data rearranging circuit 204
13 and the data transmitted from the Y memory 114 are rearranged, and the DSP is transmitted from the data input / output 134B or 134C.
111 and data input / output 1
The data output from the 34B or 134C is rearranged in the little endian format, and the XDB 143 or the YD
B144.

As described above, when performing the processing of the big endian format such as the communication processing, only the data rearrangement in the data rearrangement circuits 202, 203, and 204 is different, and otherwise, little endian. This is the same operation as when executing in the system. In this example, CP
Since the architecture of U110 is big-endian, it is not necessary to switch the upper and lower data positions at this time.

FIG. 4 shows a configuration of a microprocessor 400 having the data rearrangement circuit described in FIG. 1 in the BSC 116A. The cache controller 115A is not provided with the data rearrangement circuits 202 to 204. FIG. 5 shows an example of the data rearranging circuits 202A and 203A in the microprocessor 400. The basic configuration is the same as that of FIG. 3, and internal data buses 151A to 151D and external data buses 163A to 163 are provided.
D, a data rearranging circuit 202A is arranged between the internal data buses 151C and 151D and the peripheral data bus 15A.
7A and 157B, a data rearranging circuit 203A is arranged. 151A to 151D, 163A to 16
3D, 157A, and 157B indicate signal lines in byte units, respectively, and the relationship between the upper and lower bits is the same as in FIG.
The data rearrangement circuits 202A and 203A are configured by selectors 301A to 306A provided for each signal line in byte units. Selector 301 by signal 215
The operations of A to 306A are the same as those in FIG. 3. In the big endian selection state, the byte-based signal line is not switched between the upper byte and the lower byte. Swap bytes with lower byte. In this switching mode, C
The PU 110 may need to access the built-in memories 112 to 114 without passing through the data switching circuits 202A and 203A at all. Therefore, in the microprocessor 400 of FIG. 4, the internal memories 112 to 114 store information in a big endian format.
In the external memory 101, data information and instruction information can be arranged in a mixture of both big endian and little endian formats. In other words, the cache memory 112, the X memory 113, and the Y memory 11
Access to the built-in memory such as No. 4 is always executed in big endian format. Otherwise, the operation is the same as that of the microprocessor 100.

FIG. 6 shows an example of a handheld PC to which the microprocessor 100 is applied. The microprocessor 100 includes, as other peripheral modules 118, a timer 400, a keyboard interface 401,
It has a D / A converter 402, an A / D converter 403, an optical communication interface (IrDA) 404 for infrared rays, a serial communication interface (SCI) 405, a real-time clock (RTC) 406, and a clock pulse generator (CPG) 407. In FIG. 6, the microprocessor 100 further includes a memory management unit (MMU) 408 and a direct memory access controller (DMAC) 415.
The microprocessor 100 includes a keyboard 410 and a tablet (pen input device) 412 as input devices.
Are connected, and a speaker 411 is connected as an output device. The SCI 405 is connected to a communication line via a modem (not shown). The BSC11
6, external buses 162 and 163 are connected.
Although not particularly limited, PCMCIA (Personal Computer Memory C) 62 and 163 can be connected to a PC card.
ard International Association) card interface 420, miniature card interface 421, I / O port 422 such as a parallel port, color liquid crystal controller (color LCDC) 423 for controlling display driving of color liquid crystal display 424, and DRAM
And an external memory 101 such as a ROM.

In the handheld PC shown in FIG.
The little endian selection state is achieved when an interrupt for the optical communication process via the A404 is requested and when an interrupt for the serial communication process via the SCI 405 is requested. When returning from the communication process to the OS process, the big endian selection state is achieved.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, the basic architecture of the CPU is not limited to big endian, but may be little endian. Further, the circuit module included in the data processing device is not limited to the above description, and may include other circuit modules, or may delete appropriate peripheral circuit modules. The product-sum operation device is not limited to the DSP, but may be a floating-point operation unit.

[0048]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to dynamically switch the recognition of the word order for the information of a plurality of words, which is one of the information processing units, even during the operation. Specifically, in a system in which both big-endian and little-endian formats are mixed, the endian can be switched even during the operation of the system. For example, in a system in which OS processing using a little endian format and communication processing using a big endian format are mixed, it is possible to dynamically switch the endian during the operation of the system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a microprocessor as an example of a data processing device according to the present invention and an example of a data processing system to which the microprocessor is applied.

FIG. 2 is a block diagram illustrating an example of a cache controller including a data rearranging circuit.

FIG. 3 is a logic circuit diagram showing a detailed example of a data rearrangement circuit.

FIG. 4 is a block diagram illustrating an example of a microprocessor including a data rearrangement circuit in a bus state controller and a data processing system to which the microprocessor is applied;

FIG. 5 is a logic circuit diagram showing an example of a data rearrangement circuit included in the bus state controller.

FIG. 6 shows a handheld P to which a microprocessor is applied.
It is a block diagram showing an example of C.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Microprocessor 101 External memory 110 CPU 111 DSP 112 Cache memory 113 X memory 114 Y memory 115 Cache controller (CCN) 116 Bus state controller (BSC) 117 Interrupt controller (INTC) 118 Other peripheral modules 120 Cache address bus (CAB) 121 X address bus (XAB) 122 Y address bus (YAB) 142 Cache data bus (CDB) 143 X data bus (XDB) 144 Y data bus (YDB) 150 Internal address bus (IAB) 151 Internal data bus (IDB) 156 Peripheral address bus (PAB) 157 Peripheral data bus (PDB) 162 External address bus (EAB) 163 External data bus (EDB) 1 70 External memory access control signal 171 Endian flag signal 172 Interrupt generation signal 173 Interrupt request vector signal 174 Interrupt processing execution end signal 175 Interrupt request signal 180 Interrupt setting register 181 Interrupt determination circuit 182 Endian flag 183 Flag state saving circuit 184 Interrupt vector generation circuit Reference Signs List 201 endian switching circuit 202 data rearranging circuit for C bus access 203 data rearranging circuit for X bus access 204 data rearranging circuit for Y bus access 205 address comparing circuit 206 built-in memory access circuit 207 selector 210 CCN internal address bus 211 cache memory Access control signal 212 X memory access control signal 213 Y memory access control signal 214 External memory Li access request signal 215 endian switching control signals 301 to 308 selectors

Claims (7)

[Claims] 1. An arithmetic control unit for recognizing information of a plurality of words, which is one of information processing units, in a first word order, and connected to the arithmetic control unit to output information of a plurality of words with respect to the input information of the plurality of words. An alignment means capable of selectively switching the word order to a first word order or a second word order; a flag means for instructing the alignment means on the first word order or the second word order; Interrupt control means for changing the value of the flag means after saving the value of the flag means in response to the interrupt, and returning the saved value to the flag means in response to return from the interrupt; A data processing device comprising: 2. The arithmetic control means includes a central processing unit having an arithmetic and logic unit for executing a fetched instruction, and a product-sum arithmetic unit for performing a product-sum operation under the control of the central processing unit. 2. The data processing apparatus according to claim 1, wherein the data processing apparatus is formed on one semiconductor substrate. 3. The first word order is little endian, which is one mode of byte order for word information, which is one of the processing units of information processed by the central processing unit, and the second word order is the byte order. 3. The data processing device according to claim 2, wherein the data is big endian, which is another aspect of the order. 4. The first word order is big endian, which is one mode of byte order for word information, which is one of the processing units of information processed by the central processing unit, and the second word order is the byte order. 3. The data processing device according to claim 2, wherein the data is in little endian, which is another aspect of the order. 5. A cache memory, a work memory,
A cache controller that controls the cache memory and the work memory in response to an instruction execution state of the central processing unit, a built-in peripheral circuit, and an external or built-in peripheral circuit of a data processing device in response to an instruction from the cache controller A bus state controller that controls access to the cache memory; the cache controller includes the alignment unit; the alignment unit includes a first bus to which the cache memory, the work memory, and the bus state controller are connected; 3. The data processing device according to claim 2, wherein the data processing device is arranged between the processing device and a second bus connected to the product-sum operation device. 6. A cache memory, a work memory,
A cache controller that controls the cache memory and the work memory in response to an instruction execution state of the central processing unit, a built-in peripheral circuit, and an external or built-in peripheral circuit of a data processing device in response to an instruction from the cache controller And a bus state controller for controlling access to the memory. The bus state controller includes the alignment unit, the alignment unit includes a third bus to which the cache memory controller is connected, the built-in peripheral circuit, and an external bus. 3. The data processing apparatus according to claim 2, wherein the data processing apparatus is arranged between the first bus and a fourth bus. 7. A data processing device according to claim 5, further comprising an external memory for storing program information and data information for arithmetic control means of said data processing device. A data processing system characterized by the following.