JP3822885B2 - 1 chip data processor - Google Patents

Description

  The present invention relates to a data processing apparatus that executes an exception processing program to deal with an exception when an exception such as a reset, an exception event or an interrupt event occurs, and in particular, an exception process for dealing with the exception from the point of occurrence of the exception. The present invention relates to a technique for shortening the transition time until transition to a handler. The present invention relates to a technique effective when applied to, for example, a single chip microcomputer or a microprocessor incorporating a memory management unit.

  During data processing using the central processing unit included in the data processing device, decoding of undefined instructions not defined in the instruction set of the data processing device, generation of invalid operations, storage protection violation in virtual memory For notifying the central processing unit when a general exception event (general exception event) such as a TLB miss occurs, or when the data input / output operation in the external peripheral circuit of the data processing unit ends. An interrupt request (general interrupt event) such as an end notification or a reception request from a communication module in the data processing apparatus may occur.

  When an exception (exception event) such as the above general exception event or general interrupt event occurs, the central processing unit suppresses the execution of the instructions of the data processing program and handles the exception that has occurred. Control is transferred to, data processing specified by the exception handler is executed, and the generated exception is dealt with. After executing the exception handler, the central processing unit re-executes the instruction whose execution has been suppressed, or returns to the instruction address next to the instruction whose execution has been suppressed, and interrupted predetermined data processing. Continue the program. Therefore, when a general exception event or a general interrupt event occurs, the central processing unit executes an operation for saving the internal program counter value and the internal state of the status register to the stack area of the external memory. When the processing of the central processing unit returns from the processing of the exception processing handler to the inhibited data processing program, the central processing unit reads the value of the saved program counter and the internal state of the status register from the stack area of the external memory. The data processing program is stored in the program counter and the status register, and the suppressed data processing program is continued.

  As a branching method from the predetermined data processing program to the processing of the predetermined exception handler, various branch destination addresses (start memory addresses of various exception handlers) are fixed by hardware (logic circuit) A vector system is adopted that allows a branch destination address to be specified from a processing device. In the vector method, for example, a vector table storing the start addresses of various exception handlers for responding to interrupt requests is placed on the external memory, and the above-mentioned vector table pointer (interrupt vector register) is specified from the central processing unit. Read the start address of the corresponding exception handler from the specified vector table, and read and execute the required exception handler from the position of the read head address.

  Examples of documents describing exceptions such as an interrupt request include “Microcomputer Handbook” on pages 177 and 178 published on December 25, 1987.

“Microcomputer Handbook”, Ohm Co., Ltd., December 25, 1987, p. 177-178

  However, the above-described vector method requires an external memory read operation for acquiring the start address of the corresponding exception handler from the vector table before an exception event occurs and is dealt with. Therefore, it was found that the transition time from the occurrence of an exception event to branching to the corresponding handler becomes longer by the amount of the read operation of the external memory. If the program counter, status register, and general-purpose register data is saved to the stack area on the external memory before branching to the corresponding exception handler, the external memory write operation It was also found that the response to exceptional events was delayed.

  In particular, a high-speed response to an exception related to a TLB miss that occurs in synchronization with the operation of the central processing unit means that the time from the occurrence of a TLB miss to the re-execution of the suppressed instruction can be shortened. The present inventors have found that it is extremely important in improving the data processing performance of the central processing unit. This is because TLB misses are classified as exceptions, but in reality, unlike data exceptions that occur due to programming mistakes in user-created data processing programs, data processing programs without programming errors are being executed. It is an event that usually occurs in Therefore, dealing with TLB misses at high speed improves the data processing performance of the central processing unit.

  In addition, there is a method to fix various branch destination addresses completely by hardware. However, this method is inconvenient because it does not have the flexibility of mapping exception handling handlers related to user descriptions and the program size. . It is also considered that the amount of hardware for generating branch destination addresses will increase.

  An object of the present invention is to provide a data processing apparatus capable of shortening the transition time from the occurrence of an exception event to the transition or branching to an exception handling handler for dealing with it.

  Another object of the present invention is to provide a data processing apparatus capable of giving a degree of freedom to the configuration of an exception handling handler for responding to an exception event.

  Still another object of the present invention is to reduce the transition time to processing such as TLB miss exception, which is closely related to high-speed data processing, and to the exception processing. For exception events and interrupt events that are considered not to contribute to speeding up the data processing speed as much as the TLB miss exception, the exception handler and the memory size of the exception handler are highly flexible. It is an object of the present invention to provide a data processing device capable of having the characteristics.

  Another object of the present invention is to provide a low-cost and high-speed data processing apparatus that satisfies both the physical circuit scale reduction and the high-speed data processing in terms of exception processing.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  As illustrated in FIG. 1, the data processing apparatus responds to the occurrence of an exception event (for example, reset, general exception event, general interrupt request), and a memory circuit (in which an exception code assigned in advance to the exception event is written) (EXPEVT, INTEVT), program counter (PC), and in response to the occurrence of the exception event, a predetermined instruction address is written into the program counter, and the first exception handler assigned to the instruction address can be executed. A central processing unit (CPU) including control means (CTRL).

  The control means writes a second instruction address for branching from the first exception handler to the second exception handler according to the processing defined in the first exception handler. The factor code is used as an address offset for calculation, and the obtained second instruction address is set in the program counter.

  The branching to the predetermined instruction address is, for example, a vector point operation by hardware illustrated in FIG. The first exception handler assigned to the predetermined instruction address (branch destination vector point) is, for example, as shown in FIG. 2, a TLB miss exception process which is one general exception event unique to the vector point. An exception handling handler common to a handler or a plurality of exception events specific to the vector point (for example, a plurality of general exception events other than a TLB miss exception), or an exception handling handler common to a plurality of interrupts. In the common exception handler, the cause code is used as an address offset for branching to another exception handler (second exception handler) unique to each exception. The base address for the cause code (address offset) is determined by the description of the common exception handler. The base address is, for example, VBR (value of the vector base register) + H′100 (the symbol H ′ means a hexadecimal number), or the value of the program counter at the time of branching is used as the base address, Furthermore, it is possible to use a value calculated by appropriate calculation as a base address.

  If the above means is grasped from another point of view, the data processing apparatus uses a vector offset, which is a fixed offset with respect to the vector base address, as an exception in order to change the instruction execution order by the central processing unit in response to the occurrence of an exception event. Have fewer than the number of factors.

  The data processing device according to the present invention is executed after returning from the exception processing held by the first save register (SSR) in which the internal state of the status register is saved when an exception event occurs and the program counter (PC). A return instruction address indicating an instruction to be executed is included in a second save register (SPC) in which the address is saved. By employing the first and second save registers, the number of memory accesses to the external memory for saving the internal state of the status register and the return instruction address can be reduced.

  Further, the central processing unit of the data processing apparatus according to the present invention operates with an arithmetic logic circuit (ALU) and a predetermined value (in response to occurrence of the exception) for the vector point operation by hardware illustrated in FIG. A constant generation unit or calculation means (CVG, SFT) for generating a vector offset) and a base register (VBR) for storing base addresses of a plurality of exception handlers stored in an external memory. The arithmetic logic circuit adds the base address and the predetermined value under the control of the control circuit to generate the predetermined instruction address (branch destination instruction address). For example, according to FIG. 2, the vector offset of the general exception excluding the TLB miss exception is set to H′100, and the vector offset of the TLB miss exception is set to H′400. The constant generation unit includes a constant generation circuit (CVG) that generates a 2-bit constant, and a shift circuit (SFT) that shifts the 2-bit constant output from the constant generation circuit by a predetermined amount. The circuit configuration is simplified.

  A register as a storage circuit for recording a cause code includes a first register (EXPEVT) assigned to a first exception event (for example, a general exception) that occurs in synchronization with the operation of the central processing unit (CPU), and a central processing unit. A second register (INTEVT) assigned to a second exceptional event (for example, an interrupt) that occurs asynchronously with the operation of the apparatus is used. The reset is included in the category of the second exceptional event.

  The status register (SR) stores data that selectively indicates whether the operation state of the data processing device is a user state where the user program is running or a privileged state where the system program is running. A first control bit (MD), and a second control bit (BL) in which data indicating whether to accept or ignore (mask) other exception events that occur after the occurrence of the exception event is stored .

  The control means saves the internal state and the return instruction address to the first save register (SSR) and the second save register (SPC), respectively, and then stores data indicating a privileged state in the first control bit. The second control bit is set with data indicating that other exception events generated after the occurrence of the exception event are ignored, and the process branches to the first exception handler assigned to the predetermined instruction address. Access to the first and second control bits is made possible by a predetermined privileged instruction (for example, LDC, STC). That is, as illustrated in FIG. 2, the processor mode on the first exception handler assigned to the vector point is set to a privileged state and a state where multiple exceptions are suppressed. Here, the privileged state is a state in which an address space that is regarded as an address error in the user state can be accessed, and a privileged instruction (for example, LDC, STC) that cannot be executed in the user state can be executed. Different from user status.

  In order to allow the first and second save registers to save the internal state and save the return address when an exception occurs, on the first exception handling handler assigned to the vector point, multiple exceptions are generated. It is determined whether or not reception is to be suppressed and the contents are reflected in the control bit. When multiple receptions are received, the contents of the first and second save registers are saved in the memory.

  In order to reduce the memory saving of the general-purpose registers when an exception occurs or to improve the degree of freedom of processing for the general-purpose registers, first and second general-purpose register sets constituting a plurality of banks are provided. One of the first and second general-purpose register sets is used as a general-purpose register in the privileged state, and the other of the first and second general-purpose register sets is used as a general-purpose register in the user state. It is preferable that the register bank of the general-purpose register can be switched by software only in the privilege state.

  The data processing apparatus according to the present invention further includes an instruction break controller (UBC). The instruction break controller (UBC) includes an instruction break address register (IBR) in which a breakpoint address is set. When an instruction corresponding to the instruction address set in the instruction break address register is executed by the central processing unit, An instruction break exception is generated. The control means detects the instruction break exception without saving the internal state and the return instruction address to the first and second save registers when the instruction break exception is detected in a state instructed to suppress multiple exceptions. Branch to the handler. The instruction break exception handler saves the contents of the save register for saving the state and the return address in a memory, and then uses the breakpoint address held by the instruction break address register to return from the instruction break exception handler. The address is calculated, and the calculated return instruction address is written to the second save register. As a result, the instruction break exception can be processed by an exception processing handler in a state where the multiple acceptance of the exception is suppressed.

  In the above, when the control means further detects a first exception other than the instruction break exception in a state in which multiple acceptance of exceptions is suppressed, the control means records a reset exception after recording the cause code in the cause register. When the branch is made to the handler and the second exception is detected, the second exception is inhibited from being accepted until the state where the exception multiple inhibition is canceled.

  According to the above-described means, when the vector point is allocated, the first exception handling handler is made an exception handler unique to a certain exception factor (for example, TLB miss exception), and another exception factor (for example, TLB miss). General exceptions other than exceptions) for branching to a second exception handling handler (for example, an address error exception or a TLB protection violation exception) which is a different exception handling handler provided for each factor. A common exception handler that includes a description.

  In the former, since it is possible to branch to a specific first exception handler only by hardware processing without memory access, it is possible to shift to desired exception processing at high speed. In the latter, the exception factor code of the storage circuit (factor register) is used as an address offset for branching to another handler, so it is not necessary to access the address table in the memory to obtain the branch destination address. . Therefore, also in this case, a high-speed transition to a desired exception handling handler is possible.

  In other words, the exception cause code held in the cause register in the latter is assigned code so that it can be used as an address offset for branching to another exception handler. For example, code allocation is performed with an interval of H′20 corresponding to 32 bytes in address conversion.

  Further, in the latter, the exception cause code is used as an address offset for branching, so the base address for the offset can be freely set according to the description of the first exception handler assigned to the vector point determined by the hardware. The degree of freedom can be guaranteed with respect to the actual branch destination address and the size of the exception handling handler at the branch destination.

  Employing the registers (SSR, SPC) for saving the internal state and the return instruction address reduces memory access when saving when an exception occurs.

  When the operation clock frequency of the central processing unit is operated at a clock frequency that is a multiple of the operation clock frequency of the peripheral module that is the source of the interrupt request, it is generated in synchronization with the operation of the central processing unit. In order to cope with both the general exception as the first exception event and the interrupt request as the second exception event generated asynchronously, the register storing the exception cause code includes the first exception event and the second exception event. Separately for exception events. It is possible to avoid complicated processing for writing an exception factor code to a common register at the same timing when both exceptions occur.

  Making the initial processor mode on the branch destination handler (first exception handler) determined by the hardware according to the exception factor constant according to the exception event multiple acceptance suppression state and the privilege state is, A high degree of freedom can be guaranteed for the contents of exception handling that can be defined by the user on the handler.

  Making the register bank of a general-purpose register switchable by software only in the privileged state makes it possible to use a general-purpose register in a bank different from the user state in the privileged state. For example, in the exception processing, the processor is changed from the user state to the privileged state. When switching modes, it is not necessary to save the contents of the general-purpose register to the memory, and the transition to exception processing can be speeded up.

  Enabling an instruction break exception in an exception handler with an exception suppressed means that an instruction break can be placed at an arbitrary position even for a debug target program that is prohibited from receiving multiple exceptions. Can guarantee system evaluation and program debugging.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, the branch destination address is obtained by direct memory access in both the branch to the handler at the first vector point determined by the hardware and the branch from the handler to another handler with the cause code as an offset. Therefore, it is possible to shorten the transition time from the occurrence of an exception to the transition to the handler for dealing with it, thereby realizing an increase in the overall data processing speed of a data processing device such as a microcomputer.

  For processing such as TLB miss exception, which is closely related to high-speed data processing, exception processing is directly performed by an exception handler arranged at an address obtained by using a vector offset as a fixed offset. Therefore, the transition time to the processing for the TLB miss exception can be shortened. On the other hand, for interrupts, etc., where shortening of the transition time to exception processing is thought not to contribute to speeding up the data processing speed as much as TLB miss exceptions, improved usability in terms of handler mapping and flexibility in handler size Can be prioritized.

  Only some exception handlers (TLB miss exception handlers) of the exception handlers located at the address obtained by adding the value of the vector base register and the vector offset are directly exceptions to the corresponding exception. Perform processing. For other exceptions, the exception cause code is used as an address offset, and further branched to reach a predetermined handler. Therefore, it is possible to satisfy both a reduction in physical circuit scale and an increase in data processing speed.

  On the vector point handler defined by the hardware, it is decided whether or not to suppress the multiple exceptions that are newly generated, and when multiple exceptions are received, the contents of the save register are saved in the memory. State saving and return address saving at the time can always be saved registers, and also in this respect, the transition time from the occurrence of an exception to the handler for dealing with it can be shortened.

  When branching from a vector point handler determined by hardware to another handler, the cause code is used as an address offset for branching, so the base address for the offset is determined by hardware. It can be freely determined according to the description of the vector point handler, and the degree of freedom can be guaranteed for the actual branch destination address and the size of the branch destination handler.

  By adopting a register that saves the internal state and the return instruction address, memory access can be reduced when saving when an exception occurs.

  When dealing with both the first exception generated synchronously with the operation of the central processing unit and the second exception generated asynchronously, the peripheral module from which the central processing unit is the source of the interrupt request When operating at a clock frequency that is a multiple of the operating clock frequency, an exception factor code is provided for each of the first and second exceptions, thereby generating both exceptions. On the other hand, a complicated process for writing the factor code to the common register at the same timing can be avoided, and the process for setting the factor code in the register can be simplified.

  It is possible for the user to specify that the initial processor mode on the branch destination handler determined by the hardware according to the cause of the exception is constant with the exception multiple-rejection suppression state and privileged state on the handler. A high degree of freedom can be guaranteed for the contents of exception handling.

  By enabling the register bank of general-purpose registers to be switched by software only in the privileged state, it becomes possible to use a general-purpose register in a bank different from the user state in the privileged state. For example, processor mode from user state to privileged state in exception processing It is possible to avoid saving the contents of the general-purpose register to the memory when switching, and in this respect as well, the transition time from the occurrence of an exception to the processing for dealing with it can be shortened.

  By enabling an instruction break exception to be processed in an exception handler with the exception suppressed, an instruction break can be set at an arbitrary position even for a debug target program that is prohibited from receiving multiple exceptions. Can guarantee system evaluation and program debugging.

  << Outline of Microcomputer >> FIG. 1 is a block diagram of a single chip microcomputer (also referred to as a single chip microprocessor) according to an embodiment of the present invention. The microcomputer MPU shown in the figure is formed on a single semiconductor substrate or semiconductor chip such as single crystal silicon by, for example, a known semiconductor integrated circuit manufacturing technique. The microcomputer MPU includes, but is not limited to, a system bus S-bus, a cache bus C-bus, and a peripheral bus P-bus as internal buses. That is, the microcomputer MPU has a three-bus configuration. Each of the internal buses S-bus, C-bus, and P-bus includes a data bus for transferring data, an address bus for transferring address signals, and a control bus for transferring control signals.

  The system bus S-bus includes a central processing unit CPU, a multiplier MLT, a cache memory CACHE, a memory management unit MMU, and an instruction break controller (instruction break). controller) UBC is coupled. The cache memory CACHE, the memory management unit MMU, the instruction break controller UBC, and the bus state controller BSC are coupled to the cache bus C-bus. The peripheral bus P-bus connected to the bus state controller BSC has a timer TMU and a real-time clock circuit that enables a clock operation even when the operation clock supply to the central processing unit CPU is stopped. Serial communication between the RTC, the refresh controller REFC that controls the refresh operation of the dynamic memory included in the external memory MMRY, and the external peripheral devices provided outside the microcomputer MPU An internal peripheral module such as a serial communication interface SCI to be executed is connected. The bus state controller BSC is connectable to an external bus EX-bus via an input and output circuit EXIF. An external memory MMRY, an auxiliary storage device DISK and the like are connected to the external bus EX-bus. The bus state controller BSC performs activation of a bus cycle for the built-in peripheral module and the outside and various bus controls associated therewith.

  The interrupt controller INTC receives external interrupt requests from the built-in peripheral modules and multi-bit external interrupt terminals IRL0 to IRL3, and interrupt priority level. Follow the instructions to arbitrate interrupt requests. When the interrupt controller INTC permits the acceptance of the generated interrupt request, the interrupt controller INTC supplies the interrupt request signal SIG1 to the central processing unit CPU. The interrupt controller INTC notifies the interrupt factor of the accepted interrupt request to the control circuit (TLBC) of the memory management unit MMU by the interrupt factor signal SIG2. The central processing unit CPU that has received the interrupt request signal SIG1 supplies the interrupt permission signal SIG3 to the control circuit TLBC of the memory management unit MMU. In response to the interrupt permission signal SIG3, the control circuit TLBC of the memory management unit MMU writes an exception factor code (exception code) corresponding to the permitted interrupt request into an interrupt factor register INTEVT as a storage circuit described later. The control unit CTRL of the central processing unit CPU branches the process from the process of the data processing program being executed to a predetermined interrupt process by using the exception factor code set in the interrupt factor register INTEVT.

  The microcomputer MPU of the present embodiment divides a logical address space into units called logical pages, and performs address translation (address translation) into physical addresses for each page. Supports virtual memory to do. The address translation look-aside buffer TLB of the memory management unit MMU stores a plurality of translation pairs related to logical page numbers and physical page numbers as TLB entries. The control unit TLBC of the memory management unit MMU performs control for converting the logical address output from the central processing unit CPU into a physical address using the address conversion buffer TLB. In the case of a TLB miss, that is, when the translation pair corresponding to the logical address output by the central processing unit CPU is not stored in the address translation buffer TLB as a TLB entry, the control unit TLBC executes the page table on the external memory MMRY. And the conversion pair corresponding to the logical address is read from the external memory MMRY. Thereafter, the control unit TLBC operates to write the read translation pair as a TLB entry in the address translation buffer TLB.

  The address translation buffer TLB is configured by, for example, a 4-way-set-associative cache memory. When various exception events as described later relating to address translation such as a TLB miss occur, the control unit TLBC sets an exception factor code corresponding to the exception event in an exception factor register EXPEVT as a storage circuit described later, and A notification signal SIG4 for notifying the occurrence of an exceptional event related to address translation such as a TLB miss is supplied to the control unit CTRL of the central processing unit CPU. The central processing unit CPU uses the exception factor code set in the exception factor register EXPEVT, or directly executes the data processing in hardware without using the exception factor code set in the exception factor register EXPEVT. The process branches from the program process to the corresponding exception process.

  The central processing unit CPU uses, for example, a 32-bit address signal to support a 4-gigabyte logical address space. As shown in FIG. 1, the central processing unit CPU includes, for example, an operation unit 100 including general purpose registers R0 to R15 and an arithmetic and logic operation unit ALU, A system control register set 110 such as a program counter PC, which will be described later, and a control unit CTRL for fetching instructions, decoding instructions, controlling instruction execution procedures, and controlling operations Including. These circuit devices (R0 to R15, ALU, 110, CTRL) are coupled to the system bus S-bus. The central processing unit CPU fetches an instruction to be executed from the external memory MMRY, and performs data processing according to the instruction description (instruction code). In FIG. 1, a control signal SIG5 is a general term for various control signals from the central processing unit CPU to the memory management unit MMU and signals for notifying the internal state of the central processing unit CPU.

  The cache memory CACHE is not particularly limited, but has a 4-way set associative format. The index for the cache memory CACHE is performed using a part of the logical address output from the central processing unit CPU, and the physical address is held in the tag portion of the cache entry of the cache memory CACHE. The logical address output from the indexed tag portion is compared with the physical address converted by the address conversion buffer TLB, and a cache miss / hit is determined according to the comparison result. In the case of a cache miss, the data or instruction relating to the cache miss is read from the external memory, and the read data or instruction is stored in the cache memory CACHE as a new cache entry.

  The instruction break controller UBC is provided to enhance the debugging function, and monitors whether the state of the system bus S-bus matches the break condition. When the state of the system bus S-bus matches the break condition, a break interrupt is generated in the central processing unit CPU. The IBR included in the instruction break controller UBC is an instruction break address register in which an instruction address or the like is set as a break condition. The central processing unit CPU executes a service routine for that purpose before starting debugging or emulation, and presets desired instruction break conditions such as the start address and operand address of the instruction to be broken in the instruction break address register IBR. When the internal state of the microcomputer MPU matches the instruction break condition, an instruction break exception described later occurs. As a result, the central processing unit CPU can execute an instruction break handler for debugging. Therefore, breakpoint control can be performed inside the microcomputer MPU.

  << Register Configuration of CPU >> Next, a register configuration in the central processing unit CPU will be described. As shown in FIG. 3, the general-purpose registers R0 to R15 each have 32 storage bits and are coupled to the system bus via an interface circuit (not shown). The general purpose registers R0 to R7 are bank registers that are switched according to the processor mode. In other words, two sets of general-purpose registers R0 to R7, that is, bank 0 and bank 1, are provided. That is, R0 (BANK0) to R7 (BANK0) as the first general purpose register set and R0 (BANK1) to R7 (BANK1) as the second general purpose register set. The processor mode includes a user mode (user state) that means an operating state in which a user application program is run and a privileged mode (privileged state) that means an operating state in which a system program such as an operating system is run. ). Thus, each of the privileged state and the user state can have its own general purpose registers R0-R7. That is, in the user state shown in FIG. 4, the general-purpose registers R0 (BANK0) to R7 (BANK0) of the bank 0 are made available. In the privileged state, the usage form of the general-purpose registers R0 to R7 is determined by the setting state of a register bank bit RB (SR.RB) of the status register SR described later.

  For example, as shown in FIG. 5, in the privileged state, when RB = 0, R0 (BANK0) to R7 (BANK0) are allowed free use as general-purpose registers, and R0 (BANK1) to R7 (BANK1) Are only allowed to be accessed by a control load instruction (LDC) and a control store instruction (STC). When RB = 1, contrary to the above, R0 (BANK1) to R7 (BANK1) can be freely used as general-purpose registers, and control load instructions (LDC) are applied to R0 (BANK0) to R7 (BANK0). ) And control store instruction (STC). The control load instruction (LDC) and the control store instruction (STC) are examples of privileged instructions or system control instructions that can be executed in a privileged state.

  In this way, the general-purpose register is configured as a bank register, and in the privileged state, the general-purpose register in a bank different from the user state can be used. For example, when switching the processor mode from the user state to the privileged state in exception processing, the user state The contents of the general-purpose registers R0 to R7 that have been used for general purpose can be saved in the stack area of the external memory MMRY. Therefore, the shift to the exception processing of the central processing unit CPU can be speeded up.

  As shown in FIG. 3, the system registers are a data register high MACH, a data register low MACL, a return address register PR, and a program counter PC. The data register high MACH and the data register low MACL store data for multiplication, integration, and product-sum operations. The return address register PR stores the return address from the subroutine. The program counter PC indicates the start address of the current instruction.

  As shown in FIG. 6, the control registers are a save status register SSR, a save program counter SPC, a global base register GBR, a vector base register VBR, and a status register SR. The save status register SSR is a register that saves the current value of the status register SR when an exception event occurs. The save program counter SPC is a register for holding the instruction address of an instruction to be executed by the central processing unit CPU after returning from the corresponding exception processing when an exception event occurs. In the save program counter SPC, the value of the program counter PC is saved at a predetermined timing when an exceptional event occurs. The global base register GBR is a register that stores a base address in the GBR-indirect address mode. The GBR-indirect address mode is used when data is transferred to the register area of the built-in peripheral module such as the serial communication interface SCI or when a logical operation is performed. The vector base register VBR holds the base address (vector table base address) of the vector area for exception handling. The status register SR is a T bit that is used to indicate carry, borrow, and overflow in an operation, an S bit that is used for memory access control, an interrupt mask bit IMASK that indicates a mask level for an interrupt request in 4 bits, and a division bit that is used for division. M and Q bits, register bank bit RB, block bit BL, processor operation mode bit MD, and zero bit as described above. Block bit BL is used to mask exceptions, BL = 1 indicates masking exceptions, and BL = 0 indicates that exceptions are allowed. The mode bit MD indicates the privilege mode when MD = 1, and the user mode when MD = 0. The M, Q, S, and T bits can be set or cleared by the central processing unit CPU that has executed a predetermined dedicated instruction in the user mode. All other bits are readable and writable by the central processing unit CPU only in privileged mode. Writing to the control register is performed by a central processing unit CPU that executes a control load instruction (LDC), and reading to the control register is performed by a central processing unit CPU that executes a control store instruction (STC).

  << Microcomputer Address Space >> The microcomputer MPU of the present embodiment uses a 32-bit address to support a 4 GB (gigabyte) logical address space. The logical address is made expandable by a space number. FIG. 13 shows address mapping between the privilege mode address space and the user mode address space. In the figure, an area indicated as “Mapped” is an address conversion target using the address conversion buffer TLB.

  The area from H′FFFFFFFF to H′80000000 is an accessible area in the privileged mode, and an access in the user mode is an address error.

  The address area P4 is a control space to which control registers such as peripheral modules are mapped.

  The address areas P1 and P2 are areas having fixed physical addresses, and are not subjected to address conversion using the address conversion buffer TLB. The logical addresses in the address areas P1 and P2 are converted into physical addresses by addition or subtraction of a certain constant. Therefore, when the address areas P1 and P2 are accessed in the privileged state, an exceptional event related to address translation such as a TLB miss does not occur. By assigning physical addresses of various exception handlers, such as general interrupt events and general exception events, to the address area P1 or P2, exception events related to address translation such as TLB miss do not newly occur during exception processing. . In other words, it is possible to avoid the occurrence of multiple exceptional events related to address translation, thereby contributing to the efficiency of data processing.

  In particular, the address area P2 is not subject to caching by the cache memory CACHE, while the address area P1 is subject to caching. With regard to the exception handling handler, which exception handling handler among a plurality of exception handling handlers is assigned to the address area P1 or P2 is determined according to the nature of the exception handling. For example, an exception handling handler that requires high-speed processing, such as an exception handling handler for dealing with a TLB miss exception, is best allocated to the address area P1. On the other hand, an exception handler that does not require high speed exception handling is best allocated to the address area P2 in order to release the cache memory to other data.

  << Outline of Exception Processing >> Exception processing is processing that exceptionally branches the current program execution to another processing because special handling is required, and the central processing unit CPU executes the current instruction (the execution will be described later). The interrupt request is allowed to continue until completion), and responds to the exception handling request by transferring control to an exception handler written by the user. For example, exception handling can be classified into three processes in relation to the currently executing instruction. The first process is a process of ignoring the currently executing instruction and branching to the exception handler process. The second process is a process of re-executing the instruction currently being executed after completion of the exception handler process. The third process is a process of branching to the exception handler process after completing the execution of the currently executing instruction and returning to the state before the branch after completing the process at the branch destination. The latter two can be distinguished from a first exception event such as a general exception and a second exception event such as a so-called interrupt request. Since the second exception event such as an interrupt request occurs asynchronously with the operation of the central processing unit CPU, it is accepted at the stage where the instruction being executed is completed, and the exception handler corresponding to the interrupt process is processed. Is completed, the processing of the central processing unit CPU is returned to the instruction next to the instruction whose execution has been completed. Since the first exception event such as a general exception occurs in synchronization with the operation of the central processing unit CPU, after the cause of the request is removed, the central processing unit is issued when the exception processing request is issued. The instruction executed by the CPU is re-executed by the central processing unit CPU. However, it goes without saying that all exception handling does not match both definitions.

  FIG. 7 shows an exceptional event assigned as a vector. As shown in FIG. 7, exception processing is performed for reset processing, processing for exception events (general exceptions) that occur in synchronization with the operation of the central processing unit CPU, and interrupt requests that occur asynchronously with the operation of the central processing unit CPU. Broadly divided into processing. In each exception processing, as shown in the figure, the actions for the currently executing instruction are roughly classified into three types: Aborted, Retried, and Completed.

  1) The reset process includes a power-on reset (Power-On) and a manual reset (Manual Reset). For example, the power-on reset is a reset process that initializes the central processing unit CPU and the built-in peripheral module on condition that the reset signal is asserted when the power is turned on.

  2) General exceptions are broadly classified into exceptions that occur inside the central processing unit CPU and exceptions that occur during address translation by the memory management unit MMU.

  As the former exception events, there are a reserved instruction exception, a slot illegal instruction exception (Illegal Slot Instruction Exception), a trap instruction exception (Unconditional Trap), and an instruction break exception (User Breakpoint Trap).

  The latter exception events include an address error exception (Address Error) during instruction access and data access, a TLB miss exception (TLB Miss) during instruction access and data access, and a TLB invalid exception during instruction access and data access ( TLB Invalid), TLB protection violation exception (TLB Protection Violation) at instruction access and data access, and TLB initial page write exception (Initial Page Write).

  The TLB miss occurs when the address comparison of the address translation buffer TLB does not match, and the page table entry of the logical address related to the mismatch is loaded from the external memory MMRY to the address translation buffer TLB. The trap instruction exception occurs on condition that the TRAP instruction is executed, and performs processing defined by the branch destination handler using the immediate value of the instruction, and can be positioned as a software interrupt. The reserved instruction exception is generated under the condition that an undefined instruction code other than the delay slot is decoded when the delayed branch instruction is used, and the process specified by the branch destination handler is performed. An instruction break exception occurs on condition that the break condition set in the register IBR matches, and performs processing specified by the branch destination handler.

  3) Interrupt requests include non-maskable interrupts, external hardware interrupts, and peripheral module interrupts.

  The priority level (Exception Level) of exception processing is not particularly limited, but is defined as follows as shown in FIG. That is, reset is assigned to priority level 1, general exceptions are assigned to priority level 3, non-maskable interrupt requests are assigned to priority level 2, and other interrupt requests are assigned to priority level 4. The priority levels are 1 to 4 in descending order, the highest priority level is 1, and the lowest priority level is 4.

  Since the above general exception occurs in relation to the instruction execution sequence, priority level 3 is assigned. Various general exceptions assigned to priority level 3 are assigned execution priorities (Execution Order) of 1 to 12 in accordance with the early and late of the instruction execution stage. When an instruction is executed in a pipeline, certain general exceptions with priority level 3 detected during execution of an instruction precede other general exceptions with priority level 3 detected during execution of a subsequent instruction. To be accepted. Therefore, the execution priority is regarded as defining the priority within the execution span of each instruction. In particular, in the case of an instruction break exception (user break trap exception), when a trap is generated before execution of an instruction specified as a breakpoint, the execution priority of the instruction break exception is set to 1, and a trap is generated after execution The execution priority of the instruction break exception is 12, and the execution priority of the instruction break exception is 12 even when the operand breakpoint is set. The priority level between external interrupts and built-in peripheral module interrupts is defined by software.

  Note that one general exception in the general exception in FIG. 7 is illustrated so as to be distinguished between instruction access (Instr. Access) and data access (Data Access). This is because the description of general exceptions from Address Error to Initial Page Write in FIG. 7 describes exception factors according to the execution order when a certain instruction is executed in a pipeline manner. Therefore, TLB Miss (Instr. Access) and TLB Miss (Data Access) shown in FIG. 7 are processed by the same exception handler. The same applies to Address Error (Instr. Access) and Address Error (Data Access), TLB Invalid (Instr. Access) and TLB Invalid (Data Access), and TLB Protection Violation (Instr. Access) and TLB Protection Violation (Data Access) . In FIG. 7, the general exception is assigned to priority level 3 and the non-maskable interrupt request is assigned to priority level 2. However, priority level 2 is assigned to the general exception and non-maskable interrupt request is assigned. May be assigned a priority level of 3.

  << Vector Arrangement for Exception Handling >> Various exception handlers (collectively referred to as exception handlers) that define the contents of each exception handling are called using vector arrangement. The microcomputer MPU supports four types of vector arrangement depending on its hardware configuration. The fixed physical address H′A0000000 is assigned as a vector for reset. For other exception processing, a fixed address offset (vector offset) from the vector table base address set in the vector base register VBR by software is assigned. As shown in FIG. 7, the vector offsets are H'0000100, H'00000040, and H'00000600. H'00000400 is assigned to the vector offset of the TLB miss exception, H'00000100 is assigned to the vector offset of general exceptions other than the TLB miss exception, and H'00000600 is assigned to the vector offset of the interrupt request.

  The base address of the vector table is loaded into the vector base register VBR by the central processing unit CPU that executes software. For example, at the time of task switching or process switching, the vector base register VBR is set by a central processing unit CPU that executes a system program such as an operating system. The base address of the vector table is arranged in a predetermined fixed physical address space. That is, the base address of the vector table is arranged in the address areas P1 and P2. The vector point (vector address) determined by the value of the register VBR and the vector offset is defined by hardware. That is, the vector point is not of a nature defined by a program written by the user.

  FIG. 14 shows a hardware configuration for generating a vector offset value as the fixed offset. In the figure, the constant generation circuit CVG and the shifter SFT are regarded as a constant generation unit or a calculation means provided for generating a vector offset. The addition of the vector offset value and the vector base register VBR value is performed by the arithmetic logic unit ALU, and the vector point obtained by the addition is written to the program counter PC. Thereafter, the central processing unit CPU generates the vector point (logical address) to the address bus in the system bus S-bus in order to access the exception handling handler assigned to the vector point written in the program counter PC. . When the memory management unit MMU receives the logical address as the vector point and stores an address translation pair related to the logical address as an entry, the memory management unit MMU converts the logical address into a physical address and supplies it to the cache memory CACHE. . When there is no instruction corresponding to the physical address in the cache memory CACHE, the physical address passes through the address bus of the cache bus C-bus, the bus state controller BSC, the input / output circuit EXIF, and the address bus of the external bus EX-bus. And supplied to the external memory MMRY. In synchronization with the output of the physical address to the address bus of the external bus EX-bus, a read control signal (not shown) output from the central processing unit CPU is sent to the control bus and cache bus C in the system bus S-bus. The external memory MMRY supplied to the external memory MMRY via the bus control bus, bus state controller BSC, input / output circuit EXIF, and external bus EX-bus control bus is read-accessed by the physical address, The data stored at the physical address (the first instruction data of the first exception handler) includes the data bus of the external bus EX-bus, the input / output circuit EXIF, the bus state controller BSC, the data bus of the cache bus C-bus, and Via the data bus in the system bus S-bus Is supplied to the processing unit CPU is executed.

  The constant generation circuit CVG, shifter SFT, and arithmetic logic unit ALU for generating vector points set in the program counter PC are included in the arithmetic unit 100 of the central processing unit CPU.

  The constant generation circuit CVG and the shifter SFT are supplied with an interrupt notification signal SIG1, a notification signal SIG4a indicating the occurrence of a TLB miss exception, and a notification signal SIG6 indicating the occurrence of a general exception other than a TLB miss exception. The notification signal SIG4a is one signal included in the signal SIG4 output from the control unit TLBC in the memory management unit MMU. That is, the signal SIG4 includes a signal of a plurality of bits, and as described above, is a signal for notifying the central processing unit CPU of the occurrence of an exception due to address translation in the memory management unit MMU. The signal SIG4 includes a notification signal SIG4a indicating that the exception event that has occurred is a TLB miss exception, a notification signal SIG4b indicating that the exception event that has occurred is an exception event other than a TLB miss exception, and the like. As shown in the figure, the notification signal SIG6 includes the signal SIG4b which is activated when an exception event other than a TLB miss exception occurs during address conversion in the memory management unit MMU, and an exception event has occurred in the central processing unit CPU. The output signal of the OR circuit OR which receives the internal signal SIG6a activated at this time.

  In the constant generation circuit CVG and the shifter SFT, the constant to be generated and the shift amount are controlled based on which of the signals SIG1, SIG4a, SIG6 is activated. The constant generation circuit CVG generates, for example, a 2-bit constant H′1 (01) or H′3 (11) in binary code. The constant generation circuit CVG generates a constant H′1 when the notification signal SIG4a or the notification signal SIG6 is activated. The constant generation circuit CVG generates a constant H′3 when the interrupt generation notification signal SIG6 is activated. When the notification signal SIG6 is activated, the shifter SFT outputs a vector offset H′100 (1.00000.0000) by shifting the constant H′1 (01) by 8 bits to the left. When the TLB miss exception notification signal SIG4a is activated, the shifter SFT outputs a vector offset H′400 (100.0000.0000) by performing a 10-bit left shift on the constant H′1 (01). . When the notification signal SIG1 is activated, the shifter SFT outputs a vector offset H′600 (110.0000000.0000) by shifting the constant H′3 (11) by 9 bits to the left. In particular, in the present embodiment, H′100, H′400, and H′600 are assigned as vector offsets in order to minimize the number of bits set to the logical value “1” in the vector offsets. This is because the logic scale of the constant generation circuit CVG is reduced.

  As apparent from FIG. 14, since there are three types of vector offsets to be generated by hardware (circuit), the amount of hardware is only a 2-bit constant generation circuit CVG and a shifter SFT. The shifter SFT is not necessarily dedicated to the generation of the vector offset, and can easily be used for other operations.

  << Exception factor code indicating exception handling >> As shown in FIG. 8, the exception code has a different value for each exception event so that each exception handling factor can be identified. An exception cause code is assigned. This exception factor code is used for determining the cause of the exception that has occurred in software or the like in debugging, and is also used as address offset information for branching to an exception handler, as will be described later. Registers EXPEVT and INTEVT are coupled to the cache bus C-bus and are accessible from the outside of the microcomputer MPU via the bus state controller BSC, the input / output circuit EXIF and the external bus EX-bus for use in debugging. To be. That is, the factor codes stored in the registers EXPEVT and INTEVT can be output to the outside of the microcomputer MPU. As a result, the debugger can easily determine the cause of the exception that has occurred from the factor code.

  The exception cause code shown in FIG. 8 is assigned for each H′20. If this is converted into an address, it has a meaning as an address offset every 32 bytes. For example, if one instruction is a fixed-length instruction of 2 bytes, the address range corresponds to the description of 16 instructions. In FIG. 8, among general exceptions, load instruction execution is performed for an address error exception (Address Error), a TLB miss exception (TLB Miss), a TLB invalid exception (TLB Invalid), and a TLB protection violation exception (TLB Protection Violation). Different exception cause codes are assigned at the time of loading (load) and at the time of executing store instruction (store). This is set in consideration of ease of debugging. In FIG. 8, only one factor code H′400 is typically shown as the exception factor code related to the interrupt request of the built-in peripheral module. However, it should be understood that there are actually many depending on the number of built-in peripheral modules and their functions.

  The exception factor register EXPEVT shown in FIG. 9 is a 32-bit register that stores exception factor codes assigned to reset and general exception events in the above-mentioned exception factor codes in bits 11 to 0. On the other hand, the interrupt factor register INTEVT is a 32-bit register that stores the exception factor code assigned to the interrupt request among the exception factor codes in bits 11 to 0. As shown in FIG. 1, these registers EXPEVT and INTEVT are coupled to the system bus S-bus and the cache bus C-bus, and are arranged in the control unit TLBC of the memory management unit MMU. The reason is that it is the control unit TLBC of the memory management unit MMU that can detect the occurrence of a general exception requiring high-speed processing such as a TLB miss the earliest.

  The reason why a register for storing an exception factor code is separately provided for a general exception and an interrupt request is as follows. That is, the general exception is generated in synchronization with the operation of the central processing unit CPU, and the interrupt request is generated asynchronously with the operation of the central processing unit CPU. Further, the operation clock frequency of the central processing unit CPU is set to a multiple of, for example, four times the operation clock frequency of the built-in peripheral modules and external circuits that are the generation sources of interrupt requests. In this way, when considering the difference between the generation timing of interrupt requests and general exceptions, and the difference in operating speed between the interrupt request generation source and the exception generation source, both exception cause codes are stored in the same register at the same timing. This is because the writing process of setting the exception factor code write timing to the register may be complicated.

  FIG. 15 shows a configuration of a logical block for generating the exception cause code. The logic circuit LOG shown in the figure is included in the control circuit TLBC of the memory management unit MMU. The logic circuit LOG is supplied with an interrupt factor A, an exception occurrence situation B inside the central processing unit CPU, an exception occurrence situation C inside the memory management unit MMU, a reset instruction D, and other incidental information E. A corresponding exception cause code is generated according to the information status.

  The interrupt factor A is supplied from the interrupt controller INTC to the logic circuit LOG by the signal SIG2. The other incidental information E includes the interrupt acceptance notification signal SIG3. In response to the activation state of the interrupt factor A and other incidental information E, the logic circuit LOG generates an exception factor code corresponding to the interrupt factor, and sets the generated exception factor code in the interrupt factor register INTVT.

  Exception occurrence status B in the central processing unit CPU includes a reserved instruction exception, an illegal slot instruction exception, a trap instruction exception (Unconditional Trap), and an instruction break exception (User Breakpoint Trap). ) Is supplied from the central processing unit CPU to the logic circuit LOG as a multi-bit signal for distinguishing the occurrence status of The exception occurrence situation B is considered to be included in the control signal SIG5 shown in FIG.

  Exception occurrence status C in the memory management unit MMU includes an address error exception (Address Error), a TLB miss exception (TLB Miss), a TLB invalid exception (TLB Invalid), a TLB protection violation exception (TLB Protection Violation), and a TLB initial page. It is supplied to the logic circuit LOG as a multi-bit internal signal for distinguishing the occurrence status of the write exception (Initial Page Write).

  The accompanying information E includes information for distinguishing whether an instruction relating to address translation is a load instruction or a store instruction. This information is obtained from the result of decoding the instruction to be executed in the central processing unit CPU, and is supplied from the central processing unit CPU to the logic circuit LOG.

  The logic circuit LOG generates an exception factor code corresponding to the generated general exception based on the exception occurrence situation B in the central processing unit CPU, the exception occurrence situation C in the memory management unit MMU, and the incidental information E. And the generated exception cause code is set in the exception cause register EXPEVT.

  An exception factor code related to reset is generated by the logic circuit LOG in response to the reset instruction D formed by the reset signal. The generated exception cause code relating to the reset is set in the exception cause register EXPEVT by the logic circuit LOG. The reset instruction D is considered to be included in the control signal SIG5 shown in FIG.

  << Arrangement of Exception Handler >> The vector offset defined by H′100, H′400, and H′600 defines a fixed offset from the value of the vector base register VBR (base address of the vector table). As shown in FIG. 2, the exception handler relating to reset is arranged at a fixed address of H′A00000000. The exception handler related to the TLB miss exception is directly arranged at the address of the value of the register VBR + the vector offset (H′400). The exception handler for other general exceptions and interrupt requests is the first handler (common to the general exceptions shown in FIG. 2) at the address position obtained by adding the vector offset of H′100 or H′600 to the value of the register VBR. Handlers and handlers common to interrupt requests). Branching from the first handler to another second handler specific to the factor is performed by using the exception factor code stored in the register EXPEVT or INTEVT as an address offset.

  How to use the exception factor code as the address offset is determined by the description contents (software program) of the handler (by user description) arranged at the position of the vector base register VBR + vector offset. For example, it is specified to branch to the second handler as VBR + vector offset + exception cause code, or to branch to the second handler by adding the exception cause code to the base address set in the handler. Or, it can be specified that the exception cause code is shifted by a predetermined number of bits and branched to the second handler. In short, since each exception factor code is allocated with a predetermined interval such as H′20, the exception factor code may be used as desired according to the description amount of the handler. When the exception cause code stored in the register EXPEVT or INTEVT is used as an address offset, the central processing unit CPU supplies the address signal of the register EXPEVT or INTEVT to the address bus of the system bus S-bus, and the system bus S-bus A read control signal is supplied to the control bus to access the register EXPEVT or INTEVT. The read-accessed register EXPEVT or INTEVT supplies the factor code stored therein to the data bus of the system bus, and the CPU stores the factor code in, for example, one general-purpose register (R0). Thereby, the central processing unit CPU can use the factor code for calculation. The actual calculation is performed by the arithmetic logic unit ALU in the central processing unit CPU.

  For example, as shown in FIG. 2, for an exception handler for a general exception other than a TLB miss exception, the first handler common to the general exception is placed at the vector point of VBR + vector offset (H′100). Is done. The first handler has a description that specifies that an exception factor code corresponding to the exception factor is branched to another handler (second handler) as an address offset. Therefore, it is possible to branch to a desired second handler by placing a second handler specific to the exception factor at each address obtained by adding the exception factor code to the vector point. In this case, the exception cause code is acquired from the register EXPEVT.

  The exception handler related to the interrupt request is the same as described above, and the first handler common to the interrupt request is arranged at the vector point of VBR + vector offset (H′600). The first handler has a description that prescribes branching to another handler (second handler) using the cause code corresponding to the interrupt cause as an address offset. Therefore, it is possible to branch to a desired second handler by placing a second handler specific to the interrupt factor at each address obtained by adding the exception factor code to the vector point. In this case, the exception factor code of the interrupt request is acquired from the register INTEVT.

  According to this embodiment, since various exception handlers are assigned to the address area P1 or P2 that does not require address translation using TLB, it is possible to avoid a situation in which multiple exception events related to address translation occur. This can contribute to efficient data processing.

  In the exception handler arrangement as described above, when a TLB miss exception, other general exception, or an interrupt request occurs, the processing of the central processing unit CPU performs a vector offset to the base address of the vector table set in the VBR register. Branch to the address position added as an offset address, and the handler arranged at that address position is processed. This branch is defined by the hardware of the microcomputer MPU. At this time, which vector offset is used is uniquely determined by the type of the cause of the exception as described with reference to FIG. When the generated exception is a TLB miss exception, the handler assigned to the vector point specified by VBR + vector offset (H′400) is regarded as a TLB miss exception handler. In the case of other general exceptions or interrupt requests, the vector point handler specified by VBR + vector offset includes a process that branches using the cause code of the exception cause as an offset, and the branch destination has a handler specific to the exception cause. Has been placed.

  For trap exceptions that occur when a trap instruction is executed, the 8-bit immediate value held by the trap instruction is stored in the trap register TRA shown in FIG. 9, and the value is stored in the lower address data of the VBR register. The corresponding exception handler is fetched according to the value obtained by the addition. The trap instruction exception is used, for example, for a system call from a task in the user program to the operating system.

  << Exception Processing Flow >> FIG. 10 shows a flowchart of processing for branching to a vector point by the vector offset. As described in FIG. 14, the branch to the vector point is a process defined by the hardware of the microcomputer MPU and positioned as a transition to the privileged state, and includes the following steps.

  [Detection of Exception / Interrupt] When a reset, a general exception, or an interrupt request is generated, it is detected by the control unit CTRL (S1). For example, the control unit CTRL generates an interrupt request such as a reset signal generated by a reset switch operation in the case of a manual reset, and a TLB miss detection signal output from the control circuit TLBC of the memory management unit MMU in the case of a TLB miss exception. If there is, an exception is detected based on the interrupt signal SIG1 supplied from the interrupt controller INTC to the central processing unit CPU. An exception in the central processing unit CPU is detected based on its internal state.

  [Saving PC and SR] Next, the central processing unit CPU saves the value of the program counter PC to the save program counter SPC, and saves the value of the status register SR to the save status register SSR (S2). In the case of a general exception, the save timing is the time when the exception occurs. Therefore, the address of an instruction that has not been executed is saved, and the instruction is re-executed after returning. The timing of saving in the case of an interrupt request is that when the interrupt request is generated, the above two values are saved after the central processing unit CPU waits for the execution of the instruction executed at that time. As a result, the address of the instruction next to the instruction is saved. As a result, when an exception occurs, it is not necessary to access the memory to save the value of the program counter PC or the value of the status register SR to the stack area on the memory, and only the internal register access is required. Evacuation processing can be performed at high speed.

  [Switching of processor mode] The central processing unit CPU sets the mode bit MD of the status register SR to a logical value 1, and sets the operation mode of the microcomputer MPU to the privileged mode (S3). The central processing unit CPU further sets the block bit BL of the status register SR to the logical value “1” to mask other exceptions and interrupts (S3). The central processing unit CPU further sets the register bank bit RB of the status register SR to a logical value 1, and switches the general purpose registers R0 to R7 in the privileged state to a register bank different from the user state (S3). Therefore, since the bank switching of the general purpose registers R0 to R7 is performed, the processing for saving the general purpose registers R0 to R7 of the register bank in the user state is not necessary.

  [Set of Exception Factor] Next, the exception factor code assigned to the exception or interrupt request factor at that time is set in the register EXPEVT or INTEVT as described in FIG. 15 (S4). A general exception factor or reset factor code is set in the former register EXPEVT, and an interrupt request factor code is set in the latter register INTEVT by the logic circuit LOG in the MMU.

  [Branch to Vector Point] As described above, the control of the central processing unit CPU branches to a predetermined vector point (S5). If the exception processing is reset, the process branches to a fixed address H′A00000000. In the case of a general exception or an interrupt request, the control of the central processing unit CPU branches to an address obtained by adding a predetermined vector offset to the vector table base address of the register VBR. As shown in FIG. 2, a predetermined handler is placed at the branched vector point. In the case of reset, an exception handler for reset is arranged, and in the case of TLB miss exception, a TLB miss exception handler for TLB entry update or the like is arranged (see FIG. 2). In the case of a general exception other than a TLB miss exception, or in the case of an interrupt request, a handler including processing for branching to another handler specific to the exception factor (a handler common to the general exception shown in FIG. Common handler) is placed.

  When a TLB miss exception occurs during instruction execution, the physical page address corresponding to the logical page address related to the TLB miss is read from the page table on the external memory MMRY, the address translation buffer TLB is updated, and the conversion to the physical address is performed. Since it must be performed, the transition time from the occurrence of the TLB miss exception to its handling greatly affects the instruction execution speed or the data processing speed by the central processing unit CPU. Therefore, placing the TLB miss exception handler, which is considered to have the greatest influence on the data processing performance, directly at the vector point significantly reduces the processing time until the control of the central processing unit CPU is transferred to the exception handler. Thereby, the data processing speed of the microcomputer MPU can be increased.

  FIG. 11 shows an example of a processing flow of an exception handler (excluding a reset handler and a TLB miss exception handler) placed at the vector point. As described above, this process is defined exclusively by software and includes the following processing steps.

  First, it is determined whether or not another exception or interrupt request that occurs later is received in a multiple manner (S11). The decision follows the description of the handler.

  If multiple interrupt requests are not accepted, an exception factor code is read from the registers EXPEVT and INTEVT (S12), and processing for branching to a corresponding exception handler is performed using the exception factor code as an address offset ( S13). The central processing unit CPU executes the calculation of VBR + vector offset + exception cause code, and the processing is shifted to the exception handler assigned to the calculated address, that is, the branch destination exception handler. Thereby, the central processing unit CPU handles the exception that has occurred.

  When accepting multiple interrupt requests or the like, the central processing unit CPU uses the data of the registers used in the handler of FIG. 10 such as the save status register SSR and the save program counter SPC in order to guarantee the processing flow described in FIG. Save to the external memory MMRY (S14). The central processing unit CPU further sets the block bit BL of the status register SR to the logical value “0” and cancels the mask for other exceptions and interrupts (S15). Thereafter, as described above, the central processing unit CPU reads the exception factor code from the registers EXPEVT and INTEVT (S16), and branches to the corresponding exception handler using the exception factor code as an address offset (S17). That is, the central processing unit CPU executes the calculation of VBR + vector offset + exception cause code, and the processing is shifted to the exception handler assigned to the calculated address, that is, the branch destination exception handler. Thereby, the central processing unit CPU handles the exception that has occurred.

  As is apparent from the flowcharts of FIGS. 10 and 11, for the case where high-speed processing is given the highest priority as in the case of the TLB miss exception, the value of the register VBR is read once and the vector offset (H′400) is read. The vector point of the TLB miss exception handler can be acquired simply by adding. For another exception factor, in addition to obtaining a vector point obtained by adding a vector offset to the value of the register VBR, an exception factor code obtained by reading the value of the register EXPEVT or INTEVT once. You can branch to the required exception handler by setting the address offset. Even in this branch, control can be transferred to processing that responds to an exception at high speed without acquiring the branch destination address directly by memory access.

  As is apparent from FIG. 11, whether or not to accept multiple exceptions and interrupts is determined by the description of the handler assigned to the vector point address defined by the hardware. When allowing multiple exceptions to be accepted, the values already saved in the save registers SSR and SPC are saved in the external memory MMRY. When high-speed processing is required, such as a TLB miss exception, the TLB miss exception handler is executed while prohibiting multiple exceptions and multiple interrupts, so it is absolutely necessary to save the save status register SSR and save program counter SPC to the memory. In this respect, it is guaranteed that the transition time from the occurrence of the TLB miss exception to the TLB miss handler is minimized.

  FIG. 12 shows a processing flow when an exception or interrupt is newly generated at the branch destination after branching to exception processing for handling general exceptions or interrupt requests.

  When an exception or interrupt is newly generated (S21), whether or not the block bit BL of the status register SR is a logical value “1” (S22), and the newly generated exception or interrupt is an instruction break exception. Whether or not to accept the newly generated exception or interrupt is determined depending on whether or not (S23). SR. If multiple acceptance is permitted due to BL = 0, processing is performed according to the flow of FIGS. 10 and 11 (S24).

  SR. When multiple acceptance of exceptions is prohibited due to BL = 1 (YES in S22), the general exception that occurred is not an instruction break exception (NO in S23), and it is an interrupt request (in S25) YES), the software is SR. Until BL = 0 is set (for example, until the process of step S14 is completed and the process proceeds to step S15), the acceptance of the interrupt is suppressed (S26). If it is a general exception or reset (NO in S25), the exception cause code is set in the register EXPEVT and then automatically branched to the reset handler (S27).

If the exception event at that time is an instruction break exception, the SPC, SSR, and EXPEVT registers are not updated in the hardware processing of FIG. 10, and the processing of the central processing unit CPU branches to the instruction break handler. Thus, the registers SPC and SSR are saved in the memory. Further, a return address is calculated from the breakpoint address of the break register IBR, and the return address is set in the save program counter SPC. Then, an instruction break exception handler process for dealing with an instruction break exception is performed. To return from the instruction break exception handler, the return address saved in the register SPC is used, and the program to be debugged can be continuously executed after the instruction breakpoint. In this way, for instruction break exceptions, system evaluation and program debugging can be performed by placing an instruction break at an arbitrary position even on a debug target program that is prohibited from receiving multiple exceptions. Can do.
According to the said Example, there exist the following effects. [1] For the case where high-speed processing has the highest priority, such as for the TLB miss exception, the value of the register VBR is read once, and the vector offset (H'400) is added to the value to obtain the TLB miss exception. The vector point (branch destination address) of the handler can be acquired. For another exception factor, the address of the exception factor code obtained by reading the value of the register EXPEVT or INTEVT once is added to the vector point obtained by adding the vector offset to the value of the register VBR. By adding as an offset, the start address (branch destination address) of the required exception handler can be acquired. Thus, since the branch destination address is not acquired by accessing the external memory, the transition time from the occurrence of the exception to the processing of the handler for dealing with the exception is shortened. As a result, the overall data processing speed of the microcomputer MPU can be increased. In other words, for processes such as TLB miss exceptions that are closely related to high-speed data processing, reducing the transition time to exception processing is the top priority, and reducing the transition time to exception processing is the top priority. For interrupts that are considered not to contribute to the speeding up of data processing speed as much as TLB miss exceptions, flexibility in handler mapping and handler size is provided, and user convenience is improved.

  [2] Only a part of the exception handlers (TLB miss exception handlers) arranged at the address obtained by adding the value of the vector base register and the vector offset directly to the corresponding exception Exception handling. For other exceptions, the exception cause code is used as an address offset, and further branched to reach a predetermined handler. In other words, the number of vector offsets, which are fixed offsets with respect to the vector base address, is much smaller than the number of exception factors. When a unique fixed offset (vector offset) is used for all exception factors, the amount of hardware for generating a vector offset increases as the exception factors increase. Therefore, it is considered that the area of the semiconductor chip on which the microcomputer is formed increases, and the cost of the microcomputer itself increases. However, in the exception processing as in the present invention, it is possible to satisfy both the physical circuit scale reduction and the data processing speedup. Therefore, the microcomputer MPU of the present invention can be formed on a semiconductor chip with a small area, and its cost is also reduced.

  [3] Whether or not to accept multiple exceptions and interrupts is determined by the description of the vector point handler defined by the hardware. When accepting multiple exceptions, values already saved in the save registers SSR and SPC are further saved in the external memory MMRY. When high-speed processing is required, such as a TLB miss exception, the exception handler is executed with multiple exceptions and multiple interrupts suppressed, so that the save status register SSR and save program counter SPC are saved to the external memory MMRY. Not required at all. In this respect, it is guaranteed that the transition time from the occurrence of the TLB miss exception to the TLB miss handler is minimized.

  [4] When branching from a vector point handler determined by hardware to another handler, the exception cause code is used as an address offset for branching. In other words, for example, the exception factor codes are assigned at intervals of H′20 corresponding to 32 bytes in terms of addresses so that each exception factor code can be used as an address offset. Therefore, the base address for the exception cause code (address offset) can be freely determined according to the program description of the exception handler disposed at the vector point determined by the hardware. This guarantees the user's degree of freedom with respect to the actual branch destination address and the size of the branch destination handler.

  [5] By using the registers SSR and SPC for saving the internal state and the return instruction address, it is possible to reduce access to the external memory when saving when an exception occurs.

  [6] In order to deal with both general exceptions that occur in synchronization with the operation of the central processing unit CPU and interrupt requests that occur asynchronously, a register EXPEVT that stores exception cause codes related to general exceptions and an exception cause code related to interrupt requests Is stored in the register INTEVT. It is possible to avoid a complicated process for writing the cause code to the common register at the same timing when both exceptions occur, and to simplify the process of setting the exception cause code in each register.

  [7] In the processing of a reset exception handler or TLB miss exception handler (branch destination handler determined by hardware according to the exception cause), the initial processor mode is the exception multiple-rejection suppression state and privilege state. Made constant by the transition to. Therefore, the content of exception handling that can be defined on the handler of the user is guaranteed a high degree of freedom.

  [8] By enabling the register banks of the general-purpose registers R0 to R7 to be switched by software only in the privileged state, the central processing unit CPU can use the general-purpose registers R0 to R7 in a bank different from the user state in the privileged state. . This means that, for example, when the processor mode is switched from the user state to the privileged state in exception processing, saving the contents of the general-purpose registers R0 to R7 to the external memory MMRY can be omitted. Also in this respect, the transition time from the occurrence of an exception to the processing for dealing with the exception is shortened.

  [9] In an exception handler process in which multiple exceptions are suppressed, an instruction break exception can be processed, so that any program to be debugged in a state where acceptance of multiple exceptions is prohibited can be arbitrarily set. It can be assured that system evaluation and program debugging can be performed with an instruction break at the position.

  [10] The address areas P1 and P2 are areas in which the corresponding physical addresses are fixed, and are not targeted for address translation using the address translation buffer TLB. When the address areas P1 and P2 are accessed in the privileged state, multiple exceptions related to address translation such as a TLB miss do not occur. Accordingly, by arranging various exception handlers such as interrupts and general exceptions in the address area P1 or P2, exceptions relating to address translation such as TLB misses do not newly occur during exception processing. In other words, it is possible to avoid a situation in which multiple exceptions relating to address translation occur, so that the data processing of the central processing unit CPU can be made more efficient.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the vector offset determined by hardware is not limited to H′100, H′400, and H′600, and the factor code that defines the address offset and its allocation interval are not limited to the above embodiment, It can be changed. In addition, the exception is not limited to the concept roughly divided into the reset, the general exception, and the interrupt request in the above embodiment. Further, although the TLB miss exception handler is arranged directly at the first vector point determined by the hardware, the exception handler that can be arranged at the vector point is not limited to this, and can be appropriately changed according to the system configuration. Needless to say, another exception handler arranged at the second point branched from the first vector point can further branch to another handler. Even in this case, the factor code can be used as address offset information.

  In the above description, the case where the invention made by the present inventor is applied to the microcomputer, which is the field of use behind it, has been described. However, the data processor, the microprocessor, the digital signal processor, etc. The present invention can be widely applied to various data processing devices that support exception handling.

1 is a block diagram of a single chip microcomputer according to an embodiment of the present invention. FIG. It is explanatory drawing which showed notionally the method of the present Example which branches from the vector point by hardware at the time of exception generation, and the handler further pointed to another handler. It is explanatory drawing of the general purpose register of a bank structure, and a system register. It is state explanatory drawing of the general purpose register | resistor and system register | resistor of FIG. 3 in user mode. It is state explanatory drawing of the general purpose register | resistor and system register | resistor of FIG. 3 in privilege mode. It is explanatory drawing of a control register. It is explanatory drawing which shows the allocation of an interrupt factor, a vector offset, etc. FIG. 10 is a diagram for explaining correspondence between interrupt factors and interrupt factor codes assigned to the interrupt factors. It is explanatory drawing of an exception factor register and a trap register. It is an example flowchart of the vector point process determined by hardware. It is an example flowchart of the process of the handler placed at the vector point. 10 is a flowchart illustrating an example of processing when another interrupt or general exception occurs in processing by an interrupt or general exception handler. It is an example address map of the microcomputer concerning a present Example. It is an example block diagram of the hardware which produces | generates a vector offset. It is an example block diagram of the logic which produces | generates an exception factor code.

Explanation of symbols

MPU microcomputer CPU central processing unit CTRL control unit PC program counter SPC save program counter SR status register MD mode bit RB register bank bit BL block bit SSR save status register VBR vector base register R0 to R15 general-purpose register UBC instruction break controller IBR instruction break Address register MMU Memory management unit TLB Address translation buffer TLBC control unit EXPEVT General cause exception factor register INTEVT Interrupt request exception factor register TRAP trap register CVG constant generation circuit SFT shifter

Claims (2)

A central processing unit, a storage circuit divided into a plurality of areas, a vector table, and an address translation buffer;
The vector table stores start addresses of a plurality of interrupt / exception handlers,
The address translation buffer is used to translate a logical address into a physical address;
The first area, which is one of the plurality of areas, is fixed to a physical address, is not subject to address translation in the address translation buffer, and the interrupt / exception handler is located in the first area. A one-chip data processor which is arranged. In claim 2,
The one-chip data processor further includes a cache memory,
The first area is not cached in the cache memory,
The second area, which is another one of the plurality of areas, is fixed to a physical address, is not subject to address translation in the address translation buffer, and is not subject to caching in the cache memory. ,
The interrupt / exception handler has a first block and a second block, wherein the first block is arranged in the first area, and the second block is arranged in the second area. Chip data processor.

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