JP2014179107A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing device in a bi-endian system, which allows the shared use of a program regardless of the endian type and allows the sharing of a vector table.SOLUTION: An instruction is fixed to a little endian, and the endian of data used for executing the instruction is variable. The size of each vector address of a vector table is 32-bits, and the number of bits at the time of data access is 32 bits at the maximum. A CPU performs an instruction fetch and before executing the fetched instruction, performs a 32-bit data access to a memory, for example. In so doing, the CPU controls an aligner so that the address and alignment of data which is stored in each address in the unit of byte in a data register become identical to the address and alignment of data which is specified by the little endian of the instruction, without depending on the endian type of the data.

Description

  The present invention relates to a data processing apparatus having a processor.

  In a data processing device having a processor such as a CPU (central processing unit) or DSP (digital signal processor), for example, a so-called microcomputer (also referred to as a microprocessor, a microcontroller, or a microcomputer) is a semiconductor integrated circuit device. In the data arrangement of binary information, there are a data arrangement called “Little Endian” and a data arrangement called “Big Endian”.

  The binary information handled by the microcomputer includes binary information processed as an instruction for controlling the operation of the microcomputer and binary information as data processed by execution of the instruction. In general, data processing is performed using either little endian or big endian for both instructions and data.

  On the other hand, as described in Patent Document 1, a microcomputer that can support both little endian / big endian endian of both instructions and data of the microcomputer, or Patent Document 2 Describes a microcomputer that can change little endian / big endian for data processed by the microcomputer.

  In the microcomputer described in Patent Document 2, the arrangement of data in byte units is changed depending on whether stored data is little endian or big endian, and processing can be performed for any endian. It is described that it is configured to be possible.

  In addition, in a microcomputer, it is also required to reduce the memory capacity required for storing instructions and data, and to improve instruction execution / data processing efficiency with appropriate power consumption.

JP 2000-82009 A JP 2005-174296 A

  Currently, a CPU (when the description as a function and the description as a physical area formed on a semiconductor are distinguished, the former is described as a CPU, the latter is described as a CPU core, and when there is no need for distinction, it is described as a CPU.) Alternatively, in the development of a data processing apparatus (hereinafter simply referred to as a microcomputer) having a processor such as a DSP, various peripheral function blocks (referred to as peripheral function IP or peripheral function IP core) together with the function of the CPU itself and the CPU core. Is configured on a semiconductor substrate, and various peripheral function blocks are operated under the control of the CPU, so that processing corresponding to one purpose is performed as a whole. In such a case, the peripheral function block that is required by a company specializing in the design and development of a specific peripheral function block called a so-called IP core vendor is purchased, or the peripheral function that has been designed in the past or designed by another product. Designs and development of target microcomputers have begun by using blocks and configuring them on a single semiconductor substrate.

  In such a microcomputer design and development system, the endian of the peripheral function block data purchased or designed by the company is different from the endian of the CPU itself, and the endian of the peripheral function blocks to be cooperated is also different. Can also occur.

  Conventionally, when such an endian difference occurs, a peripheral function block that matches the endian of the CPU is selected or the peripheral function block is redesigned to match the endian of the CPU. .

  In view of such a microcomputer development system, the inventors of the present application have recognized that the processing performance of the CPU and the microcomputer as a whole is impaired particularly by endian conversion as described in Patent Document 2. It was.

  One object of the present invention is to provide a microcomputer that performs suitable endian conversion.

  Another object of the present invention is to provide a bi-endian data processing apparatus in which a CPU can use a common program and a common vector address without depending on the type of endian.

  Either little endian or big endian can be selected as data to be processed by the CPU. When data is transferred between the CPU and the memory, the data transfer sequences at the size of the vector address of the CPU are made to match regardless of the endian.

  By fixing the endian of the instruction code, the same program can be used, the endian of the data is variable, and each vector address of the vector table is N bits, and the N bit size aligned to N bits When the data is accessed, the data is controlled so that it can be accessed with the same address / alignment without depending on the endian regardless of whether the data is endian or big endian. On the other hand, when the CPU accesses data in a unit different from N bits, it is obtained from the memory so that it is suitable for the address and alignment of the data stored in each address in byte units of the data register in the CPU. A mechanism for changing the address and alignment of the data is provided.

  In the data transfer at the vector size, the vector address can be shared by enabling the data transfer in the same data order regardless of the data endian.

  In a data processing apparatus that employs a bi-endian system in which the endian of an instruction is fixed, a program can be used in common and a vector table can be used in common.

  Hereinafter, various embodiments of the present invention will be described in detail along with the effects and advantages thereof with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating a configuration of a part of the microcomputer according to the first embodiment. It is a figure which shows typically the structure of the vector table stored in the memory area. FIG. 3 is a block diagram schematically showing signal wiring relationships when a CPU performs a data read operation or write operation in a bi-endian system. FIG. 3 is a block diagram schematically showing a connection relationship between each address of a register in a CPU and each address of a storage area in a memory in the case of 32-bit data access. It is a figure which shows the byte order in a memory and a register at the time of reading the data stored in the memory area, and storing in a register. FIG. 10 is a block diagram schematically showing a connection configuration between a CPU and a CPU peripheral I / O device in the second embodiment. It is a figure which shows the structure of a memory typically. It is a figure which shows schematic structure of a microcomputer. It is a figure which shows schematic structure of CPU. It is a figure which shows the general connection relationship between CPU and memory. It is a figure which shows the address space of the memory allocated by CPU. It is a figure which shows the access relationship at the time of the data transfer between a memory and a register | resistor. It is a figure which shows an example of an aligner. It is a figure which shows an example of the connection condition of the aligner at the time of the data transfer per interrupt vector address. It is a figure which shows schematic structure of the microcomputer which has a peripheral function block from which an endian differs. It is a figure which shows an example of an aligner. It is a figure which shows roughly the flow of the development tool of the program run with a microcomputer. It is a figure which shows the example of an evaluation item about the processing performance of a microcomputer. It is a figure which shows the outline of the pipeline process of an instruction. It is a figure which shows the outline of the bus structure in a Harvard architecture. It is a figure which shows the outline of the pipeline process in a Harvard architecture. It is a figure which shows the example of a calculation using a product-sum calculator. It is a figure which shows the example of a calculation using a floating point arithmetic unit. It is a figure which shows another example of calculation using a sum-of-products calculator and a floating point calculator. It is a figure which shows the appearance frequency of the command which appears in a program. It is a figure which shows an example of the instruction | command which made instruction size small among the instructions with high appearance frequency. It is a figure which shows the address calculation of the register indirect addressing with an index. It is a figure which shows the address calculation of the register indirect addressing with a post-increment / pre-decrement function. It is a figure which shows the calculation by 3 operand specification. It is a figure which shows an example of the register structure in a microcomputer. It is a figure which shows an example about speeding up of an interruption process. It is a figure which shows the usage example of a register | resistor in a high-speed interrupt process. It is a figure which shows the time until the interruption process execution start by a high-speed interruption process exemplarily. It is a figure which shows the outline of the function of a memory protection. It is a figure which shows an example of an endian conversion instruction | indication. It is a figure which shows the outline of a clock gating design. It is a figure which shows the outline of the timing biolation solution design in a critical path. It is a figure which shows the outline regarding power supply domain division | segmentation. It is a figure which shows the outline of the processing performance at the time of using Flash memory for a microcomputer.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a part of the microcomputer according to the present embodiment. In FIG. 1, the description of an aligner 11 to be described later is omitted.

  In FIG. 1, a memory 4 is a readable / writable storage medium, and is composed of, for example, a volatile memory such as SRAM or a nonvolatile memory such as a flash memory (an example of EEPROM), and is the same semiconductor as the CPU 1. It is mounted on the chip. Alternatively, the memory 4 may be mounted on a semiconductor chip separate from the CPU 1. Alternatively, the memory 4 is present outside the microcomputer in a practical state, such as a USB memory, and is connected to a system bus of the microcomputer, which will be described later, via a connection terminal such as a USB terminal. May be electrically connected.

  The memory 4 includes (1) a storage area 4R1 for storing instruction codes (hereinafter simply referred to as “instructions”), (2) a storage area 4R2 for storing data used when executing instructions of the program, (3 ) A storage area 4R3 for storing signals such as other data.

  In this embodiment, as one of the feature points, the endian of the instruction is always fixed only to one of little endian and big endian. Therefore, the endian of the instruction bus 5 that can be used only when the CPU 1 fetches an instruction is always fixed to only one of little endian and big endian. In this example, it is assumed that the endian of the instruction is always fixed to little endian.

  On the other hand, the endian of the data used when the instruction stored in the storage area 4R2 is executed, that is, the endian of the data bus 3 used when the CPU 1 executes the read operation or the write operation is variable. Alternatively, it can be set to either big endian. In the present embodiment, the bit amounts of signals that can be transferred through the address bus 2, the data bus 3, and the instruction bus 5 are all 32 bits. Therefore, in the bi-endian system for transferring data which is a multi-byte binary numerical value, the data bus 3 is composed of four sets of signal lines each transferring 8-bit (1 byte) data ( This corresponds to signal lines 30 to 33 in FIG. Note that the address bus 2, the data bus 3, and the instruction bus 5 are not only configured as physically different buses, but also physically configured as one bus and function as temporally different buses (a so-called split transaction bus). Etc.) should be understood as indicating the time during which the bus is functioning.

  FIG. 2 is a diagram schematically showing the configuration of the vector table 6 stored in the area 4R3 of the memory 4. As shown in FIG. The vector table 6 is an area in which a plurality of vector addresses 7 each having a size of N bits are arranged together. That is, each vector address 7 is input with a reset signal when the microcomputer is started, and an interrupt signal for requesting processing of a specific commonly used interrupt program such as execution of a debug processing program. (Both are referred to as “interrupt factors”). The address gives the storage location of the corresponding interrupt processing program in the area 4R1, which is predetermined according to each interrupt factor. First, when a reset signal is input from the outside at the time of activation, an N-bit reset vector address 8 is read through the data bus 3 and the reset vector address 8 is output to the CPU 1. When an interrupt signal is input to the CPU 1 during the operation of the CPU, the vector address 7 corresponding to the input interrupt signal is read through the data bus 3 and output to the CPU 1. In the example of the present embodiment, the size N of each vector address 7 including the reset vector address 8 in a bit unit is set to 32 (N = 32). The endian of the data bus 3 is switched according to the level of the endian signal given from the CPU 1 at the time of reset. In other words, the state of the dedicated mode terminal and the state of the mode terminal that is also used as a general-purpose I / O port (external terminal) are taken into the microcomputer at the time of power-on reset, and latched in a register, for example, and the data is little endian or big endian. The CPU 1 can determine which is before the vector address is accessed.

  Here, the vector table 6 may be stored in a storage area of a ROM (second memory) that can be read / written separately from the memory (first memory) 4 for storing instructions and data. In an example of the present embodiment, the areas 4R1 and 4R2 for storing instructions and data in the storage area of the memory 4 correspond to the “first memory”, and the area 4R3 for storing the vector table 6 is the “second memory”. It can also be defined as “memory”.

  When the memory 4 shown in FIG. 1 is composed of a RAM (first memory), the RAM 4 is provided separately from the RAM 4 as a second memory mounted on a semiconductor chip in the microcomputer, or an external second memory. As a memory (USB memory or the like), a readable / writable ROM for storing the vector table 6 is provided.

  FIG. 7 is a diagram showing a schematic configuration of the memory. A plurality of memory cells are arranged in an array, and each memory cell is connected to a corresponding word line and bit line. In general, a memory activates a predetermined word line based on an access address supplied from a CPU or the like, and a Y decoder sends data stored in a memory cell connected to the word line via a bit line. read out. For example, when address 0 is supplied as an access address, if the memory is one in which the 0th word line is activated, data of the number of bytes to be accessed is supplied to the CPU from the 0th bit line of the 0th word line. That is, when X is supplied as the access address, the Yth word line (Y = X ′ / l, X ′ is X × 8 bit representation, l is the number of memory cells per word line) is activated. Then, data is read from the Zth bit line (Z = X ′ mod 1, mod is a remainder operation).

  FIG. 3 is a block diagram schematically showing a signal wiring relationship when the CPU 1 performs a data read operation or write operation in the bi-endian system. A register (data register, mainly a general-purpose register) 9 arranged in the CPU 1 is a storage area 90, 91, 92 given by four addresses 0, 1, 2, 3 in byte units. , 93. On the other hand, the memory cell array of the storage area 4R2 of the memory 4 has a storage area 10 that is a set of four storage areas 10A, 10B, 10C, and 10D given by addresses 0, 1, 2, and 3, respectively. Aligned in the row and column directions. The aligner 11 is composed of a switch group (not shown) including switches that can be switched on / off in accordance with a control signal CNT1 output from the CPU 1. The aligner 11 is connected to each address 10A to 10D in the storage area 10 to each signal line (each line of the data bus 3) 30 to 33 connected through the corresponding bit line and to each address 90 to 93 of the register 9. A function of connecting the connected signal lines in accordance with the data or the endian type of the data bus 3 is exhibited. FIG. 4 is a block diagram schematically showing a connection relation between each address of the register in the CPU 1 and each address of the storage area in the memory in the case of 32-bit data access. If the 0 address 90 side of the register 9 is LSB, the 3 address 93 side is MSB, the 0 address 10A side of the memory 4 is LSB, and the 3 address 10D side is MSB, the aligner 11 is connected when the data is little endian. Is shown.

  Here, when the CPU 1 stores 32-bit data in the storage area 10 (access address X) of the memory 4, the 32-bit data is stored in advance in the respective addresses 10 </ b> A to 10 </ b> D as follows. The address of the area 4R2 of the memory 4 is defined. That is, as shown in FIG. 5, (1) when data is stored in little endian, the LSB side of the data stored in the register is set to +0 byte order, and the MSB side is set to +3 byte order. Determine the byte order of the data. Similarly, the byte order of +0 to +3 is determined at the memory storage destination address so that the byte order of the data stored in the register matches the byte order determined for the memory storage address. Store the data. On the other hand, (2) when the data is stored in big endian, the byte order of the data is set so that the MSB side of the data stored in the register is +0 byte order and the LSB side is +3 byte order. The byte order is also determined at the storage destination address of the memory, and the data is stored in the memory. Each byte order of +0 to +3 determined with respect to the storage destination address of the memory corresponds to each address 10A to 10D.

  Assume that a reset signal is input from the outside at the time of startup, and the CPU 1 acquires the 32-bit reset vector address 8 shown in FIG. 2 by performing operand access. The 32-bit reset vector address 8 gives the address of the instruction stored in the area 4R1 of the memory 4. When an interrupt signal is input to the CPU 1, the CPU 1 automatically performs operand access and obtains a 32-bit vector address 7. Then, the CPU 1 performs an instruction fetch operation based on the reset vector address 8 or the vector address 7 corresponding to the interrupt factor, decodes the fetched instruction, and moves the operation to the instruction execution. . In this case, the case where 32-bit data having the same data size as the reset vector address 8 and the vector address 7 is acquired from the memory and the case where 16-bit data having a data size different from the vector address are acquired from the memory are described below. To do.

  FIG. 5 shows how data alignment is changed during data transfer. The location indicated by the arrow at address 0 corresponds to the 4-byte boundary (the 32nth bit line) of the memory, and 32-bit data is stored in the memory cells for 32 bits (up to the 32nd (n + 1) -1 bit line). . For the data storage state, the aligner assigns a byte order according to the endian of the data and transfers it to the register. Since the byte order stored in the memory in each endian is stored so that the byte order stored in the register matches, the data order stored in the register matches regardless of the endian when transferring 4 bytes. .

  In the case of performing 16-bit data transfer, the data alignment is changed as follows. The aligner assigns a byte order to 32-bit data from the 4-byte boundary of the memory according to the endian of the data. Data corresponding to the + 0 / + 1 byte order of each endian is stored in order from the LSB of the register. As shown in the figure, in little endian, the byte order +0 assigned by the aligner corresponds to the LSB of the register, so the 2-byte data stored in the memory matches the 2-byte data stored in the register. . On the other hand, in the big endian, +0 of the byte order assigned by the aligner corresponds to the MSB of the register. Therefore, at the time of 4-byte transfer, 2-byte data stored in the MSB side of the register is stored in the LSB side of the register. Note that “**” stored in the MSB side 2 bytes of the register indicates that “0” or “1” or the sign bit of the data is expanded and stored.

  The above description is valid even when the CPU 1 accesses 8-bit data.

  In the operation description of the above example, the data read operation is mainly described. However, the feature points of the present embodiment described above are stored in the register even in the data write operation. It is possible to apply the same correspondence between the byte order of the stored data and the byte order assigned by the aligner when stored in the memory.

  As described above, when the configuration of the present embodiment is adopted as the configuration of the data processing device, the transfer of data having the same size as the vector address and the vector address is the same regardless of the type of data endian. Data can be read / written to / from the memory at the same address and the same data alignment, and a common program can be executed at that time, and the vector table can be shared.

(Embodiment 2)
The feature of the present embodiment is that in the bi-endian microcomputer according to the first embodiment, the data bus between each I / O device around the CPU and the CPU is changed to a data bus dedicated to little endian and big endian. It is in a point separated from a dedicated data bus.

  FIG. 6 is a block diagram schematically showing feature points of the present embodiment. As shown in FIG. 6, a data bus for transferring data between the CPU 1 and peripheral I / O devices of the CPU 1 is provided with a data bus 14 dedicated to big endian and a data bus 17 dedicated to little endian. ing. The peripheral I / O devices 15 and 16 dedicated to each big endian are connected to the big endian data bus 14 via individual signal lines. On the other hand, the peripheral I / O devices dedicated to each little endian are used. Reference numerals 18 and 19 are connected to the little endian data bus 17 via individual signal lines. Examples of each peripheral I / O device include an interrupt control circuit (INTC), a direct memory access controller (DMAC), and a serial communication interface (SCI).

  The CPU 1 stores data transferred between the CPU 1 and the peripheral I / O devices 15 to 19 of the CPU 1 in the I / O register 12. The endian of the data stored in the I / O register 12 is one of little endian and big endian. Under the control of the control signal CNT2 output from the CPU 1, the aligner 13 determines the byte order of the data in the I / O register 12 according to the type of endian of the data stored in the I / O register 12. The connection is made to match the byte order assigned to the corresponding data bus among the big endian data bus 14 and the little endian data bus 17. Depending on which address range the registers, memories, etc. in the peripheral I / O device are in, little endian or big endian is known. That is, the state of the control signal CNT2 is determined by decoding the address accessed by the CPU1.

  When the above configuration is adopted, the endian of the data transferred between the peripheral I / O device and the CPU is fixed, and the access processing to the peripheral I / O device depends on the type of endian. Therefore, a common program can be used. That is, since the aligner 13 adjusts the byte order of data to each peripheral I / O device, both the big endian peripheral I / O device and the little endian peripheral I / O device are used. Even when data processing is performed, it is possible to eliminate the processing that considers the endian of the data of the peripheral I / O device such as performing endian conversion of the data in the program executed by the CPU. Further, in a data processing apparatus having a plurality of data processing modules (so-called function IP, which corresponds to the peripheral I / O device in FIG. 6) on one semiconductor substrate, it corresponds to the data endian of the data processing module itself. By separating the bus and connecting to the CPU via the aligner, the data processing module is selected or executed by the CPU of the data processing device so that the data endian matches in the configuration of the data processing device. It is possible to reduce the burden on the hardware / software when configuring the data processing apparatus, such as converting the endian of the data for each data processing module by the program.

(Embodiment 3)
FIG. 8 is a block diagram showing an outline of an example of the microcomputer MCU.

  A central processing unit (hereinafter referred to as a CPU) 1 performs processing control for the entire microcomputer MCU by fetching and executing instructions stored in a nonvolatile memory ROM, a volatile memory RAM, or the like. The direct memory access controller DMAC transfers data between the external memory EMEM and the memory 4 (consisting of a nonvolatile memory ROM, a volatile memory RAM, etc.) or between the memory 4 and the peripheral circuit group (IP1, IP2). Take control. The bus controller BSC performs control such as granting a bus right when the CPU 1 and other functional blocks perform data transfer via the bus. The interrupt controller INTC accepts an interrupt generated inside or outside the microcomputer MCU and performs control such as notification to the CPU 1. The peripheral circuit group (IP1, IP2) is a communication IF (InterFace) system (serial IO (Input / Output), parallel IO, etc.) that communicates with another semiconductor integrated circuit device connected to the outside of the microcomputer MCU, Dedicated data processing system (image processing block, encryption processing block, etc.). The external bus interface BIF is connected to an external memory EMEM and the like via a bus connected to the outside of the microcomputer MCU.

  FIG. 9 is a block diagram showing an outline in the CPU 1, FIG. 10 is a diagram showing a memory access relationship of the CPU 1, and FIG. 11 is a diagram showing an address space of the memory 4 allocated by the CPU 1. In FIG. 11, “H” on the right side of the address indicates that the address is expressed in hexadecimal. In FIG. 11, only the address of the head address of each area is shown.

  A bus to which the CPU 1 in FIG. 8 is connected to other functional blocks is composed of a 32-bit address bus 2, a 32-bit data bus 3, and a 32-bit instruction bus 5 shown in FIG. Another bus configuration may be a split transaction bus configuration in which addresses, data, and instructions are exchanged on a bus signal line in a time-sharing manner. In the case of an architecture in which data and an instruction are not accessed in parallel, the data bus 3 and the instruction bus 5 are not separated but may be configured by the same bus. Further, the data bus 3 and the instruction bus 5 may be 64 bits long.

  When the CPU 1 performs instruction fetch, the address of the instruction to be fetched stored in the 32-bit program counter PC is output to the address bus 2, and the memory 4 that has received the address via the address bus 2 receives the address. Binary information corresponding to is output to the instruction bus 5. The CPU 1 stores the binary information received from the instruction bus 5 in the instruction register IR as an instruction to be executed, decodes the instruction by the instruction decoder iDEC, and a control signal corresponding to the decoded result is an arithmetic logic unit ALU, a multiplier MLT, Calculations that are output to arithmetic units such as a divider DIV, shift arithmetic unit SHFT, and floating-point arithmetic unit, and that correspond to the data stored in the register group REG (general-purpose registers and dedicated registers), the memory 4, etc. Execute.

  When the CPU 1 receives an interrupt notification from the interrupt controller INTC, the CPU 1 performs the interrupt processing corresponding to the received interrupt notification, in order to perform the interrupt processing corresponding to the received interrupt notification. Among them, an address corresponding to the received interrupt notification is output to the address bus 2, and the memory 4 outputs binary information corresponding to the address to the data bus 3. The CPU 1 sets the binary information received from the data bus 3 in the program counter PC as an address (referred to as a vector address) where the interrupt processing routine is stored, and branches to execute the instruction of the interrupt processing routine. Here, the vector address is 32 bits (4 bytes) long. It is assumed that a vector address for exception processing other than the interrupt notification from the interrupt controller INTC (for example, privileged instruction exception processing, undefined instruction exception processing, etc.) is also stored in the interrupt vector table area.

  Note that the reset vector area (address FFFFFE00H in FIG. 11) is an address (for example, boot) that stores a program to be executed immediately after the reset period ends when the microcomputer MCU is turned on or a reset signal is input from the outside. This is an area in which the head address (0000H) of the instruction area is stored. Although there is a difference between the interrupt process and the reset process whether the cause is an interrupt or a reset, they are almost the same in acquiring a branching address.

  The endian of the instruction stored in the program area such as the boot instruction area, the first program area, the second program area, and the interrupt processing routine area is fixed to either little endian or big endian. Further, the endian of the data in the vector areas such as the reset vector area and the interrupt vector table is fixed to either little endian or big endian. These endians may be fixed at the time of manufacture of the microcomputer, and may be fixed at the latest before the vector area is accessed after the power-on reset. In the latter case, the state of the dedicated mode terminal and the mode terminal that is also used as a general-purpose I / O port (external terminal) is taken into the microcomputer at power-on reset, and latched in a register, for example, and the data is little endian or big endian It is only necessary that the CPU 1 can determine before the vector address is accessed.

  The first program is stored in an area in the range of addresses 1000H to 1FFFH in the memory 4. The second program is stored in an area in the range of addresses 3000H to 3FFFH in the memory 4. The first program and the second program each have a first data area (addresses 2000H to 2FFFH) and a second data area (addresses 4000H to 4FFFH). The first program performs data processing with the endian of the data in the first data area as little endian, and the second program performs data processing with the endian of the data in the second data area as big endian. For example, the first program is a program that processes data generated by a peripheral circuit that processes data in little endian, and the second program is a program that processes data generated by a peripheral circuit that processes data in big endian. Applicable.

  Whether little-endian or big-endian data is processed is determined in advance depending on the address range of the CPU 1 address space. Depending on the address range, the little endian or big endian data may be processed by the CPU. In addition, after the reset is released, data stored in advance in the built-in nonvolatile memory may be automatically transferred to a register so that it can be set whether little endian data or big endian data is processed.

  When an interrupt notification is generated from the interrupt controller INTC while the CPU 1 is executing the first program, the interrupt vector table area (addresses FFFFFD00H to FFFFFFFFH) is accessed in a fixed endian.

  On the other hand, when an interrupt notification is generated while the CPU 1 is executing the second program, the interrupt vector table area is accessed in a fixed endian.

  FIG. 12 is a diagram showing an access relationship when data is transferred between the memory 4 and the register 9 of the CPU 1. FIG. 13 is a diagram showing an example of the aligner 11.

  When data is transferred from the memory 4 to the register 9 (one register in the register group REG), if the data to be transferred is stored in the areas 10A to 10D of the memory 4, the relative address displacement The data at address 0 (10A) is output to the 8-bit partial bus indicated by number 30 in the data bus 3. Similarly, the data (10B to 10D) at the address displacements 1 to 3 are output to the 8-bit partial bus indicated by the numbers 31, 32 and 33. Depending on the state of the control signal CNT1, whether the data output to the respective partial buses indicated by the numbered numbers 30 to 33 is stored in the 8-bit partial area of the relative address displacements 0 to 3 of the register Is determined by the aligner 11. The control signal CNT1 is a signal generated by information such as little endian or big endian, an access size to the memory 4, and an access byte address.

  First, the case where data transfer from the memory 4 to the register is accessed with 4 bytes, which is the size of a vector address (hereinafter referred to as interrupt vector address) such as a reset vector address or an interrupt vector address, will be described. In this case, the aligner 11 is set to be in a connected state as shown in FIG. FIG. 14 is a block diagram schematically showing a connection relation between each address of the register in the CPU and each address of the storage area in the memory 4 in the case of access with 4 bytes. If the 0 address 90 side of the register 9 is LSB, the 3rd address 93 side is MSB, and the 0 address 10A side of the memory 4 is LSB, and the 3rd address 10D side is MSB, the aligner 11 stores data in the memory 4 and data in the CPU 1. The connection relationship when the endian is the same is shown. That is, when the endian of the data in the CPU 1 is little endian, it indicates that the endian of the data in the memory 4 is little endian. Hereinafter, as an example, a case where the endian of data in the CPU 1 is little endian will be described.

  In FIG. 13, when 4-byte access is made to data in the first data area (little endian data), partial buses [0: 7] (data bus 30), [8:15] (data bus 31), [16 : 23] (data bus 32), [24:31] (data bus 33) is connected to the 4-byte data, and the data output to the partial bus [24:31] is on the MSB side of the register. Thus, the address displacement of the register 9 is stored at address 0 (90), address 1 (91), address 2 (92), address 3 (93). On the other hand, when data in the second data area (big endian data) is accessed, the partial bus [0: 7], so that the data output to the partial bus [24:31] is on the MSB side of the register, The respective data connected to [8:15], [16:23], and [24:31] are stored at address displacement address 0, address 1, address 2, and address 3 of register 9. That is, regardless of whether the data in the first data area or the second data area is being accessed, the aligner is arranged so that the order stored in the register 9 in the CPU 1 coincides with the access at the interrupt vector address size. Eleven selectors 1 to 4 are set. Each of the selectors 1 to 4 is composed of four bidirectional switches, and the bidirectional switch is composed of a CMOS transfer gate. The control signal CNT1 is directly or decoded to control the bidirectional switch.

  Similarly, even if an interrupt notification is generated during execution of either the first program or the second program, the partial bus [0: 7], [8] of the address storing the interrupt vector address is used to access the interrupt vector address. : 15], [16:23], and [24:31] are output 4 bytes of data, and the data output to the partial bus [24:31] is placed on the MSB side of the register. Address displacement is stored at address 0, address 1, address 2, and address 3.

  The register that stores the interrupt vector address is the program counter PC, and the address stored in the program counter PC is updated to branch to the interrupt processing routine.

  Such a branching operation is not limited to branching to an interrupt processing routine when an interrupt notification is generated, but is also the same for execution of an instruction with an address modification such as an address modification branch instruction.

As an address modification branch instruction, for example,
jmp @ # adr (1)
jmp @Rn (2)
The instruction is described as follows. “@” Included in the instruction description indicates that address modification is performed, “#” indicates that the following binary information is recognized as numerical information, and Rn indicates that a register number is designated.

  In the instruction (1), the branch destination address is stored at the address of the memory 4 indicated by adr. When the instruction is executed, the address adr is accessed and the branch destination address is acquired with the same size as the interrupt vector address. And transferred to the program counter PC. By updating the address stored in the program counter PC to the branch destination address, it is possible to branch the execution of the instruction. In the instruction (2), the address adr in the instruction (1) is stored in a register, and the address adr is acquired by accessing the register Rn. Subsequent operations are the same as those of the instruction (1).

  Next, a case where data transfer from the memory 4 to the register is performed with 2 bytes, which is half the interrupt vector address size, and a case where the data transfer is performed with 1 byte will be described. Even when data transfer from the memory 4 is performed by 2 bytes or 1 byte, after data is read from the memory 4 by 4 bytes, 2 bytes or 1 byte to be read is transferred to the register.

  When 2-byte data transfer is specified from the address 2000H of the first data area, the data connected to the partial buses [24:31] and [16:23] of the 4-byte data read starting from the address 2000H On the other hand, the selector 3 connects the partial bus [24:31] to the in-register displacement address 1 of the register 9, and the selector 4 connects the partial bus [16:23] to the in-register displacement address 0. In this case, the selectors 1 and 2 are controlled not to store the data connected to the partial buses [0: 7] and [8:15] in the register.

  When 2-byte data transfer is specified from the address 2002H, for the data connected to the partial buses [8:15] and [0: 7] of the 4-byte data read starting from the address 2000H, The selector 3 connects the partial bus [24:31] to the in-register displacement address 1, and the selector 4 connects the partial bus [16:23] to the in-register displacement address 0. In this case, the selectors 1 and 2 are controlled so as not to store the data connected to the partial buses [0: 7] and [8:15] in the register.

  On the other hand, when 2-byte data transfer is specified from the address 4000H of the second data area, it is connected to the partial buses [0: 7] and [8:15] of the 4-byte data read starting from the address 4000H. The selector 3 connects the partial bus [0: 7] to the in-register displacement address 1 of the register 9, and the selector 4 connects the partial bus [8:15] to the in-register displacement address 0 of the register 9. To do. In this case, the selectors 1 and 2 are controlled not to store the data connected to the partial buses [0: 7] and [8:15] in the register.

  When 2-byte data transfer is specified from the address 4002H, for the data connected to the partial buses [16:23] and [24:31] of the 4-byte data read starting from the address 4000H, The selector 3 connects the partial bus [16:23] to the in-register displacement address 1, and the selector 4 connects the partial bus [24:31] to the in-register displacement address 0. In this case, the selectors 1 and 2 are controlled so as not to store the data connected to the partial buses [0: 7] and [8:15] in the register.

  Next, a case where data transfer from the memory 4 to the register 9 is performed with 1 byte which is a quarter of the interrupt vector address size will be described.

  When 1-byte data transfer is specified from the address 2000H of the first data area, data connected to the partial bus [0: 7] is output, and the selector 4 shifts the partial bus [0: 7] to address 0 in the register. Connect to. When 1-byte data transfer is specified from the address 2001H, data connected to the partial bus [8:15] is output, and the selector 4 connects the partial bus [8:15] to the displacement 0 in the register. . When 1-byte data transfer is specified from the address 2002H, data connected to the partial bus [16:23] is output, and the selector 4 connects the partial bus [16:23] to the in-register displacement address 0. . When 1-byte data transfer is designated from the address 2003H, data connected to the partial bus [24:31] is output, and the selector 4 connects the partial bus [24:31] to the displacement 0 in the register. .

  On the other hand, when 1-byte data transfer is designated from the address 4000H of the second data area, data connected to the partial bus [24:31] is output, and the selector 4 places the partial bus [24:31] in the register. Connect to address 0. When 1-byte data transfer is specified from the address 4001H, data connected to the partial bus [16:23] is output, and the selector 4 connects the partial bus [16:23] to the in-register displacement 0 address 90. . When 1 byte data transfer is specified from the address 4002H, data connected to the partial bus [8:15] is output, and the selector 4 connects the partial bus [8:15] to the in-register displacement 0 address 90. To do. When 1-byte data transfer is designated from the address 4003H, data connected to the partial bus [0: 7] is output, and the selector 4 connects the partial bus [0: 7] to the in-register displacement address 0.

  The aligner 11 may be provided between the register 9 of the CPU 1 and the data bus 3, and may be provided in the CPU 1, for example. Further, an aligner for the external memory EMEM may be provided in the external bus interface BIF. In this case, switching between big endian and little endian for each address space of an external device such as the external memory EMEM may be set by a CPU using a register.

  The case of transferring data of various sizes from the memory 4 to the register 9 has been described above, but the same applies to the case of transferring data from the register 9 to the memory 4. In the case of transferring data from the memory 4 to the register 9, when the data size is 2 bytes and 1 byte, the data of the portion not transferred is sign-extended (0 extension or 1 extension may be performed). On the other hand, when data is transferred from the register 9 to the memory 4, when the data size is 2 bytes and 1 byte, the untransferred portion is not affected.

  As described above, in the third embodiment, the same data is accessed when the memory 4 is accessed in units of the interrupt vector address size regardless of whether the data in the memory 4 is little endian or big endian. By storing in the registers in order, it is possible to share programs such as interrupt vector addresses and interrupt processing programs, regardless of the endianness of the data of the program being executed when the interrupt notification is received. Become.

  In the third embodiment, the big endian and little endian areas can be set according to the address space of the memory. However, as in the first embodiment, the entire memory 4 built in the microcomputer is either big endian or little endian. It may be possible to set either endian. In this case, as in the third embodiment, the state of a dedicated mode terminal or a general-purpose I / O port (external terminal) and a mode terminal that is also used at the time of power-on reset is taken into a microcomputer and latched in a register, for example. The CPU 1 may determine whether the data is little endian or big endian before the CPU 1 accesses the vector address.

(Embodiment 4)
FIG. 15 shows an outline of a microcomputer having peripheral function blocks of different endians, and other configurations are the same as those of the microcomputer MCU (FIG. 8) of the third embodiment. FIG. 15 shows a CPU 1, a bus controller BSC, a little endian peripheral function block (little endian peripheral I / O devices 18, 19) connected to the bus controller BSC, and a bus controller BSC. The big endian peripheral function blocks (big endian peripheral I / O devices 15 and 16) that perform data processing in big endian connected to are described. The little endian peripheral function block is connected to the aligner 13 in the bus controller BSC via the little endian peripheral data bus 17, and the big endian peripheral function block is connected to the bus controller BSC in the bus controller BSC via the big endian peripheral data bus 14. Connected to aligner 13. In this configuration, the transfer buffer TBL in the little endian peripheral I / O device 19 and the transfer buffer TBB in the big endian peripheral I / O device 15 and the I / O register 12 of the CPU 1 (of the register group REG) A single register, which may be the same as register 9, is connected to the bus so that the LSBs are connected in common regardless of the size of the transfer buffers and registers in the peripheral I / O device. Is done. The little endian peripheral I / O devices 18 and 19 or the big endian peripheral I / O devices 15 and 16 can be discriminated by the addresses assigned to the respective transfer buffers and registers.

  The little-endian peripheral I / O devices 18 and 19 receive little-endian sequence data from the external or little-endian peripheral data bus 17 or process the data to generate little-endian sequence data. Output to the endian peripheral data bus 17.

  The big endian peripheral I / O devices 15 and 16 receive big endian sequence data from the external or big endian peripheral data bus 14 or process the data to generate big endian sequence data. Output to the endian peripheral data bus 14.

  The CPU 1 controls the operation of the little endian peripheral I / O devices 18 and 19 by executing the first program, and controls data input and output to the little endian peripheral I / O devices 18 and 19. For example, when data is transferred to the little endian peripheral I / O devices 18 and 19 and the processed data is transferred to the memory 4, the transfer setting information of the aligner 13 is added to the control signal CNT2 according to the size of the data to be transferred. Set. The setting of the control signal CNT2 is the same in the data transfer in the big endian peripheral I / O devices 15 and 16.

  The aligner 13 is configured so that the same data is arranged regardless of the endian when the sizes of the transfer buffers and registers in the peripheral I / O device and the access sizes of these transfer buffers and registers are the same. For example, when the CPU 1 transfers the data stored in the transfer buffer TBL of the little endian peripheral I / O device 19 to the second data area (big endian) of the memory 4, the designated address of the transfer buffer is set to the head. Are stored for the interrupt vector address size, with the designated address in the second data area as the head. In this case, the data stored in the transfer buffer TBL is once taken into a register in the CPU 1 and then transferred to the second data area of the memory 4.

  When data is transferred from the little endian peripheral I / O device 19 to the big endian peripheral I / O device (15, 16) or the second data area (big endian), the little endian peripheral I / O device 19 is used. Stores data on the LSB side when storing data in the transfer buffer, the I / O register 12 of the CPU 1 that processes the data, the transfer buffer TBB of the big endian peripheral I / O device 16, and the big endian peripheral I / O When the data stored on the LSB side of the register BIREG of the O device 15 is the same, the sizes of the transfer buffers and registers in the peripheral I / O device and the access sizes to these transfer buffers and registers are the same It is not necessary to change the arrangement of data in the aligner 13.

  On the other hand, when the access size to these transfer buffers and registers is smaller than the sizes of the transfer buffers and registers in the peripheral I / O device, the aligner 13 needs to change the data arrangement.

  The control signal CNT2 in which the CPU 1 sets the transfer setting information of the aligner 13 includes information on the processing unit of the data to be transferred and information on the transfer direction as well as the size information of the data to be transferred.

  FIG. 16 shows a configuration example of the aligner 13. The selectors 1A to 4A and 1B to 4B receive the control signal CNT2, respectively, and determine the input / output direction and the connection between the partial buses. When the size of the transfer buffer or register in the peripheral I / O device and the access size to these transfer buffer or register are the same, the data bus of the same bit position (the little endian peripheral data bus 17 and the big endian peripheral The data bus 14 and the partial bus [0: 8]) of the CPU 1 / memory 4 data bus 3 are connected to each other.

  On the other hand, when the size of the transfer buffer or register in the peripheral I / O device is 2 bytes or 4 bytes, the data to be processed in units of bytes is transferred from the little endian peripheral data bus 17 to the big endian peripheral data bus 14. When the order of data is reversed (for example, in the case of 4 bytes, one partial bus [0: 7], the other partial bus [24:31], and one partial bus [8:15] And the other partial bus [16:23]) and the partial bus.

  Note that the selectors 1A to 4A and 1B to 4B are configured by the same bidirectional switches as the selectors 1 to 4 of the third embodiment.

  By configuring the aligner 13 in this manner, peripheral function blocks are connected to different buses according to the endian to be processed, and data can be transferred between the peripheral function blocks connected to the respective buses via the aligner 13. Is possible.

  As described above, in the fourth embodiment, data can be transferred in the same data order regardless of the endian of the data to be transferred to and from the peripheral function IP and the endian of the data to be processed in the program that controls the peripheral function IP. This makes it possible to share a program for controlling the peripheral function IP.

  Furthermore, regardless of the difference between the endian of the data processing of the peripheral function block and the endian of the data processing of the CPU 1, the degree of freedom to adopt the peripheral function block required by the microcomputer MCU can be improved.

(Embodiment 5)
FIG. 17 shows an outline of a flow of a program development tool executed by a microcomputer according to the first, second, third, and fourth embodiments and the sixth embodiment described later. The compiler performs syntax analysis and optimization on the source program described in a high-level language such as C language, and outputs an assembly language program described in the assembly language. The assembler generates a machine language from the assembly language output from the compiler and outputs a machine language program. One or a plurality of machine language programs are linked (linked) by a linkage editor to generate a program that can be executed by a microcomputer.

  Assembly language programs output by the compiler are broadly divided into code sections (or code segments), which are a collection of instruction codes executed by the CPU of the microcomputer, and constants and compilers described in high-level language programs. And a data section (or data segment) that is a set part such as a constant. As described above, the instruction code in the code section is fixed to either little endian or big endian. On the other hand, constants in the data section can be selected as either little endian or big endian. However, there is a specification instruction for which endian is to be used in the high-level language program. A solution is made.

  If it is a constant included in a high-level language or assembly language program, endian resolution is possible by a compiler or assembler, but the address reference value such as the branch destination address of a branch instruction is determined at the time of link processing in the linkage editor. Endian resolution cannot be performed by the compiler or assembler. The endian resolution of such an address is performed by the linkage editor.

  The linkage editor combines one or more machine language programs. For the address reference value referenced as a variable name in the machine language program before linking, the address value is determined by the arrangement after linking, and endian resolution is performed to determine the address. Stored as a constant in the data section of the executable program.

  The executable program generated by the above-described flow is stored in a mask ROM or flash memory configured on the semiconductor substrate of the microcomputer and configured to be executable by the microcomputer.

  In correspondence with the above-described third embodiment, when data is transferred from the data section to the register, the control signal CNT1 for setting the aligner 11 according to the data transfer size is output, and the data stored in the data section is transferred. The order is determined.

  The address reference value including the interrupt vector address and the address constant are set to have the same data size. As a result, in the execution of other branch instructions and address reference instructions, address information acquisition with the interrupt vector address size can appropriately acquire address information regardless of the endian of the stored data section.

  In correspondence with the above-described fourth embodiment, when data transfer is performed between peripheral function blocks or between the peripheral function block and the memory 4 or the register, the aligner 13 is set according to the data processing unit together with the data transfer size. The control signal CNT2 for performing is output, and the arrangement of data at the time of data transfer is determined.

(Embodiment 6)
Hereinafter, improvement in processing performance, improvement in code efficiency, and improvement in power consumption in the microcomputer MCU will be described, respectively. Note that the improvement in code efficiency is to reduce the memory capacity required for storing instructions.

  FIG. 18 shows the evaluation items for the processing performance of the microcomputer MCU. Although the microcomputer MCU has a range in processing performance required depending on the application to be used, FIG. 18 shows a microcomputer MCU that is incorporated in a device that performs relatively advanced processing such as a so-called digital home appliance. It is an example of the required processing performance.

  In order to realize such processing performance, five-stage pipeline processing is adopted as shown in FIG. As is generally known, pipeline processing divides instruction execution in the CPU 1 into a plurality of processing stages, and each processing stage is executed in one cycle of a clock.

  In the memory fetch stage, an instruction is fetched from the memory 4 to the instruction register IR. At the decode stage, the instruction fetched into the instruction register IR is decoded, and the arithmetic unit for executing the instruction at the subsequent execution stage is scheduled. In the decode stage, bypass processing for ending the pipeline for an instruction that does not need to be executed, such as a NOP instruction, and register fetch for fetching the contents of a register used for an operation are also performed.

  In the execution stage, arithmetic processing and address calculation are performed from the arithmetic unit scheduled in the decode stage and the contents of the fetched register. In the memory access stage, memory access is performed when there is an operand that requires memory access in the instruction.

  In the write-back stage, the operation result in the execution stage is stored in a register or the like, and the pipeline end process for the instruction is performed.

  FIG. 20 shows a bus configuration between the CPU 1 and the memory 4 of the microcomputer MCU. As shown in FIG. 21, by performing pipeline processing, each processing stage of instruction execution in the CPU 1 is caused to execute different processing stages with a plurality of instructions, thereby improving the effective processing performance per instruction. In this case, the memory access stage of an instruction having an operand that requires memory access and the instruction fetch have the same timing, resulting in a memory access conflict. For this reason, the Harvard architecture that separates the instruction bus 5 for fetching instructions from the memory access bus (data bus 3) for operands is employed to reduce the chance of occurrence of memory access conflict.

  The Instruction Interface described in FIG. 20 corresponds to the instruction register IR and instruction decoder iDEC described in FIG. Data Interface is an interface with the memory access bus, and performs memory access control for operands.

  By adopting the Harvard architecture and pipeline processing in the CPU 1, it is possible to avoid a memory access conflict (instruction fetch and operand fetch) performed by the CPU 1 and to improve instruction execution performance in the CPU 1.

  In so-called digital home appliances, there are a number of devices that perform moving image processing, such as DVDs (including high recording density standards) and digital TVs. In moving image processing, a DSP (Digital Signal Processing) operation such as a product-sum operation is repeatedly executed for each pixel.

  As shown in FIG. 22, in the DSP operation, the data for each pixel stored in the memory 4 is read out to the register for each operation and the operation is repeated. Become. For this reason, it is possible to execute an inter-memory product-sum operation instruction that directly reads two data used for the calculation from the memory 4 and performs multiplication, and performs addition processing with the already calculated result.

  In addition, it is possible to execute an inter-register product-sum operation instruction that similarly performs a product-sum operation on data stored in a register.

  In the product-sum operation using a large number of data stored in the memory 4 by the inter-memory product-sum operation instruction, it is possible to reduce the time for data transfer from the memory 4 to the register, and the processing efficiency of the arithmetic unit is improved. Since a transfer instruction for transferring data from the memory 4 to the register becomes unnecessary, the code efficiency is improved. Further, the product-sum operation using the data stored in the register by the inter-register product-sum operation instruction can be executed at high speed, and the processing efficiency of the arithmetic unit is improved.

  Further, in coordinate calculation or the like, it is necessary to repeatedly execute floating point calculation. As shown in FIG. 23, the floating point arithmetic unit has a dedicated data register different from the general-purpose register, and performs an operation using the dedicated data register. In such an operation, the process of transferring the data stored in the general-purpose register to the dedicated register is an overhead. For this reason, the data stored in the general-purpose register is configured so that the floating-point arithmetic unit can directly access and perform the calculation. With this configuration, it is possible to reduce the data transfer processing from the general-purpose register to the dedicated register, improve the processing efficiency of the arithmetic unit, and eliminate the need for a transfer instruction to transfer data from the general-purpose register to the dedicated register. improves.

  FIG. 24 shows another example of calculation using a product-sum calculator and a floating-point calculator.

  An analog signal from an external sensor or the like is digitally converted by an A / D converter and stored in the memory 4, and then the digitally converted sensor information stored in the memory 4 and the filter operation coefficient stored in the memory 4 are used. It is possible to perform a filter operation using an inter-memory product-sum operation instruction to remove noise included in the digitally converted sensor information.

  In motor control that performs rotation control by supplying a PWM (Pulse Wave Modulation) waveform to the motor, the motor current output from each phase (U / V / W phase) of the motor is digitally converted by an A / D converter. After storing in the register, coordinate conversion is performed by an inter-register product-sum operation instruction. The product-sum operation result stored in the general-purpose register is subjected to PID (proportional / integral / derivative) control operation using a floating-point arithmetic unit, and then the coordinate operation is performed again using the inter-register product-sum operation instruction. The PWM waveform is supplied to the motor as a motor control signal. Such a calculation makes it possible to repeat a calculation using a general-purpose register, and enables motor control at a short time interval as compared with a calculation using a dedicated register.

  FIG. 25 shows an analysis of a command having a high appearance frequency in the user application. By reducing the instruction size for frequent instructions, it is possible to reduce the execution program size of the user application and to improve the code efficiency. In addition, making a command with a high appearance frequency a command that is easier to use for the user leads to an improvement in usability.

  FIG. 26 shows an example of an instruction having a high appearance frequency and a reduced instruction size.

  Branch destination address as a relative instruction as a branch instruction used when a loop condition in a program or a multi-directional branch according to the value of a variable establishes or does not satisfy a loop condition or branches according to the value of a variable There are BEQ (conditionally satisfied branch), BNE (condition not satisfied branch), and BRA (unconditional satisfied branch).

  In the operation of these instructions, the address distance in the branching memory 4 is relatively short, and the code size of the branch instruction is set so that the branch distance is within 8 bytes, within 256 bytes, and within 65434 bytes, respectively. 1-byte, 2-byte, and 3-byte instructions can be used. As a result, the degree of freedom of selection by the user according to the branch distance is increased, and the code efficiency can be improved.

  Transfer instruction in register indirect addressing that specifies relative displacement value with reference to address value stored in register, comparison instruction or addition instruction that performs operation between immediate value (immediate value) and register, using register stored value as reference The code size of the instruction can be selected from 2 bytes to 8 bytes according to the range of values that can be designated as relative displacement values and immediate values. Alternatively, in an operation instruction that can specify the data width used for the operation of the register stored value, the code size can be selected from 2 bytes to 6 bytes in the multiplication instruction in accordance with the range of values that can be specified as the data width. Alternatively, the code size can be selected from 3 bytes to 7 bytes in the division instruction.

  Further, in the subroutine branch instruction, the instruction code size can be selected from 2 to 4 bytes by obtaining the branch destination address by calculation of the program counter stored value + register stored value.

  FIG. 27 shows an example of indexed register indirect addressing.

  In the indexed register indirect addressing, the register storing the base address and the register storing the offset address are added, and data transfer or the like is performed on the obtained address. In this case, when the byte size is specified, the offset address is added as it is and the base address is added. When the long word size is specified, the offset address is multiplied by 4 and the base address is added. . By adopting such an addressing specification, an instruction for adding an offset address and a base address is specified for a byte size specification, and a quadruple operation (2-bit left shift operation) for an offset address is specified for a longword size specification, an offset address and a base. It is possible to reduce the addition instruction with the address, and the code efficiency is improved.

  FIG. 28 shows an example of register indirect addressing with a post-increment / pre-decrement function.

  Post-increment / pre-decrement is mainly used when an operation is performed on a value stored in a table having a predetermined number of entries. Whether to use post-increment or pre-decrement, post-increment is used when calculation is performed from the lower address of the table, and pre-decrement is used when calculation is performed from the higher address of the table. When performing an operation from the lower address of the table, it is necessary to perform an operation on the value stored in the first table entry and then add an address referring to the value of the next table entry. Addition / subtraction of an address referring to a table entry by the post-increment / pre-decrement function can be performed by an operation instruction that performs an operation on a value stored in the table entry. Reduction can be achieved and code efficiency is improved.

  FIG. 29 shows an example of an operation that can specify three operands.

  When an addition instruction specifying two registers as operands is executed, the addition value and the addition value are stored in the respective registers, and the addition result is stored in the register in which the addition value was stored. In such a calculation operation, when the added value is used in another calculation, it is necessary to store the added value in another register or the memory 4 and to transfer the added value to the added value storage register for each calculation. .

  By making it possible to specify 3 operands in the register, etc., it becomes possible to specify that the operation result is stored in a register different from the added value storage register, and the added value is transferred to the added value storage register for each operation. It is possible to reduce the number of instructions to be executed, and the code efficiency is improved.

  FIG. 23 shows an example of a register configuration in the microcomputer MCU. The microcomputer MCU has a general-purpose register mainly used for calculation and a control register used for operation control of the microcomputer MCU.

  The general-purpose register may be divided so that it can be used as an 8-bit register or a 16-bit register used for operations with 8-bit data or 16-bit data with respect to the basic size (32 bits). However, in the microcomputer MCU according to the present embodiment, such register division is not performed, and all registers are used only in the basic 32 bits.

  When the registers are divided, access control between the partial registers to be operated and the partial registers that are not to be operated is required, which complicates the register control circuit, and increases the time overhead and power consumption of register access. Will be invited. General-purpose registers are accessed frequently during instruction execution, and even if the time overhead and power consumption increase during register access are small at a time, the time overhead and consumption of the entire program execution are small. Electricity is big.

  By not using the register division, it is possible to reduce the temporal overhead of register access and the power consumption. In addition, since the size of the general-purpose register is unified, the degree of freedom of the register that can be used in the compiler from the high-level language to the assembly language is increased, and the use efficiency of the general-purpose register is improved. Access frequency can be reduced. Also in this respect, it is possible to reduce the memory access overhead and power consumption in executing instructions.

  The control register includes a stack pointer (ISP, USP) in interrupt processing and subroutine processing, an interrupt table register (INTB) indicating the allocation address of the interrupt table, a program counter (PC) indicating the instruction address being executed, and instruction execution And a floating point status word (FPSW, CPEN) indicating the execution state of the floating point arithmetic unit and other coprocessors. Further, as dedicated registers for performing high-speed interrupt processing, a backup PSW (BPSW) and backup PC (BPC) for backing up PSW and PC, and a high-speed interrupt vector address (FINTV) for high-speed interrupt processing are provided.

  31, FIG. 32 and FIG. 33 show the case of high-speed interrupt processing.

  FIG. 31 shows a sequence of high-speed interrupt processing. In normal interrupt processing, in response to an interrupt notification from the interrupt controller INTC, the PSW and PC are saved in the stack area, the vector table is read according to the interrupt cause, the address of the interrupt processing routine is obtained, and the interrupt Branch to the processing routine. Also, when multiple interrupt notifications are notified or another interrupt notification is already made when interrupt processing is already in progress, the processing priority of interrupt processing is determined, and an interrupt mask is set according to the interrupt processing to be prioritized. Etc. Flag setting processing is performed. Among these processes, since the stack area and the interrupt vector table are allocated to the memory 4, memory access time is required for saving the PSW and PC to the stack area and reading the vector table.

  In high-speed interrupt processing, the PSW and PC are not saved in the stack area and accessed to the interrupt vector table, but are saved in the backup PSW and backup BPC prepared as control registers, respectively, and stored in the high-speed interrupt vector address. Branches to the interrupt processing routine. With such processing, memory access can be reduced in high-speed interrupt processing, and branching to interrupt processing can be speeded up.

  FIG. 32 shows general-purpose register allocation in interrupt processing. In normal interrupt processing, the data stored in the general-purpose register used by the application before branching to interrupt processing is rewritten during interrupt processing, and the application continues execution after returning from interrupt processing. In order not to cause inconvenience, data stored in the general-purpose register is saved in the stack area, or the register bank used when branching to the interrupt processing is switched to a different bank. This saving to the stack area is realized by generating a memory access, and in actuality even by switching the register bank, the data stored in the register is saved to the area of the memory 4.

  In order to speed up branching to interrupt processing, general-purpose registers are assigned to application registers and interrupt registers, respectively. Registers used for applications are used during application execution, and interrupts are executed during interrupt processing. Control to use registers. Application registers and interrupt processing registers can be assigned and set by a program, increasing the degree of freedom of register assignments, and eliminating the need to save general-purpose registers, speeding up the start of interrupt processing execution Is possible.

  As shown in FIG. 33, interrupts can be achieved by reducing memory access (saving high-speed interrupt processing) by saving PSW and PC and acquiring interrupt vector addresses, and switching general-purpose registers from application registers to interrupt-use registers (general-purpose register allocation). It is possible to shorten the time until the start of the interrupt processing corresponding to the interrupt notification after the notification is made, and to improve the program execution efficiency of the microcomputer MCU.

  FIG. 34 shows memory protection. When application A and application B are assigned a memory area for application A and a memory area for application B, respectively, application A erroneously accesses the memory area for application B and rewrites data used by application B Or, if an accidental branch from the application A to the application B occurs, the execution operation of the application B becomes unstable, and the operation of the microcomputer MCU as a whole becomes unstable.

  In order to prevent the occurrence of such a situation, a memory protection unit is provided to prevent the application A from accessing the memory area for the application B or branching from the application A to the application B. As a result, the execution operation of the application B is prevented from becoming unstable, and the operation of the microcomputer MCU as a whole can be stabilized.

  FIG. 35 shows an example of the endian conversion instruction.

  The bi-endian processing of data has been described as the third and fourth embodiments. However, after the data stored in the memory area to be processed as little endian is read into a general-purpose register and subjected to a predetermined operation, the big endian processing is performed. As a result, data may be transferred to a memory area where data processing is performed or a peripheral I / O device for big endian. In such a case, by setting the control signal CNT1 to the aligner 11 or the control signal CNT2 to the aligner 13, it is possible to change the arrangement of data in the aligner 11 or the aligner 13. When data conversion is performed continuously to some extent, it is effective to change the data arrangement by the aligner 11 or the aligner 13.

  On the other hand, in the case where data is alternately converted into little endian and big endian and stored in the memory area, it is necessary to set the aligner 11 or aligner 13 to perform endian conversion alternately. In such a case, it is possible to reduce the power consumption related to the setting change of the aligner 11 or the aligner 13 by converting the endian of the data in the register by the endian conversion instruction and not changing the settings of the aligner 11 and the aligner 13. It may be possible.

  36, 37 and 38 show an example of a design method for reducing the power consumption of the microcomputer MCU.

  Since logic elements such as flip-flops and clock drivers placed in the clock supply path flow current as long as the clock is supplied, it is necessary to stop supplying the clock to unused circuits. is there. Therefore, as shown in FIG. 36, a clock gating circuit is inserted when logic synthesis of the microcomputer MCU is performed so that the clock supply can be stopped.

  Next, in the clock synchronous design, when a logic element that performs clock asynchronous operation is arranged so as to be sandwiched between flip-flops that perform clock synchronous operation, a path (critical path) that causes timing violation occurs between the flip-flops. It is necessary to eliminate such timing violation. As shown in FIG. 37, first, clock synchronous design is performed using a low-speed high threshold voltage / low leakage current logic element, and a low threshold voltage / high leakage current is high speed only for the critical path. To eliminate timing violation. By performing such a clock synchronous design, a large number of logic elements constituting the microcomputer MCU become low-power consumption logic elements, and in the low-power consumption logic elements, the path for generating timing violation is faster with higher power consumption. This makes it possible to design a clock synchronization of the microcomputer MCU that consumes less power as a whole.

  Further, as shown in FIG. 38, the inside of the microcomputer MCU is divided into a plurality of power supply domains, and a plurality of low power consumption modes are provided so as to stop the power supply to the non-operating power supply domains. In this case, the built-in regulator inside the microcomputer MCU supplies power to each power domain, and a switch circuit that supplies power to the power domain or stops is arranged between the built-in regulator and the power domain.

  FIG. 39 is a diagram showing the influence of the access speed of the flash memory on the processing performance of the microcomputer MCU when the flash memory is used as the ROM for storing the program. When a flash memory that can be read at 30 MHz is used for the microcomputer MCU, even if the microcomputer MCU is operated with a clock of 100 MHz, a wait operation of a plurality of clock cycles is required every time an instruction is fetched. Execution performance will drop significantly from 100 MHz.

  In order to avoid such a decrease in execution performance, it is conceivable to arrange an instruction cache memory between the flash memory and the CPU 1. By arranging the instruction cache memory, when the CPU 1 fetches an instruction stored in the instruction cache memory (cache hit), the instruction can be fetched in one clock cycle, but the instruction is stored in the instruction cache memory. If not (cache miss hit), a wait operation in a plurality of clock cycles is required, and the area occupied by the instruction cache memory is required.

  The flash memory can be operated at 100 MHz by increasing the memory array configuration of the flash memory and the speed of peripheral logic circuits such as an address decoder, and the CPU 1 can operate every clock cycle without having an instruction cache memory. In addition, even when the operation clock of the microcomputer MCU is further increased, it is possible to reduce the number of clock cycles to wait when a cache miss hit occurs.

  It goes without saying that the configuration, function, operation, and the like of the microcomputer MCU and CPU 1 described in the sixth embodiment can be applied to the microcomputer MCU and CPU 1 of the first to fourth embodiments.

  While the embodiments of the present invention have been disclosed and described in detail above, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

1 CPU, 2 address bus, 3 data bus, 4 memory, 5 instruction bus, 9 registers, 11, 13 aligner, 14 big endian peripheral data bus, 17 little endian peripheral data bus, BSC bus controller, INTC interrupt controller, PC program counter, IR instruction register, iDec instruction decoder

Claims (8)

A CPU having a register;
With bus,
An interrupt controller;
With memory,
The CPU acquires an instruction from the memory via the bus, performs operation control according to the instruction, and executes an interrupt processing program in order to perform processing according to the interrupt notification according to the interrupt notification from the interrupt control unit. Get the storage address,
The memory stores a first area for storing first data used for processing in the first program and the first program, and a second area for storing second data used for processing in the second program and the second program. Divided into an area, a third area for storing the interrupt processing program, and a fourth area for storing a storage address of the interrupt processing program;
The first program and the second program have different endian data in each processing,
Regardless of whether the first program is being executed or the second program is being executed, in the data transfer for obtaining the storage address of the interrupt processing program from the memory, output from the memory to the bus A semiconductor integrated circuit device that can be obtained without changing the order of the data in byte units.   The storage address of the interrupt processing program has a data size that can be transferred in one data transfer via the bus, and the storage address of the interrupt processing program is transferred to the CPU by one data transfer. Semiconductor integrated circuit device. When the first data is acquired by a single data transfer with the same data size as the storage address of the interrupt processing program during execution of the first program, and the second data is acquired by the interrupt during execution of the second program In the case of acquiring by one-time data transfer with the same data size as the storage address of the processing program, it can be transferred and processed to the register without changing the order of data output from the memory to the bus in byte units. Yes,
When the first data is acquired by a single data transfer with a data size different from the storage address of the interrupt processing program during execution of the first program, and the second data is acquired by the interrupt during execution of the second program Processing can be performed by changing the order of data output from the memory to the bus in byte units and transferring it to the register when the data is acquired at a single data size different from the storage address of the processing program The semiconductor integrated circuit device according to claim 1. The bus has an instruction bus used for acquiring the instruction and a data bus used for data transfer of the first data or the second data;
2. The semiconductor integrated circuit device according to claim 1, wherein acquisition of a storage address of the interrupt processing program in response to the interrupt notification is performed using the data bus.   2. The semiconductor integrated circuit device according to claim 1, wherein the bus is connected to an aligner for changing the order of data in units of bytes in data transfer with the memory.   The aligner is supplied with a control signal generated from identification information indicating whether the acquisition of the first data or the acquisition of the second data and information indicating the data transfer size, and the order of the data in byte units 6. The semiconductor integrated circuit device according to claim 5, wherein the change of the control is controlled. The bus is connected to a second aligner;
The second aligner is connected to the first peripheral circuit via the first peripheral bus, and is connected to the second peripheral circuit via the second peripheral bus;
The first peripheral circuit and the second peripheral circuit have different endian data in the processing in each,
In the data transfer between the first peripheral circuit or the second peripheral circuit and the register or the memory, the second aligner performs data transfer with a data transfer size for acquiring a storage address of the interrupt processing program. Is different from the data transfer size for controlling the data transfer without changing the byte order of the data output to the first peripheral bus or the second peripheral bus and obtaining the storage address of the interrupt processing program. 2. The semiconductor integrated circuit device according to claim 1, wherein in data transfer at a transfer size, control of data transfer is performed to change the order of data output to either the first peripheral bus or the second peripheral bus in byte units. .   8. The semiconductor integrated circuit device according to claim 7, wherein the first peripheral circuit is controlled by the first program, and the second peripheral circuit is controlled by the second program.

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