JP2006313561A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve branching and subroutine branching by minimizing an increase in logical/physical scales, maintaining compatibility with existing CPUs, and determining the state of the bits of data at an arbitrary address in a memory. <P>SOLUTION: For commands for branching according to the state of the bits of data in a memory, an operation field for prescribing an operation is divided into a plurality of portions for achieving by separate words on the basic unit of a command code, and the word is shared with the code of another command that can be used independently or one portion of the code of another command. The first word of the command code transfers data between a latching means (TRD) that has not been released in terms of a program and a memory. The second word determines the state of the desired bits of the latching means for branching. The latching means has a means (38) for determining the state of the specified bit, thus determining the state of a prescribed bit without reading out to an ALU, or the like. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a data processing apparatus such as a microcomputer, a microprocessor, a data processor, and a CPU (Central Processing Unit), and more particularly to a register architecture, upward compatibility, expansion of arithmetic performance, etc. The present invention relates to a technology that is effective when applied to effective utilization of software assets in microcomputers, expansion of computing performance, improvement of usability, and the like.

  A microcomputer integrated with a semiconductor integrated circuit has been attempted to expand an address space, expand an instruction set, and increase speed. Since the functions of the CPU (central processing unit) of the microcomputer are defined by software, the software of the existing microcomputer can be used in microcomputers that have expanded the address space, expanded the instruction set, and increased the speed. It is desirable that assets can be used effectively.

  For this reason, as an example of realizing address space expansion and instruction set expansion while maintaining compatibility at the object level, for example, there is a microcomputer described in JP-A-6-51981. Among these, it has been shown that adopting a load store type architecture such as a so-called RISC (Reduced Instruction Set Computer) architecture is effective in extending the instruction set.

  In the load store type architecture, arithmetic processing is performed using a general-purpose register of the CPU. In other words, the data on the memory is not directly used for the operation, but the data on the memory is once transferred to the general-purpose register, the operation is performed on the transferred data, and the operation result on the general-purpose register is stored on the memory. Write back. Therefore, if there is a general-purpose register that is not used in the processing, the data on the memory may be transferred to the general-purpose register. However, the number of general-purpose registers is limited, and all general-purpose registers may be used depending on the processing status inside the microcomputer. When all the general purpose registers are used, in other words, when the contents of all the general purpose registers must be retained, the contents of the general purpose registers are stored in the stack area before performing the operation on the data on the memory. After saving, the necessary processing is performed, and after this processing is completed, the contents of the saved general-purpose register must be restored in order to resume the interrupted processing.

JP-A-6-51981

<< Exercise A >>
The present inventor considered increasing the number of general-purpose registers of the CPU while maintaining compatibility and enabling effective use of software assets as the examination subject A. The matter relating to the examination subject A is already disclosed in the specification of Japanese Patent Application No. 11-123450, which is the first basic application claiming domestic priority in the present application, but is not yet known. This examination subject A will be described.

  In a CPU adopting the load store architecture, since data processing is centered on general-purpose registers of the CPU, it is convenient that there are many general-purpose registers. As a result, the program can be facilitated and speeded up.

  However, which general register is to be processed is generally designated by an instruction code, so it is necessary to hold a register designation field corresponding to the number of general purpose registers in the instruction code. For example, for 16 general purpose registers, 4 bits are required for the register designation field. If an attempt is made to increase the general-purpose registers, the register designation field increases. If the number of general-purpose registers is four times 64, 6 bits for the register designation field are required. Since the processing target is generally two pieces of data (source and destination), the register designation field requires twice as many bits.

  If the basic unit of an instruction is, for example, 16 bits (hereinafter referred to as a word), the number of bits occupied in the register designation field increases, and eventually the instruction code length must be increased. If the instruction code is lengthened, the processing speed is reduced. This is because the CPU reads and executes instructions, but the number of instructions read increases as the number of words (number of bits) of the instruction to be read increases. Also, enlarging the register designation field is incompatible with the existing instructions of the existing CPU and makes it difficult to maintain compatibility with the existing CPU.

  As a technique for apparently increasing the general-purpose registers, there is a register bank system in which the general-purpose registers are divided into groups called banks and any one of the banks is exclusively selected. Which bank is selected is specified by a control register or a control instruction. Therefore, the instruction code has only a register designation field corresponding to the general-purpose register in the bank, and an increase in the instruction code length can be suppressed. However, an instruction for switching the register bank is required, and when creating a program, it is necessary to be aware of which bank is selected, and the ease of programming tends to be impaired. Since the number of general-purpose registers that can be used at the same time has not increased, it is difficult to interchange general-purpose register assignments when there are tasks with a large amount of data or tasks with a small amount of data.

  An object of the present invention related to the examination subject A is to provide a data processing apparatus capable of increasing the number of general-purpose registers while maintaining upward compatibility.

  Another object of the present invention relating to the examination subject A is to provide a data processing apparatus capable of increasing the number of general-purpose registers without increasing the overall instruction code.

  Another object of the present invention relating to the examination subject A is a data processing device capable of realizing easy program creation and improved CPU processing performance by increasing the number of general-purpose registers while maintaining upward compatibility with software assets. Is to provide.

<< Exercise B >>
The present inventor makes it possible to maintain compatibility with a load store type architecture and the like so as to effectively use the software asset (achieve upward compatibility with the software asset) as a study subject B. We examined how data on the memory can be directly calculated while maintaining the advantages of the existing CPU such that the architecture is advantageous for improving the operation speed. The matters concerning the examination subject B have already been disclosed in the specification of Japanese Patent Application No. 11-151890, which is the second basic application claiming domestic priority in the present application, but the contents are not yet known. This examination subject B will be described.

  The advantages considered to be obtained by making the data on the memory directly operable are as follows.

  All data that can be used by the CPU or microcomputer as long as it can operate on the data in the memory without loading the data into the general-purpose register and performing the operation. In other words, since all the data that can be specified on the program by the microcomputer user can be operated, the usability, that is, the function of the microcomputer is improved.

  In this case, the instruction executed by the CPU specifies the location of data and the processing content. A method for designating the location of data is called an addressing mode. If calculation of data on the memory is enabled only in a specific addressing mode, programming restrictions occur and the ease of use cannot be sufficiently improved. It would be desirable to be able to compute data on the memory by any combination of addressing modes that access data with an existing CPU.

  Even if the data on the memory can be directly calculated, it is desirable to process the frequently used data on a general-purpose register. Since the general-purpose register is physically configured as part of the CPU, it can be accessed at a higher speed than the memory and can be processed at a higher speed than the data on the memory. Data that is used infrequently may be processed while being placed on the memory. There is no need to save / restore general-purpose registers that are not directly related to CPU processing. As a result, the processing speed of the CPU can be improved as a whole.

  Usually, the amount of data processed by the CPU or microcomputer is larger than the number of general-purpose registers of the CPU. In addition, since there are multiple tasks and these are executed in a time-sharing manner, if the data on the memory can be directly calculated when the task is switched, the data can be saved in the memory without being saved or restored. On the other hand, it becomes possible to execute processing immediately. A convenient method can be selected while intermingling with a processing method of performing a high-speed operation using a general-purpose register while accompanying a save / restore process. Similarly, during interrupt processing, it is possible to immediately execute processing on the memory without saving the general-purpose registers, and the response time until the desired processing is performed in response to the interrupt can be increased. It can also be shortened. By shortening the response time of interruption, it is possible to improve the time accuracy when controlling various devices, so-called real-time property.

  If a program that loops (repeats) the same processing routine is created, general-purpose registers necessary for arithmetic processing in the loop are secured, the overall program capacity is reduced, and the processing time is shortened. Therefore, by securing a register for allocating data to be used outside the loop, it becomes possible to perform arithmetic processing on the memory at any time even when the general-purpose register has no room. This facilitates program creation. Further, it is expected that the processing time can be shortened in proportion to the number of repetitions by shortening the processing in the loop.

  In developing a development apparatus such as a C compiler, it is necessary to consider such various conditions, and by enabling operations on a memory, a development period and time required to achieve a desired performance of the C compiler It is possible to save resources.

  Further, the above-mentioned speeding up, high functionality, and miniaturization of devices are also required in a CPU or microcomputer having a relatively small address space and a relatively small instruction set. When there is a CPU with a wide address space and a CPU with a narrow address space described in the publication, it is desirable to add an operation for data in the memory to both of them.

  However, the present inventor has revealed that there are the following problems in achieving upward compatibility with the software assets and enabling direct calculation of memory data.

  Since the existing instruction set is optimized within the specifications, there is little room for assigning a new instruction code to processing such as various operations that can directly calculate data on the memory. In other words, for a desired operation such as addition or logical product, it is actually not possible to assign a new instruction code such that the data on the memory can be operated in any combination of addressing modes for accessing the data. Hard to think.

  Also, changing the instruction code system by adding a new instruction code or a new addressing mode is incompatible with existing instructions in the existing CPU, and it becomes difficult to maintain compatibility with the existing CPU. . Moreover, the merit of the existing CPU is lost.

  Further, when developing a system using a microcomputer, a development device called an emulator is used. The emulator includes an emulation processor including a microcomputer function, and the emulation processor outputs an emulation signal for enabling the emulator to analyze the operation state of the microcomputer. An emulator and an emulation processor are described in JP-A-8-263290. When changing the configuration of the microcomputer so that the data in the memory can be directly operated, if the emulation signal is also changed, the hardware of the emulator itself must be changed, and the emulator itself is also new. However, it has become clear that there is a problem that the provision of a microcomputer development device or development environment becomes slow.

  The purpose of the present invention related to the examination subject B is to minimize the increase in logical and physical scale, and maintain compatibility with an existing CPU or microcomputer having a load / store type instruction set. It is an object of the present invention to provide a data processing device that enables direct computation on data on a memory.

  Another object of the present invention related to the examination subject B is to make it possible to perform operations on data on the memory, thereby facilitating programming and suppressing undesired general-purpose registers from being saved / returned. By improving the processing performance.

<< Exercise C >>
In order to realize the upward compatibility with the software asset examined as the examination subject A and the ability to directly calculate the data of the memory examined as the examination subject B, the present inventor further describes the following examination subject C as Was revealed. The matters relating to the examination subject C have already been disclosed in the specification of Japanese Patent Application No. 11-191608, which is the third basic application claiming domestic priority in the present application, but the contents are not yet known. This examination subject C will be described.

  Since the existing instruction set is optimized within the specifications, there is little room for assigning a new instruction code to processing such as various operations that can directly calculate data on the memory. In other words, for a desired operation such as addition or logical product, it is actually not possible to assign a new instruction code such that the data on the memory can be operated in any combination of addressing modes for accessing the data. Hard to think.

  Also, changing the instruction code system by adding a new instruction code or a new addressing mode is incompatible with existing instructions in the existing CPU, and it becomes difficult to maintain compatibility with the existing CPU. . Moreover, the merit of the existing CPU is lost.

  Therefore, the present inventor uses a pre-instruction code that combines and combines a plurality of instruction codes among existing one or more transfer instructions between memory and registers and arithmetic instructions between registers and registers. First, we found the usefulness of enabling operations on memory. According to this, since the instruction codes such as the transfer instruction between the memory and the register and the operation instruction between the register and the register are already existing, the operation code alone does not hinder the execution of the existing instruction. . Also, if only existing instructions are used, existing software assets can be used effectively. The arithmetic performance can be expanded without losing the merits of existing CPUs such as general-purpose register system and load / store architecture.

  Furthermore, the present inventor also examined various requirements for microcomputers having a wide application field. For example, an application field with a wide address space and an application field with a small address space, an application field mainly using programming in a high-level language, an application field mainly using programming in assembly language, an application field in which data processing is important, bit manipulation, etc. There are application fields that require control, application fields that require processing performance, and application fields that require lower cost than processing performance. For these, we provide a CPU (Central Processing Unit) with a consistent architecture, It is desirable to be able to commonly use development devices such as software development devices (cross software) such as assemblers and C compilers.

  Therefore, the present inventor studied a CPU having backward compatibility. As described above, according to the previous proposal by the present inventor, it is possible to add a general-purpose register or an operation for a memory while maintaining compatibility even with an existing CPU having a small address space. . In the case of adding functions, the present inventor has found a need to consider so as to sufficiently meet various requirements for the microcomputer, such as pursuing cost reduction. .

  Also, in assembly language programming, there is a large part that depends on the CPU instruction set, and there are also preferences such as the user's experience, so it is not possible to respond to all requests with one instruction set. Can not. For example, another CPU or a CPU having a command set that suits the user can easily migrate, but a CPU having the same command set has a limit.

  There are general-purpose register system and accumulator system in the microcomputer or CPU architecture, so if you have a CPU with an instruction set similar to each of them, it will be possible to meet the instruction set requirements of most users. It is done. By preparing a CPU having at least one type of instruction set rather than at least one instruction set, the applicable range can be greatly increased.

  At this time, even if a large number of independent CPUs are prepared, if compatibility and software portability are impaired, software cannot be ported for the user and the software may be changed. This tends to undesirably increase the overall development cost and undesirably increase the development period. On the other hand, for a CPU or a microcomputer provider, the technology used is different for an independent CPU, and it becomes difficult to apply the technology obtained with one CPU to another CPU, thereby improving the development efficiency. It is difficult to improve the function and performance.

  When developing a system using a microcomputer, a development device called a software development device and an emulator is used.

  For software development devices such as assemblers, C compilers, simulator debuggers, etc., a plurality of compatible CPUs such as those described above, including CPUs that do not have an instruction set that includes the other, are commonly used. The inventor has shown that it is desirable to be able to use it. If the user can also apply the software development apparatus in common to different CPUs, it is not necessary to generate undesired expenses when changing the CPU. The provider only needs to develop one development device, so that the development efficiency can be improved, and the functions of the development device and the usability can be easily improved as appropriate. While enjoying the ease of programming in assembly language, it becomes possible to move to higher-level languages sequentially.

  In JP-A-9-198272, there is a description of an emulator and an emulation processor that are compatible with a plurality of CPUs, one of which includes the other instruction set and register configuration. Such a plurality of CPUs cannot sufficiently meet various requirements such as application fields. It may be possible to prepare a higher-level CPU that includes both functions for a plurality of CPUs, one of which does not include the instruction set of the other, but the instruction codes may be different for completely different CPUs. Since the address space and effective address calculation method are different, it is difficult to configure an upper CPU that includes the address space and effective address calculation method. Moreover, even if possible, it is considered that a large development resource is necessary for this purpose, and the purpose of saving various resources necessary for development cannot be achieved. Furthermore, since the host CPU includes functions of a plurality of different CPUs, it has redundant circuits, making it difficult to use in actual products, and switching to individual CPUs. Therefore, it cannot be said that it is a new CPU, and the purpose of responding to various requests such as application fields cannot be achieved.

  An object of the present invention related to the examination subject C is to provide a data processing apparatus that can meet a wide range of requirements of application fields and users. Specifically, the manufacturing cost as a semiconductor integrated circuit is reduced, and hence the cost of the user for the semiconductor integrated circuit is reduced, the software requirement of the application field is easily met, or the assembly language is used. To make it easy to make programming, or to make it easy to migrate from another CPU according to the user's preference for the microcomputer.

  Secondly, the object of the present invention related to the examination subject C is to reduce the development cost of a data processing apparatus product group such as an overall microcomputer and to improve the development efficiency. In other words, it is to provide a plurality of CPUs suitable for individual application fields and systems, reduce the overall development cost of the plurality of CPUs, and improve the development efficiency. Specifically, to maintain compatibility and inheritance of software assets, improve the software development efficiency of users, respond to requests for improvements in functions and performance, and continue to request improvements in functions and performance To prevent the user's undesired expenses when migrating the CPU, and the development environment such as software development devices and emulators can be used in common to prevent the user's undesired expenses from increasing Or to easily improve the development efficiency of the development environment and improve it as appropriate.

  Third, the object of the present invention related to the examination subject C is to provide a data processing apparatus such as a CPU having an address space suitable for a single chip microcomputer or the like having a relatively large program capacity but a relatively small data capacity. That is, it is to provide a data processing device such as a CPU having a wide address space and a reduced logical scale.

<< Examination subject D >>
The present inventor examined a complex instruction that contributes to shortening the instruction code length and improving the processing performance from the viewpoint of a branch instruction, as a new examination problem D related to the examination problem B. This examination subject D is described.

  In a general microcomputer system, the processing of the CPU is adapted to the external input state. This is done by branching the program according to the state of the input / output port or based on the state of the bit held in the built-in RAM or the like.

  As means for realizing the processing of the CPU corresponding to such an external input state, there is a data processor having an instruction such as so-called bit test and branch as described in US Pat. No. 4,334,268. In this case, the bit to be tested is designated by an 8-bit absolute address and a 3-bit bit number, and whether the branch condition is the logical value “1” state or the logical value “0” state of the designated bit. Is specified by 1 bit, and the branch destination address is specified by an 8-bit displacement. In this case, in the case of a 3-byte instruction code, the instruction must be specified by 4 bits. In this example, a bit test-and-branch is one in which the first 4 bits of the instruction code have a logical value “0”. Therefore, the other instructions must have the first 4 bits having values 1 to F, which tends to increase the overall instruction code length.

  Such an instruction is complicated in instruction execution control such as read / determination of a designated bit and generation of a branch address, and tends to increase the logic scale, and the operating frequency is improved by delay of an undesired logic circuit. It has been made clear by the present inventor that it is likely to be an obstacle.

  Furthermore, since it is limited to 256 bytes that can be specified by an 8-bit absolute address, when the number of internal I / O registers is increased as the microcomputer becomes more sophisticated, a desired range can be specified. Bits do not exist, and address arrangement becomes difficult due to the design specification of the microcomputer. In other words, the microcomputer can be used for general purposes, but there are a plurality of different bits to be judged for each application field or user, and all the desired combinations for the bits to be judged are all different. It is difficult to meet the demands.

  Further, when the control is complicated, there are cases where branching cannot be performed with an 8-bit relative address. Since branching is possible only within the range of +127 to −128 bytes with reference to the address where the instruction exists or the address where the next instruction exists, when the bit to be judged is the logical value “1” or the logical value “0” At least one of the processing programs executed at this time (the processing program executed when the branch condition is not satisfied) needs to be less than 127 bytes. If this is not satisfactory, another branch instruction must be used to branch to the required address by executing a two-stage branch instruction. It has been clarified by the present inventors that this complicates the program and reduces the processing speed.

  On the other hand, if the absolute address or displacement is set to 16 bits, the instruction code length is inevitably increased, the processing speed is lowered, and the instruction execution control is further complicated. If there are a plurality of combinations of absolute address and displacement bit length, the instruction execution control becomes more complicated. These increase the types of instructions to be added, making it difficult to maintain upward compatibility of existing CPUs. It makes it difficult to maintain the advantages of existing CPUs (such as simplicity of logic configuration and high speed).

  The object of the present invention regarding the consideration D is to determine the bit state of data at an arbitrary address on the memory while minimizing an increase in logical and physical scale and maintaining compatibility with an existing CPU. It is to enable branching and subroutine branching. It is another object of the present invention to improve the usability of the CPU, shorten the instruction code length, and improve the processing performance.

<< Examination subject E >>
The present inventor studied as a study subject E that reading / writing is performed on a plurality of general-purpose registers or the like with a single instruction. In addition, although the matter regarding this examination subject E has already been disclosed in the specification of Japanese Patent Application No. 11-320518, which is the fourth basic application claiming domestic priority in this application, the contents thereof are not yet known. This examination subject E is described.

  Information such as a packet command at the time of data transfer is a set of a plurality of pieces of information, for example, 16 bytes, which is larger than the data processing unit of the CPU. The CPU reads and analyzes individual information (command, number of transfer bytes, transfer location, etc.) included therein. For example, the command is 8 bits, the number of transfer bytes is 32 bits, the transfer location (address) is 32 bits, etc., and these individual pieces of information are often data lengths that can be manipulated by the CPU.

  The print data of the printer is longer than the data length operated by the CPU. These are a collection of individual bits (dots, pixels, etc.). When this is operated, it is not an arithmetic process but a bit unit process, and a logical process is mainly necessary. When processing such data, it is divided into a plurality of data units operated by the CPU. That is, the process of reading data from the memory, performing processing on the general-purpose register, and writing the result to the memory is repeated.

  The present inventor further examined the use mode of the general-purpose register. The packet command and print data are larger than a data unit of data processing by the CPU such as a word. If the data unit larger than the data unit of the data processing by the CPU can be read from the register or written to the register at a time, it is advantageous for speeding up the data processing. Found. Specifically, in a so-called von Neumann type CPU, when executing a transfer instruction, it is necessary to read an instruction code, decode it, and read / write data. Rather than repeating multiple data register transfers multiple times, the number of times the instruction code is read for data transfer can be reduced by reading / writing multiple general-purpose registers with a single instruction. Because.

  Furthermore, when combined with the technology for extending general-purpose registers with the abbreviated words, it is easy to expand general-purpose registers and thereby free up a plurality of general-purpose registers for reading / writing in a batch. I found out that

  On the other hand, the CPU described in Japanese Patent Application Laid-Open No. 8-263290 previously proposed by the present inventors uses a combination of a plurality of general-purpose registers that can be specified for the control means for controlling the execution means for executing instructions. The plurality of general-purpose registers are sequentially saved / restored by having a save / return instruction for the stack of the plurality of general-purpose registers. This is limited to processing for the purpose of saving the state of the previous processing at a processing break, such as a subroutine or exception processing. Therefore, the addressing mode is also limited to pre-decrement (save) / post-increment (return) of the stack pointer. In addition, address calculation is performed using an address calculator every time the general-purpose register is saved / restored.

  If the technique described in Japanese Patent Laid-Open No. 8-263290 is applied to another addressing mode, for example, in the case of a register indirect read in a transfer instruction between four general-purpose registers and a memory, the second and later For each general-purpose register, it is necessary to generate an effective address by performing +4, +8, and +12 address arithmetic processing on the contents of the address register. On the other hand, in the case of writing, it is necessary to generate an effective address by performing arithmetic processing of -12, -8, and -4 on the contents of the address register for each general-purpose register other than the last. For this reason, an effective address calculation is required for each register, and an undesired internal operation state occurs.

  Further, in the register indirect with displacement, it is necessary to hold the result of adding the contents of the displacement and the address register inside, and to perform the same address calculation as the register indirect on the addition result. These complicate the internal operation of the CPU and tend to increase the logical scale.

  In general, it is desirable in terms of development efficiency and the like that a microcomputer can be used for general purposes (one chip can handle a plurality of application fields). In particular, since a CPU requires a software development device such as an assembler or a C compiler and a hardware development device such as an in-circuit emulator, it is not easy to change the architecture of the microcomputer. It is desirable to maintain compatibility with the CPU, to make the software or hardware development apparatus available in common, and to improve development efficiency.

  There is also a microcomputer in which an instruction set, such as a block transfer instruction, is an instruction set for continuously transferring a plurality of units of data on a memory. With such an instruction, the transfer data is not stored in the general-purpose register of the CPU, so that the data cannot be directly manipulated, or at least as fast as the general-purpose register.

  The object of the present invention related to the examination subject E is to reduce the logical scale of the data processing apparatus or data processing system such as a microcomputer while minimizing the logical size, for example, byte, word, long word. For example, when it is necessary to process larger data, the CPU processing program is shortened and the data processing speed of the CPU is increased. More specifically, the present invention is intended to reduce the frequency of instruction read for data read / write so as to increase the data processing speed.

  Another object of the present invention relating to the examination subject E is that the software resources of the existing CPU can be used effectively, the development efficiency of a new system can be improved, the system generator of the existing CPU can be diverted, and the development environment can be It is an object of the present invention to provide a data processing apparatus that can be quickly relied upon.

  Still another object of the present invention relating to the examination subject E is that the increase in the number of general-purpose registers can be specified by software for an existing CPU, and this can be used to facilitate program creation and register read / write operations. An object of the present invention is to provide a data processing apparatus capable of improving the processing performance of a CPU by increasing the rate.

  Another object of the present invention relating to the examination problem E is to maintain compatibility at the object level, and when there is a CPU having a wide address space and a CPU having a small address space, the CPU is maintained while maintaining compatibility at the object level. An object of the present invention is to provide a data processing apparatus capable of achieving the objectives such as shortening of a processing program and high-speed processing by a CPU.

  The present invention relating to the above-described examination problems A to E has a common problem to be solved in terms of expansion of calculation performance and improvement in usability of the data processing apparatus. Further, there is a common problem that processing is possible without saving / restoring data of general-purpose registers, which are high-speed but limited in number.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

<< Solutions for Examination A>
As means for solving the problem A, register designation information for designating a register is divided into two parts. These two parts are arranged in different basic units on the basic unit of the instruction code. If one instruction code is omissible and the omissible instruction code is omitted, the register selection operation is performed by implicitly assuming predetermined register designation information.

  The instruction code that can be omitted may be an instruction code that has a field for holding a part of the register designation information and does not designate the type of operation. For example, an instruction code that cannot be omitted may be shared with an existing CPU, and the instruction code that can be omitted may be assigned to an undefined word of the existing CPU.

  Means for holding register designation field information included in an optional instruction code is provided, and when the optional instruction is executed, information in the register designation field included in the optional instruction code is stored in the holding means. Store. Further, at the end of execution of the instruction, the holding means is set to a predetermined value corresponding to the implicit designation.

  According to the above-described means, if only the general-purpose register that can be specified implicitly (existing general-purpose register) is used, the instruction code that can be omitted can be omitted, and the instruction code length is not increased. If at least a conventional equivalent general-purpose register is used, a conventional equivalent instruction code may be used. By not increasing the instruction code length, the processing speed is not reduced.

  By adding the optional instruction code, all of the general purpose registers can be directly selected by the instruction, so that the number of available general purpose registers can be increased without impairing the ease of programming. In addition, by securing a part of an arbitrary amount of general-purpose registers for each desired task or desired interrupt processing (not used in other tasks or processing), the general-purpose registers can be set in the task or interrupt processing. There is no need to evacuate and speed up can be achieved. In addition, since the number of general-purpose registers reserved for the task and interrupt processing can be arbitrarily set, it is easy to interchange the general-purpose registers to be used between tasks and processing.

  By adding the optional instruction code, the access to the general-purpose register that can be specified is generally faster than the access to the memory such as RAM. Therefore, by increasing the number of general-purpose registers, the amount of data that can be processed at a high speed This increases the processing speed of the CPU. For processors that have a so-called load / store type instruction set and cannot directly operate on the contents of memory, the amount of data that can be directly processed can be increased by increasing the number of general-purpose registers. Can be reduced, and the processing speed can be improved.

  When there is a CPU with a wide address space and a CPU with a small address space while maintaining compatibility at the object level, if the CPU can have a wide address space and the optional instruction code can be added, it has backward compatibility. Since the word can be added to a CPU having a small address space, general-purpose registers can be added to a CPU having a wide address space and a CPU having a small address space while maintaining compatibility at the object level. You can enjoy both the benefits of maintaining compatibility at the object level and the benefits of adding general purpose registers.

  Reference will be made to more detailed aspects of the above means. A data processing device that operates by reading an instruction code and has a plurality of registers (ER0 to ER31) capable of storing data or addresses includes a first instruction code holding means (IR1) that holds the instruction code, and a second instruction Code holding means (IR2), instruction decoding means (DEC) for decoding the instruction code, and selection means (RSEL) for selecting the register are included. The output of the first instruction code holding means is coupled to the second instruction code holding means, the instruction decoding means and the register selection means, and the output of the second instruction code holding means is sent to the register selection means. And the output of the instruction decode means is coupled to a register selection means and the second instruction code holding means, and the output of the instruction decode means to the second instruction code holding means is the second instruction A latch signal (LGRCL) for the code holding means and a set signal (RSLGR) to a predetermined value are included. The latch signal for the second instruction code holding means is generated when the instruction decoding means decodes a predetermined instruction code. The set signal to the predetermined value for the second instruction code holding means is the predetermined signal. This occurs so that the set operation is performed after the processing using the register specified by the instruction code is completed.

  The set signal to the predetermined value for the second instruction code holding means may be generated, for example, in response to the end of execution of the instruction by the instruction decoding means. Alternatively, it further includes data holding means for holding the predetermined value, and the output of the data holding means is coupled to the second instruction code holding means in response to generation of a set signal to the predetermined value. Then, the second instruction code holding means may be set to a value corresponding to the value of the data holding means.

<< Solutions to Consideration B >>
The present invention provides means for solving the examination problem B. As a means for solving the examination problem B, a combination of a plurality of instruction codes among existing transfer instructions between memory and registers and operation instructions between registers and registers, for example, using a pre-instruction code for combining them , Allowing operations on memory. In short, when a predetermined prefix instruction code is added, a plurality of instruction codes following this are interpreted as one instruction and executed. Here, one instruction may be defined such that processing is not interrupted due to factors other than reset, or interrupts (exception processing) are not accepted midway except for specific factors such as reset. it can. At this time, it is possible to use a latch means that is not released in the program, such as a temporary register in the CPU, instead of the general-purpose register or together with the general-purpose register, for direct calculation (or direct Data transfer). Here, the direct operation on the data on the memory is an operation process in which data is loaded from the memory to the data latch means not explicitly shown in the instruction code, and is performed using the data loaded on the data latch means. The direct data transfer to and from the memory is a process of loading data from the memory into data latch means not specified in the instruction code and storing the data in the data latch means in the memory.

  Specifically, following the pre-instruction code, first, when executing a memory-register transfer instruction code, it is not a general-purpose register but released in the program, such as a temporary register in the CPU. Data transfer is performed between the first latch means and the memory that are not present. Further, as a second example, when an operation instruction code between registers is continuously executed, one or a plurality of data to be calculated is read from the first latch means. Here, the latch means that is not released on the program means a latch means that cannot be specified by the user on the program, a temporary register or a buffer register that cannot be seen by the user on the CPU or microcomputer. Since such a latch means is not released in the program, it is naturally not assumed that the stored information is saved, and in many cases, it is assumed to be used for storing an intermediate result of the operation. It is assumed that the use state is finished during execution of one instruction. Therefore, under that premise, there is no need to consider evacuation when using the latch means. In order to guarantee the premise, the pre-instruction code and a predetermined instruction following the pre-instruction code are regarded as one instruction, so that an interrupt or the like is not entered midway, and the necessity of saving to the latch means is eliminated.

  When the second operation instruction code is an instruction code for requesting processing for storing the operation result in the memory, the memory address used in the transfer instruction code is another latch means such as another temporary register. (Second latch means). The operation result of the operation instruction is stored in the first latch means. Subsequently, the microcomputer itself generates a transfer instruction code between the memory and the register, the contents of the second latch means storing the address as the address, the contents of the first latch means storing the operation result as data, Write to memory.

  Further explanation will be added. If the instruction that is regarded as one instruction by the prefix instruction code performs an operation on the data on the memory and the data on the general register, and stores the result on the general register, the prefix instruction code, the memory register The transfer instruction code and the operation instruction code are executed. When the memory / register transfer instruction code is executed, the transfer data is stored in the latch means, not the general-purpose register, and the operation instruction code is stored in the latch means and the data stored in the latch means. Calculates the above data and stores the result in a general-purpose register.

  If the instruction that is regarded as one instruction by the prefix instruction code is an instruction that performs operation on the data in the general-purpose register and the data in the memory and stores the result in the memory, the prefix instruction code and the memory register transfer Execute instruction code, operation instruction code, and internally generated memory / register transfer instruction code. When executing memory / register transfer instruction code, store transfer data in latch means instead of general-purpose registers. Performs an operation on the data stored in the latch means and the data on the general-purpose register, and stores the result in the latch means. The memory / register transfer instruction code writes to the memory using the contents of the latch means storing the address as an address and the contents of the latch means storing the operation result as data. This is the same when an operation is performed on data in one memory, such as increment. In addition, when executing the memory / register transfer instruction code, in other words, during the processing by the instruction regarded as one instruction, the change of the flag reflecting the operation result is suppressed, and the operation result by the previous operation instruction is suppressed. Holds the flag state. The reason is as follows. In the execution of the operation instruction code, it is sometimes necessary to refer to the state reflected in the flag by the execution of the previous operation instruction. At this time, all the state changes of the flag are also caused by the execution of the transfer instruction or the transfer instruction code. This is because if allowed, inconvenience occurs. More specifically, there is no inconvenience caused by a change in the flag as the instruction and a change in the flag in the transfer instruction itself. Specifically, when the operation is an arithmetic operation, an overflow flag generated as a result of the arithmetic operation is prevented from being cleared by the transfer instruction code.

  When the instruction that is regarded as one instruction by the prefix instruction code is an instruction that performs an operation using two data on the memory and stores the calculation result on the memory, the prefix instruction code, first, second Memory register transfer instruction code, operation instruction code, and internally generated memory register transfer instruction code are executed. When executing the first and second memory register transfer instruction codes, transfer data is not a general-purpose register. Is stored in the latch means, and the operation instruction code calculates the data stored in the latch means and stores the result in the latch means. The memory / register transfer instruction code writes to the memory using the contents of the latch means storing the address as an address and the contents of the latch means storing the operation result as data.

  On the other hand, when the instruction that is regarded as one instruction by the prefix instruction code is an instruction that transfers data in the memory to another memory, the prefix instruction code, the memory register transfer instruction code, the memory register transfer instruction When executing the code and executing the memory / register transfer instruction code, the transfer data is stored in the latch means instead of the general-purpose register. The memory / register transfer instruction code uses the contents of the latch means storing the operation result as data. , Write to memory.

  When the instruction that is regarded as one instruction by the prefix instruction code is an operation of immediate data and data on the memory, generally, the data on the general-purpose register and the data on the memory are calculated, and the result is stored in the memory. Can be done in the same way as an

  If the instruction that is regarded as one instruction by the prefix instruction code is an instruction that transfers immediate data to the memory, the prefix instruction code, immediate register transfer instruction code, and memory register transfer instruction code are executed, and the immediate is executed. When register transfer instruction code is executed, immediate data is stored in the latch means instead of general-purpose registers, and the memory register transfer instruction code is written to the memory using the contents of the latch means storing the operation results as data. Do.

  When a plurality of instruction codes are combined and executed as a series, it is prohibited to insert an undesired process such as an interrupt between the instruction codes. The control signal for this purpose may be generated by decoding the prefix instruction code. The prefix instruction code can also have other information such as data size.

  When the memory-register transfer instruction code is executed following the prefix instruction code, the instruction code need not be exactly the same as the instruction code of the independent memory-register transfer instruction. Only the bits shown can be shared, and the other bits can be changed as appropriate.

  According to the above means, since the instruction codes such as the transfer instruction between the memory and the register and the operation instruction between the register and the register are the existing ones, the operation code alone works as before and obstructs the execution of the existing instructions. There is no. Also, if only existing instructions are used, existing software assets can be used effectively.

  The arithmetic performance can be expanded without losing the merits of existing CPUs such as general-purpose register system and load / store architecture.

  Since the prefix instruction code can be used in common regardless of the addressing mode and the content of the operation, the instruction code to be added can be minimized. Further, by providing the prefix instruction code with other information such as data size, the overall instruction code length can be shortened.

  Data read from memory to latch means, operation, and write to memory based on the contents of latch means are different from existing instructions and used registers. it can. As a result, an increase in the logical scale due to the operation on the data on the memory can be minimized.

  By making the data in the memory directly operable, the amount of data that can be directly processed can be increased, saving / restoring of general-purpose registers can be omitted, and the processing speed can be improved.

  In the case of an instruction that performs an operation on the data in the memory and the data in the general-purpose register and stores the result in the general-purpose register, since it includes a prefix instruction code, the memory register transfer instruction code and the operation instruction code are executed separately. However, since the general-purpose register is not saved or restored, the overall processing time can be improved. In addition, in the case of an instruction that performs an operation on the data on the memory and the data on the general-purpose register and stores the result in the memory, the register / memory transfer instruction code is generated internally and the instruction code is not read. By using the other latch means (second latch means), the memory address calculated at the time of reading can be reused, so that the memory register transfer instruction code, the operation instruction code, the register memory transfer instruction code The processing time can be shortened compared to the total processing time when the processes are executed individually.

  When there is a CPU with a wide address space and a CPU with a small address space while maintaining compatibility at the object level, the CPU has a wide address space, and the pre-instruction code is added to the existing transfer instruction and operation instruction. By combining these, even a CPU having a backward compatibility and a small address space can be directly operated on the data in the memory. In other words, by using the same method, while maintaining compatibility at the object level, a CPU having a wide address space and a CPU having a small address space can directly calculate data on the memory. It is possible to enjoy both the advantages of maintaining compatibility at the object level and the advantages of allowing the data on the memory to be directly operated.

  Since a new instruction function is realized by combining existing instructions, new problems are rarely caused to the existing CPU when the instruction set is further expanded and further speeded up. In other words, if there is a technique for further expanding the instruction set or further speeding up (invented) for an existing CPU, the present invention is applied to the existing CPU. The same technique can be applied to a CPU whose instruction set is expanded. The technique may be applied to each of the existing instructions used for realizing the new instruction function and combined again. The prefix instruction code has a simple operation and can be easily changed by making the operation similar to an existing instruction.

  Further, since the new instruction function is realized by combining the existing instructions, the existing CPU and the emulation interface can be shared, and the hardware of the same emulator can be used in common. By making the emulator hardware common, it is possible to quickly establish a development environment and minimize the resources required for emulator development.

<< Solutions to Consideration C >>
As a means for solving the examination subject C, [1] a plurality of data processing devices including a register configuration, a combination of an instruction and an addressing mode, or a different instruction set in which one does not include the other regarding both points. Assume a plurality of lower CPUs. At this time, an upper CPU having an instruction set including any lower CPU is configured and provided to a plurality of lower CPUs, one of which does not include the other instruction set.

  In development, an upper CPU is developed in which the configuration of general-purpose registers and the combination of instructions and addressing modes are expanded with respect to an existing CPU (one of the lower CPUs). The lower CPU has a subset configuration or instruction set of the upper CPU. The extension of the general-purpose register and the extension of the combination of the instruction and addressing mode will be described later.

  Further, the other of the lower CPUs is realized in the form of another subset of the upper CPUs.

  By providing a plurality of lower CPUs including different instruction sets as described above and appropriate upper CPUs as appropriate, the software requirements of application fields can be met, the user's various preferences can be met, Even from a CPU assembly language program, it is possible to select a CPU having a relatively close instruction set, and to facilitate the transition to a higher-level CPU.

  By preparing an upper CPU having an instruction set including all CPUs for a plurality of lower CPUs, one of which does not include the other instruction set, it is possible to effectively use software assets. However, a CPU with improved performance / function can be prepared. Effective utilization of software assets can improve the development efficiency of software development for users.

  In development, an upper CPU in which a combination of general-purpose registers or instructions and addressing modes is expanded with respect to an existing lower CPU, and another lower CPU having this subset is developed. While minimizing an increase in logical scale, it is possible to improve performance, function, usability, etc., and to facilitate the development of the other lower CPU, thereby improving development efficiency. When developing an upper CPU of the upper CPU, compatibility with the plurality of CPUs can be automatically maintained if compatibility with the upper CPU is maintained. It becomes easy to realize a CPU that improves future functions and performance while realizing effective use of assets.

  The program developed for the lower CPU becomes available to the upper CPU according to the present invention at least at the level of the source program (description level in assembly language). Here, the lower CPU refers to a CPU whose register configuration and instruction set are included in the register configuration and instruction set of a CPU such as an upper CPU according to the present invention.

  Furthermore, in order to realize upward compatibility at the object program level, an operation mode for switching the number of bits of the effective address and the unit size of the vector and the stack according to the use form of the register, for example, maximum mode and minimum mode. Should be prepared. In the minimum mode, the CPU operates in exactly the same way as at least one lower CPU. In the maximum mode, the CPU operates as an upper CPU with the maximum functions provided for it.

  [2] In order to extend the general-purpose register, as described in the means for the examination subject A, the register designation information for designating the register is divided into two parts. These two parts are arranged in different basic units on the basic unit of the instruction code. If one instruction code is omissible and the omissible instruction code is omitted, the register selection operation is performed by implicitly assuming predetermined register designation information.

  [3] In order to expand the combinations of instructions and addressing modes, as described in the means related to the examination subject B, a plurality of existing transfer instructions between memory and registers and arithmetic instructions between registers and registers are included. For example, by using a pre-instruction code for combining the instruction codes, for example, a combination of these instruction codes, an operation using the data in the memory directly is enabled. In short, when a predetermined prefix instruction code is added, a plurality of instruction codes following this are interpreted as one instruction and executed.

  [4] In order to realize a CPU with a wide address space and a reduced logical scale, a program counter having a bit length corresponding to the entire address space is provided, and for the program, the entire address space, at least most of which is linear In addition, the addressing mode of data transfer can be reduced to such an extent that relatively small data can be handled, or the data size of transfer data is limited to reduce the usable address space during data access. Such an address space is divided into two.

  According to the above, a program counter having a bit length corresponding to the entire address space is provided so that the entire address space, at least most, can be used linearly for programming, and relatively small data can be handled. By reducing the addressing mode of data transfer or limiting the data size of transfer data, the logical scale can be reduced without impairing usability in a desired application field.

  By reducing the address space that can be used during data access and dividing the address space into two, it maintains compatibility in the address space with the upper CPU without impairing usability, and the effective address is assigned to the upper CPU. Software compatibility can be maintained by preparing an operation mode for switching the calculation method and the like in advance.

  By expanding the address space for the program, suitability for programming using a high-level language such as C language can be improved. In addition, by making the stack pointer switchable, an undesired increase in the capacity of the stack during task management such as an OS can be suppressed. Even in a single-chip microcomputer or microcomputer system that operates using only a built-in memory or the like, a high-level language, an OS, or the like can be easily used, and the software development efficiency of the user can be improved.

  [5] As for the development device, a software development device for the instruction set of the upper CPU is prepared, and it can be used in common for a plurality of CPUs, one of which does not include the other instruction set. The user can select the CPU.

  On the software development device, multiple types of general-purpose registers such as assembly language having general-purpose functions are allowed.

  As for the emulator, the emulation interface of the mounted emulation processor is made common. In order to analyze the CPU, means for selecting the target CPU is provided on the emulator. In particular, the target CPU of the disassembler can be selected.

  A software development apparatus for the instruction set of the upper CPU is prepared. Further, the software development apparatus can be commonly used for a plurality of CPUs, one of which does not include the other instruction set, and the user can select the CPU. As a result, the development efficiency of the software development apparatus can be improved. For the user, even if a plurality of CPUs are used, since the software development apparatus is common, it is not necessary to generate undesired costs. The transition from one CPU of the plurality of CPUs to another CPU is facilitated, and the development efficiency can be improved.

  In addition, the emulation interface can be shared with the upper CPU and lower CPU, and by developing the logic circuit for emulation of the upper CPU, it can be used for the lower CPU, and development including the emulation processor Efficiency can be improved. In addition, the hardware of the same emulator can be shared, so that the development environment can be quickly established and the resources required for emulator development can be minimized. As the disassembler installed in the emulator is developed for the host CPU and means for selecting the target CPU on the emulator is provided, one disassembler can be practically used. It can be improved.

  [6] Organize the means described above with respect to the examination subject C from the viewpoint of compatibility, a processor for emulation, an emulator, a software development device, a data processing device such as a higher CPU, and a data processing device such as a lower CPU. Can do.

  [6-1] The data processing apparatus in terms of compatibility executes instructions according to a predetermined procedure, and includes the instruction execution function of the first other data processing apparatus, thereby including the first It is possible to execute the same instruction code as the instruction code of another microcomputer, and the same instruction code as the second other data processing apparatus by including the instruction execution function of the second other data processing apparatus The instruction code can be executed. And either or both of the operand designation and the operation designation that are not included in the instruction execution function of the first other data processing apparatus but are included in the instruction execution function of the second other data processing apparatus. On the other hand, it is not included in the instruction execution function of the first other data processing apparatus, but included in the instruction execution function of the first other data processing apparatus, and not included in the instruction execution function of the second other data processing apparatus. Instruction execution means for executing a plurality of instructions combining the above-mentioned designations with respect to either or both of the operand designation and the operation designation.

  The operand designation is, for example, designation relating to an effective address calculation, a general-purpose register, or an address space.

  If the data processing device can switch between the first operation mode and the second operation mode in which the number of bits of the effective address and the unit size of the vector and the stack are different, the effective in the first operation mode The number of bits of the correct address and the unit size of the vector and stack are the same as those of the first other data processing apparatus. The number of valid address bits and the unit size of the vector and stack in the second operation mode are the same as those of the second other data processing apparatus.

  A data processing device according to still another aspect focusing on compatibility is a data processing device that executes instructions according to a predetermined procedure, and the entire or two-divided area can be used for holding data information, and A plurality of general-purpose registers that can be used for holding address information with a number of bits larger than the number of lower-order bits divided into two. The instruction execution means can execute an instruction code having the same number of bits as the instruction code of the first different data processing apparatus having a predetermined plurality of general-purpose registers corresponding to the number of lower bits divided into two. Including the instruction execution function of the first other data processing apparatus, executing an instruction that uses the entire general register that can be divided into two, The instruction execution function of the second other data processing apparatus is included so that an instruction code having the same number of bits as the code of the instruction of the second other data processing apparatus having a smaller number than the plurality can be executed.

  According to the viewpoint of the development method of the data processing device focusing on the compatibility, the code of the undefined instruction in the first data processing device is used as the prefix instruction code, and the prefix instruction code is the first By changing the definition of the instruction code of the data processing apparatus, an instruction combining a plurality of the above specifications is defined with respect to operand specification and / or operation specification that are not defined in the first data processing apparatus. Thus, the second data processing apparatus instruction having the instruction including the instruction of the first data processing apparatus is realized. The instruction of the third data processing apparatus is realized by a part of the instruction of the second data processing apparatus.

  The prefix instruction code, for example, makes it possible to change the designation of the general-purpose register designated by the instruction code that follows. Another prefix instruction code defines an operation of data on the memory by a transfer instruction code following this and two or more instruction codes of another transfer instruction code or an operation instruction code. It is.

  [6-2] According to the viewpoint of the processor for emulation, the data processor described in terms of the compatibility and the emulation interface are included, and the first and second different ones are executed by executing instructions of the data processor. An emulation processor is configured so that the instruction execution of the data processing apparatus can be performed.

  [6-3] From the viewpoint of the emulator, an emulation program area in which the emulation processor is mounted and a control program for controlling the internal state of the emulation processor for executing the user program can be stored; And the control processor for storing the control program.

  The emulation processor can execute the instruction execution of the first and second other data processing devices in accordance with the internal setting state according to the control program.

  [6-4] According to the viewpoint of the software development apparatus (cross software), there is provided means for selecting a data processing apparatus that is a target of the program to be generated, and the data processing apparatus described in the above-mentioned compatibility viewpoint, The software development apparatus is configured to be able to generate a program for the other data processing apparatus or the second another data processing apparatus.

  [6-5] From the viewpoint of the host CPU, the data processing apparatus includes a plurality of registers capable of storing data or addresses, and operates by reading the instruction code and decoding it by the control means. The instruction code is composed of basic units, and register designation information for designating the registers can be divided and held in a plurality of instruction code basic units. The instruction set includes a transfer instruction code for performing data transfer between the memory and the register and an operation instruction code for performing an operation on the data on the register. The control means selects a register based on a decoding result of the register designation information held by the instruction code, and is omitted when a front instruction code having one divided register designation information is omitted. A register is selected by implicitly assuming predetermined register designation information instead of the designated register designation information, and the prefix instruction code, the transfer instruction code, and the operation instruction code are sequentially read and It is interpreted as one instruction, and direct operation is performed on the data in the memory.

  The direct operation on the data in the memory is, for example, an operation process in which data is loaded from the memory into data latch means not explicitly shown in the instruction code and is performed using the data loaded into the data latch means.

  A data processing device according to another aspect of the host CPU includes a plurality of registers capable of storing data or addresses, and operates by reading an instruction code and decoding it by a control means. The instruction code is composed of basic units, and register designation information for designating the registers can be divided and held in a plurality of instruction code basic units. A transfer instruction code for transferring data between the memory and the register is included in the instruction set. The control means selects a register based on a decoding result of the register designation information held by the instruction code, and is omitted when a front instruction code having one divided register designation information is omitted. Instead of register specification information, a register is selected by implicitly assuming predetermined register specification information, and a prefix instruction code, the transfer instruction code, and another transfer instruction code are read sequentially, Interpret as a single instruction, and perform direct data transfer to and from memory.

  The direct data transfer to and from the memory is, for example, a process of loading data from the memory into data latch means not specified in the instruction code and storing the data in the data latch means in the memory.

  [6-6] The data processing apparatus from the viewpoint of the lower CPU can use the program count means having the number of bits corresponding to the number of bits in the address space, and the whole or two divided areas can be used to hold the data information. A plurality of general-purpose registers that can be used for holding address information with a number of bits larger than the number of bits divided into two, and an instruction execution unit; The instruction execution means can execute an instruction that uses the entire general-purpose register to hold data information and a data transfer instruction between the general-purpose register and another storage device. The number of bits of transfer data can be made equal to or less than the number of bits divided into two of the general-purpose register, and a part of the addressing mode for designating data on the address space can be set on the address space. It is effective in a part separated into multiple parts.

  One part separated into a plurality of parts in the address space can include a vector for designating an instruction execution start address, and the other part can be mapped to an address of another storage device that can be read / written. .

<< Solution to Study Problem D >>
As a means for solving the examination problem D, an instruction for branching according to a bit state of data on a memory is divided into a plurality of fields (operation fields) for defining an operation, which are divided into basic units of an instruction code. It is realized by another word, and the word is made common to an instruction code of another instruction that can be used independently or a part of an instruction code of another instruction. The first word of the instruction code performs data transfer between the latch means which is not released in the program, such as a temporary register, and the memory. The second word branches by determining the state of the desired bit of the latch means. The latch means such as the temporary register is provided with means for determining the state of a designated bit so that the state of a predetermined bit can be determined without reading it to an ALU or the like. The first word of the instruction code prohibits the change of the condition code or the like, and prohibits the interrupt exception processing at the end time.

  The first example is a transfer instruction code (first word) for transferring data between a latch means that is not released in the program, such as a temporary register, and a memory, and a conditional branch instruction code (second word). When the conditional branch instruction is executed following the transfer instruction code, the condition is set to the bit number and the state of the bit instead of the condition code, and the bit of the data on the memory Allows branching according to the state of Furthermore, the transfer instruction code may be shared with a part of a bit test instruction or the like.

  In another aspect of the first example, a transfer instruction code for transferring data between a latch means not released in the program and a memory, such as a temporary register, common to an instruction code such as a bit test instruction, and a condition A branch instruction that branches by determining the state of a predetermined bit of data in the address space is realized by combining instruction codes of branch instructions.

  The second example is a combination of an existing instruction code for transferring between a memory and a register, a conditional branch instruction, and a pre-instruction code for combining them, and branching according to the state of the bit of data on the memory. Enable. That is, when a memory-register instruction is executed following the pre-instruction code, it is not a general-purpose register, but between a latch means such as a temporary register in the CPU that is not released in the program and the memory. Perform data transfer.

  The second example described above is common with the method of realizing an instruction using the data in the memory as described in the prior application of the present inventor, which is not yet known, and replaces the operation instruction code with a branch instruction code. Can be realized.

  Specifically, in the case of an instruction that performs an operation on the data in the memory and the data on the general-purpose register and stores the result in the general-purpose register, the prefix instruction code, the memory-register transfer instruction code, and the operation instruction code are executed. When the memory-register transfer instruction code is executed, the transfer data is stored in the latch means instead of the general-purpose register, and the operation instruction code performs an operation between the data stored in the latch means and the data on the general-purpose register, Store the result in a general-purpose register.

  In the case of an instruction that performs an operation on data in a general-purpose register and data in a memory and stores the result in the memory, a prefix instruction code, a memory-register transfer instruction code, an operation instruction code, and an internally generated memory The register transfer instruction code is executed, and when the memory-register transfer instruction code is executed, the transfer data is stored in the latch means instead of the general-purpose register. The operation instruction code performs an operation on the data stored in the latch means and the data on the general-purpose register, and stores the operation result in the latch means. The memory-register transfer instruction code writes to the memory using the contents of the latch means storing the address as an address and the contents of the latch means storing the operation result as data. This is the same when an operation is performed on data in one memory, such as increment. Further, when the memory-register transfer instruction code is executed, the change of the flag is suppressed and the change of the flag of the operation result is held.

  In the case of an instruction that performs an operation on data in two memories and stores the result in the memory, a prefix instruction code, first and second memory / register transfer instruction code, an operation instruction code, and an internal The generated memory / register transfer instruction code is executed, and when the first and second memory / register transfer instruction codes are executed, the transfer data is stored in the latch means instead of the general-purpose register. The operation instruction code calculates the data stored in the latch means and stores the result in the latch means. The memory / register transfer instruction code writes to the memory using the contents of the latch means storing the address as an address and the contents of the latch means storing the operation result as data.

  On the other hand, in the case of an instruction that transfers data in the memory to another memory, the pre-instruction code, the memory / register transfer instruction code, and the memory / register transfer instruction code are executed, and the memory / register transfer instruction is executed. When the code is executed, the transfer data is stored in the latch means instead of the general-purpose register, and the memory / register transfer instruction code writes the contents of the latch means storing the calculation result to the memory as data.

  In the case of the calculation of immediate data and data on the memory, the calculation can be performed in the same manner as an instruction for performing calculation on data on the general-purpose register and data on the memory and storing the result in the memory.

  In the case of an instruction that transfers immediate data to the memory, the prefix instruction code, the immediate register-to-register transfer instruction code, and the memory-to-register transfer instruction code are executed. Immediate data, not a register, is stored in the latch means, and the memory / register transfer instruction code writes data to the memory using the contents of the latch means storing the operation result as data.

  According to the above-mentioned means, since the instruction codes such as the first word and the second word (conditional branch instruction) are already existing, they can operate in the same manner as before and inhibit the execution of existing instructions. Absent. Also, if only existing instructions are used, existing software assets can be used effectively. The advantages of existing CPUs such as general-purpose registers and load / store architecture are not impaired. If the first word and the second word (conditional branch instruction) have a plurality of types in the bit length of the absolute address, the bit length of the displacement, etc., these can be combined by the same method. By making these combinations possible, program restrictions can be eliminated and usability can be improved. Moreover, it becomes possible to combine with a subroutine branch instruction by the same method, and usability can be improved.

  A latch means such as a temporary register is provided with means for judging the state of a designated bit, and by making it possible to judge the state of a predetermined bit without reading it to an ALU or the like, the conditional branch instruction Since it can be realized without changing the overall operation, the portion to be changed can be reduced, and the increase in logical scale can be minimized.

  Since the prefix instruction code can be used in common regardless of the addressing mode and the content of the operation, the instruction code to be added can be minimized. Further, by providing the prefix instruction code with other information such as data size, the overall instruction code length can be shortened.

  Data read from memory to latch means, operation, and write to memory based on the contents of latch means are different from existing instructions and used registers. it can. As a result, an increase in the logical scale due to the operation on the data on the memory can be minimized.

  When there is a CPU having a wide address space and a CPU having a small address space while maintaining compatibility at the object level, the address space having a backward compatibility is realized by realizing the instruction with a CPU having a wide address space. Even with a small CPU, data on the memory can be calculated. In other words, by using the same method, it is possible to calculate data on the memory even with a CPU having a wide address space and a CPU having a small address space while maintaining compatibility at the object level. It is possible to enjoy both the advantages of maintaining compatibility at the object level and the advantages of enabling computation of data on the memory.

  Since a new instruction function is realized by combining existing instructions, new problems are rarely caused to the existing CPU when the instruction set is further expanded and further speeded up. In other words, if there is a technique for further expanding the instruction set and further speeding up the existing CPU or newly developed, the present invention is applied to the existing CPU. However, the same technique can be applied to a CPU whose instruction set is expanded. The technique may be applied to each of the existing instructions used for realizing the new instruction function and combined again. The prefix instruction code has a simple operation and can be easily changed by making the operation similar to an existing instruction.

  In addition, since the new instruction function is realized by combining the existing instructions, the existing CPU and the emulation interface can be shared, and the hardware of the same emulator can be shared. By making the emulator hardware common, the development environment can be quickly established, and the resources required for emulator development can be minimized.

  To summarize the above-mentioned examination subjects B and D, a transfer instruction code for reading a prefix code and data, and an instruction code for specifying processing (transfer instruction code: in case of transfer between memories, operation instruction code: in case of calculation between memories) , Branch instruction code: bit condition branch instruction) to define a new instruction code. If you already have an instruction code (read from memory to a temporary register and generation of a control signal) that combines a prefix code and a transfer instruction code that reads data, combine this with an instruction code that specifies processing, It defines a new instruction code.

<< Solutions for Study Problem E >>
As a means for solving the examination subject E, [1] the data processing device fixes a combination of a plurality of general-purpose registers that can be specified to a control unit that controls an execution unit that executes an instruction, and the combination is fixed The instruction set includes a transfer instruction for transferring data between the general-purpose register and the address in the address space. As a result, even data larger than the bit length of a general-purpose register can be handled easily, improving usability, and reducing the frequency of instruction reads for data read / write, and data processing Can be speeded up.

  The effective address of the above transfer instruction is calculated only once by the address calculator, and the address buffer has an increment or decrement function and a function to hold the increment result, thereby simplifying the instruction operation and controlling the existing transfer instruction. And an increase in the logical scale of an instruction decoder or the like can be minimized. Further, it can be used in common for various addressing modes.

  [2] When the general-purpose register can be divided and there is a functional difference between the divided parts, a transfer instruction that uses the entire general-purpose register and a transfer instruction that uses the divided part may be provided. . As a result, data can be transferred to a general-purpose register that is easy to use in data processing, so that processing can be facilitated and speeded up.

  [3] When the number of execution states such as operation instructions for a general-purpose register is different for each general-purpose register, a transfer instruction between a plurality of general-purpose registers in a predetermined combination and another general-purpose register is provided. Good. At this time, the number of general-purpose registers is increased, the register designation field for designating the general-purpose register is divided into two parts, these two parts are arranged in different words on the basic unit of the instruction code, and one word is assigned. If the omissible word is omitted and the omissible word is omitted, predetermined register designation information may be implicitly designated. An optional word has only a part of the register specification field and does not specify the type of operation. Means for holding a register designation field included in an optional word is provided, and when the optional word is executed, the register designation field included in the optional word is stored in the holding means. Further, at the end of execution of the instruction, the holding means is set to a predetermined value corresponding to the implicit designation. A non-omissible word may be shared with an existing CPU, and an omissible word may be assigned to an undefined word of the existing CPU.

  If only the general-purpose register that can be specified implicitly (for example, the general-purpose register of the existing lower CPU) is used, the omissible word can be omitted, so that the instruction code is not increased (at least the conventional equivalent general-purpose register) When using, an equivalent instruction code may be used). By not increasing the instruction code, the processing speed is not reduced.

  By adding the omissible word, all general purpose registers can be directly selected by an instruction, so that there are few parts that impair the ease of programming. In addition, by securing a part of an arbitrary amount of general-purpose registers for each desired task or desired interrupt processing (not used in other tasks or processing), the general-purpose registers can be set in the task or interrupt processing. There is no need to evacuate and speed up can be achieved. In addition, since the number of general-purpose registers reserved for the task and interrupt processing can be arbitrarily set, it is easy to interchange the general-purpose registers to be used between tasks and processing.

  By adding the word, the access to the general-purpose register that can be specified can generally be made faster than the access to the memory such as the RAM. Therefore, the number of general-purpose registers is increased and the transfer between the plurality of general-purpose registers and the memory is performed at high speed. By making it executable, the processing speed of the CPU can be improved. For processors that have a so-called load store type instruction set and cannot directly operate on the memory contents, the amount of data that can be directly processed can be increased, and the memory access speed can be increased. Speed can be improved.

  [4] When there is a CPU having a wide address space and a CPU having a small address space while maintaining compatibility at the object level, the transfer instruction for the general-purpose register corresponding to the address space in the CPU having a wide address space; And the transfer instruction for a general-purpose register having a size (for example, 16 bits) corresponding to the address space of the CPU having a small address space.

  When there is a CPU with a wide address space and a CPU with a small address space while maintaining compatibility at the object level, the above-described general-purpose register having a size (for example, 32 bits) corresponding to the address space in a CPU with a wide address space. By providing the transfer instruction and the transfer instruction for a general-purpose register having a size (for example, 16 bits) corresponding to the address space of the CPU having a small address space, the latter transfer instruction can be converted into an address having backward compatibility. Even a CPU with a small space can be easily realized. In other words, by using the same method, it is possible to realize a transfer instruction for a plurality of general-purpose registers even with a CPU having a large address space and a CPU having a small address space while maintaining compatibility at the object level. Both the advantage of maintaining compatibility at the object level and the advantage of adding the transfer instruction can be enjoyed.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the solution related to the examination problem B, it is possible to minimize the increase in logical and physical scale, and maintain compatibility with an existing CPU or microcomputer having a load / store type instruction set. In addition, it is possible to perform a direct operation on the data on the memory.

  Furthermore, apparently by allowing operations on data in the memory, programming can be facilitated and undesired general-purpose registers can be prevented from being saved / restored to improve the CPU processing performance.

<< Embodiment relating to means for solving examination problems A to C >>
First, a specific example of the invention relating to the means for solving the examination problems A to C will be described. FIG. 2 shows a single chip microcomputer which is an example of a data processing apparatus according to the present invention.

  A single-chip microcomputer 1 shown in FIG. 1 includes a CPU 2 that controls the entire system, an interrupt controller (INT) 3, a ROM 4 that is a memory for storing processing programs of the CPU 2, a work area of the CPU 2, and temporary storage of data. RAM 5, timer [A] 6, timer [B] 7, serial communication interface (SCI) 8, A / D converter 9, first to ninth input / output ports (IOP [1] to IOP) [9]) It is composed of functional blocks or modules of 11 to 19, a clock generator (CPG) 20, a system controller (SYSC) 21, and a DMAC (direct memory access controller) 33. It is formed on one such semiconductor substrate. The CPUCR 22 is a control register disposed in the system controller 21.

  The CPU 2 mainly fetches instructions from the ROM 4 and decodes them to perform arithmetic operations and control operations. The DMAC 33 shares the bus 30 with the CPU 2 and can perform data transfer control on behalf of the CPU 2 in accordance with the data transfer control conditions set by the CPU 2. DREQ is a data transfer request signal given to the DMAC 33 from the outside of the microcomputer 1. When the DMAC 33 accepts a data transfer request based on the data transfer request signal DREQ, the DMAC 33 returns a data transfer request acknowledge signal DACK to the request source.

  The single-chip microcomputer 1 has input terminals for ground level (Vss), power supply voltage level (Vcc), analog ground level (AVss), analog power supply voltage level (AVcc), and analog reference voltage (Vref) as power supply terminals. Have. As dedicated control terminals, there are terminals for reset (RES), standby (STBY), mode control (MD0, MD1, MD2), clock input (EXTAL, XTAL), and the like.

  The single chip microcomputer 1 operates in synchronization with a reference clock (system clock) generated based on a crystal oscillator connected to the terminals EXTAL and XTAL of the CPG 20 or an external clock input to the EXTAL terminal. . One cycle of this reference clock is called a state.

  The functional blocks of the single chip microcomputer 1 are connected to each other by an internal bus 30. The single chip microcomputer 1 includes a bus controller (not shown) that controls the bus. The internal bus 30 may include a control bus such as a read signal and a write signal in addition to the internal address bus and internal data bus, and the control bus may further include a bus size signal or a bus command in which these are encoded. Alternatively, a system clock or the like may be included.

  Although not specifically shown, there are two types of internal address buses, IAB and PAB, depending on the phase, and the internal data bus also has IDBs and PDBs depending on the phase. For example, in the case of a read, after IAB, the PAB is delayed by 0.5 state. PAB and PDB are synchronized. After the PDB, the IDB is delayed by 0.5 states. The bus controller performs the interface between IAB and PAB and IDB and PDB.

  Such functional blocks and modules are read / written by the CPU 2 via the internal bus 30. The data bus width of the internal bus 30 is 16 bits. The CPU 2 can read / write the built-in ROM 4 and RAM 5 in one state.

  The control registers of timer [A] 6, timer [B] 7, SCI 8, A / D converter 9, IOP [1] 11 to IOP [9] 19, and CPG 20 are collectively referred to as internal I / O. It is called a register.

  Each of the input / output ports 11 to 19 is also used as an address bus, data bus, bus control signal, or input / output terminals of the timers 6 and 7, the SCI 8, and the A / D converter 9. That is, the timers 6 and 7, the SCI 8, and the A / D converter 9 each have an input signal, and are input / output from / to the outside via a terminal also used as an input / output port. For example, IOP [5], IOP [6], and IOP [7] are also used as input / output terminals of timers 6 and 7, and IOP [8] is also used as an input / output terminal of SCI8. The analog data input terminal is also used as IOP [9].

  When the reset signal RES is given to the single chip microcomputer 1, the single chip microcomputer 1 including the CPU 2 is reset. When the reset is released, the CPU 2 reads a start address from a predetermined address, and performs a reset exception process that starts reading an instruction from the start address. Thereafter, the CPU 2 sequentially reads and decodes instructions from the ROM 4 and the like, and processes data or transfers data to the RAM 5 and the timers 6 and 7 based on the decoded contents. That is, the CPU 2 refers to data input from the input / output ports 11 to 19 or the like, or an instruction input from the SCI 8 or the like, and performs processing based on a command stored in the ROM 4 or the like. Based on the input / output ports 11 to 19, timers 6 and 7, etc., signals are output to the outside to control various externally connected devices.

  The states of the timers 6 and 7, the SCI 8, and external signals can be transmitted to the CPU 2 as interrupt signals. The interrupt signal is output from the A / D converter 9, the timer [A] 6, the timer [B] 7, the SCI 8, and the input / output ports 11 to 19, and the interrupt controller 3 inputs the interrupt signal to a predetermined register. An interrupt request signal 31 is given to the CPU 2 based on the designation of. When an interrupt factor occurs, a CPU interrupt request is generated, and the CPU 2 interrupts the processing being executed, goes through an exception processing state, branches to a predetermined processing routine, performs a desired process, and sets the interrupt factor. Or clear it. At the end of the predetermined processing routine, a normal return instruction is executed, and the interrupted process is resumed by executing this instruction.

  FIG. 3 shows a programming model of the host CPU 2 as a configuration example (programming model) of the general-purpose registers and control registers of the CPU 2 to which the present invention is applied.

  The CPU 2 has 32 general-purpose registers having a 32-bit length. The general-purpose registers ER0 to ER31 all have the same function, and can be used as an address register or a data register.

  As a data register, it can be used as a 32-bit (long word), 16-bit (word), and 8-bit (byte) register. The address register and the 32-bit register are used as general registers ER (ER0 to ER31) at once. As 16-bit registers, the general-purpose register ER is divided and used as general-purpose registers E (E0 to E31) and general-purpose registers R (R0 to R31). These have equivalent functions, and up to 64 16-bit registers can be used. As an 8-bit register, the general-purpose register R is divided and used as general-purpose registers RH (R0H to R31H) and general-purpose registers RL (R0L to R31L). These have equivalent functions, and up to 64 8-bit registers can be used. The usage method can be selected independently for each register.

  The general-purpose registers ER7, ER15, ER23, and ER31 are assigned a function as a stack pointer (SP) in addition to a function as a general-purpose register, and are used implicitly in exception processing, subroutine branching, and the like. Exception handling includes the interrupt handling. A stack pointer for subroutine branching and a stack pointer for exception handling can be independently selected by setting a control register (not shown).

  In terms of the internal logical configuration, ER0 to ER7 are group 0, ER8 to ER15 are group 1, ER16 to ER23 are group 2, and ER24 to ER31 are group 3. Group 0 is the same as the existing CPU (lower CPU).

  These general-purpose registers can be used equally without any difference in programming specifications. At least, when writing in assembly language, it can be described as, for example, R0H, E8, R16, ER31, etc. without regard to the group. For example, if written according to the assembler format of “H8S / 2600 Series H8S / 2000 Series Programming Manual” published by Hitachi, Ltd. in March 1995, “MOV.L ER0, ER31” or “ADD.W E8, R16” And can be described only by register numbers.

  In FIG. 3, what is indicated by PC is a 24-bit counter (program counter), which indicates the address of an instruction to be executed next by the CPU 2. Although not particularly limited, since all instructions of the CPU 2 are in units of 2 bytes (words), the least significant bit is invalid, and the least significant bit is regarded as 0 when the instruction is read.

  What is indicated by CCR is an 8-bit register (condition code register) indicating the internal state of the CPU 2. It consists of 8 bits including interrupt mask bit (I) and half carry (H), negative (N), zero (Z), overflow (V) and carry (C) flags.

  What is indicated by EXR is an 8-bit register that controls exception processing such as interrupts. It includes interrupt mask bits (I2 to I0) and trace (T).

  Examples of data structure on general-purpose registers, data structure on memory space, addressing mode and effective address calculation method, etc. "H8S / 2600 Series H8S / 2000 Series Programming Manual" published by Hitachi, Ltd. Similar to the described CPU, an address space of 16 MB (or data 4 GB) can be used. Maximum mode / minimum mode (advanced / normal mode in the description of “H8S / 2600 series H8S / 2000 series programming manual” published by Hitachi, Ltd. in March 1995), address space of 64 kbytes / 16 M respectively. Byte (or data 4G bytes) can be selected.

  FIG. 4 shows a first backward compatible CPU programming model for CPU2. The programming model shown in the figure is the same as the CPU described in “H8 / 300 Series Programming Manual” issued by Hitachi, Ltd. in July 1989.

  The first backward compatible CPU has eight 16-bit general purpose registers. All general purpose registers have the same function and can be used as both address registers and data registers.

  As a data register, it can be used as a 16-bit and 8-bit register. The address register and 16-bit register are used as general-purpose registers R (R0 to R7) at once. As an 8-bit register, the general-purpose register R is divided and used as general-purpose registers RH (R0H to R7H) and general-purpose registers RL (R0L to R7L). These have equivalent functions, and up to 16 8-bit registers can be used. The usage method can be selected independently for each register.

  As described above, the general-purpose register R7 is assigned a function as a stack pointer (SP) in addition to a function as a general-purpose register, and is used implicitly in exception processing, subroutine branching, and the like.

  As an address space, a 64-kbyte address space can be used, and the vector and stack structure are equivalent to the minimum mode of the host CPU.

  The upper CPU 2 having the programming model of FIG. 3 includes the general purpose registers and instruction set of the first backward compatible CPU of FIG. That is, in order to keep the upper CPU 2 compatible with the first lower CPU, as will be described in detail later, expansion of general-purpose registers and expansion of combinations of instruction sets and addressing modes are performed.

  FIG. 5 shows a second backward compatible CPU programming model for CPU2.

  The upper CPU 2 having the programming model of FIG. 3 includes the general purpose registers and instruction set of the second backward compatible (lower compatibility is also simply referred to as lower) CPU of FIG. That is, in order to keep the upper CPU 2 compatible with the first lower CPU, as will be described in detail later, expansion of general-purpose registers and expansion of combinations of instruction sets and addressing modes are performed. On the other hand, with respect to the first lower CPU in FIG. 4, the second lower CPU in FIG. 5 has a relationship of including or not including general-purpose registers and instruction sets. For example, the second lower CPU in FIG. 5 has a larger general register bit length than the first lower CPU in FIG. 4, and the first lower CPU in FIG. The lower CPU has a large number of general purpose registers.

  The second backward compatible CPU has four general-purpose registers having a 32-bit length. All general purpose registers have the same function and can be used as both address registers and data registers.

  As a data register, it can be used as a 32-bit, 16-bit and 8-bit register. As an address register and a 32-bit register, they are collectively used as general purpose registers ER (ER0, ER1, ER7, ER15). As a 16-bit register, the general-purpose register ER is divided and used as general-purpose registers E (E0, E1, E7, E15) and general-purpose registers R (R0, R1, R7, R15). These have equivalent functions, and up to eight 16-bit registers can be used. As an 8-bit register, the general-purpose register R is divided and used as a general-purpose register RH (R0H, R1H, R7H, R15H) and a general-purpose register RL (R0L, R1L, R7L, R15L). These have equivalent functions, and up to eight 8-bit registers can be used. The usage method can be selected independently for each register.

  The general-purpose registers ER7 and ER15 are assigned a function as a stack pointer (SP) in addition to a function as a general-purpose register, and are used implicitly in exception processing, subroutine branching, and the like. In the same manner as described above, the stack pointer for subroutine branching and the stack pointer for exception handling can be independently selected by setting a control register (not shown).

  The bit length of the general-purpose register is the same as that of the upper CPU 2, and an equivalent address space of 16 Mbytes (or data 4 Gbytes) can be used. The second lower CPU has only a mode corresponding to the maximum mode.

  In the program, ER0, R0, R0H, R0L, ER1, R1, R1H, and R1L can be described as EAX, AX, AH, AL, EBX, BX, BH, and BL, respectively. These do not indicate the function of the general-purpose register, but are adapted to the description of another CPU that is not related to the present invention. For this reason, only the description as it is is used for E0 and E1 which cannot be used independently by the further CPU. In this case, for example, “ADD.W E1, BX” and “ADD.W E1, R1” correspond to the same instruction code.

  FIG. 6 shows the address space of the CPU. As the address map of the single chip microcomputer, ROM is arranged from address 0, while RAM and internal I / O registers are arranged at both ends of the address space from address H'FFFF or address H'FFFFFF. Like that.

  As described above, the host CPU 2 has a 16 MB address space maximum mode and a 64 kB address space minimum mode. The selection of the maximum mode / minimum mode is determined by the state of the mode selection signals MD0 to MD2.

  In the maximum mode, the absolute space is 24 bits (8 reserved bits are added at the top, 32 bits in the instruction code), and the entire space is represented by 0 to H'7FFF and H'FF8000 to H 'with 16 bits of absolute address. Specify FFFFFF.

  In addition, the vector for exception processing is 24 bits (32 bits on the memory and the upper 8 bits are ignored), and the PC saved / restored in a subroutine branch is also 24 bits.

  In the minimum mode, both the absolute address and the register indirect addressing mode use only the lower 16 bits and ignore the upper bits. The vector for exception processing is 16 bits, and the PC saved / restored in a subroutine branch is also 16 bits.

  The first lower CPU has an address space of 64 kB corresponding to the minimum mode. An absolute address has only 16 bits, and in the register indirect, a 16-bit register designates the entire space. The vector for exception processing is 16 bits, and the PC saved / restored in a subroutine branch is also 16 bits.

  The second lower CPU has a 16 MB address space corresponding to the maximum mode. The absolute address has only 16 bits and designates 0-H'7FFF and H'FF8000-H'FFFFFF. On the other hand, in the register indirect, the entire space is specified by a 32-bit register. When the absolute address is 16 bits, the RAM and internal I / O registers can be specified up to 32 kB, and the ROM can be specified up to 32 kB. The capacity of 32 kB including the built-in RAM and the internal I / O register can be said to be sufficient for this single-chip microcomputer in an application field where the bus is not expanded. Also, if the combined RAM and internal I / O registers exceed 32 kB, the logical and physical scale of the built-in RAM itself increases, so there is little need to use a lower CPU with a small logical scale. It can be said that it is appropriate to use an upper CPU. At least use the second lower CPU to provide RAM or internal I / O registers that cannot be specified by absolute addresses, and pursue the reduction of the logical and physical scale, or use the upper CPU to The space can be specified by an absolute address, and it is possible to select whether to pursue usability.

  Although the ROM addresses that can be specified by the absolute address of 16 bits are limited, constants assigned to the ROM can be rearranged by inter-module optimization even when they are described by a C compiler or the like. The inter-module optimization performs optimization depending on the memory allocation and the function calling relationship when linking each program module, and is issued by Hitachi, Ltd. in August 1997, “H8S, H8”. / 300 Series C Compiler User's Manual (4th edition).

  The vector for exception processing is 24 bits (32 bits on the memory and the upper 8 bits are ignored), and the PC saved / restored at a subroutine branch is also 24 bits.

  7 and 8 illustrate the effective address calculation method in the maximum mode of the host CPU 2 as the effective address calculation method.

  The register indirect shown in (1) of FIG. 7 includes a part for designating a register in the instruction code, and designates an address on the memory by using a total of 32 bits of the contents of the general-purpose register ER designated by the instruction code as an address. . Since the address may be 24 bits, the upper 8 bits are ignored.

  In the register indirect with displacement shown in (2) and (3) of FIG. 7, the result obtained by adding the displacement included in the instruction code to the 32-bit address obtained in the same manner as the register indirect is used as the address. Specify an address in memory. The addition result is used only for address designation and is not reflected in the contents of the general-purpose register ER. Although there is no particular limitation, the displacement is 32 bits or 16 bits, and when the 16-bit displacement is added, the upper 16 bits are sign-extended. That is, the addition is performed on the assumption that the upper 16 bits of the displacement have the same value as bit 15 of the 16-bit displacement. In this case, the upper 8 bits of the 32-bit displacement are reserved and ignored.

  The post-increment register indirect shown in (4) of FIG. 7 designates an address on the memory with a 32-bit address obtained in the same manner as the register indirect. Thereafter, 1 or 2 or 4 is added to this address, and the addition result is stored in the general-purpose register ER. 1 is designated when byte data on the memory is designated, 2 is designated when word data is designated, and 4 is designated when address data is designated. The upper 8 bits of the addition result are also stored in the extension register.

  In the pre-decrement register indirect shown in (5) of FIG. 7, the address on the memory is designated by a 24-bit address obtained by subtracting 1 or 2 or 4 from the 32-bit address obtained in the same manner as the register indirect. To do. Thereafter, the subtraction result is stored in the general-purpose register ER. 1 is designated when byte data on the memory is designated, 2 is designated when word data is designated, and 4 is designated when address data is designated. Similarly to the above, when the address may be 24 bits, the upper 8 bits of the subtraction result are also stored in the extension register, although there is no particular limitation.

  The absolute addresses shown in (6), (7), and (8) of FIG. 8 designate an address on the memory by using an 8-bit, 16-bit, or 24-bit absolute address included in the instruction code as an address. The upper 16 bits of the 8-bit absolute address are extended by one. That is, bits 23 to 8 of the address are all 1 bits. Therefore, usable addresses are 256 bytes of H'FFFF00 to H'FFFFFF. In the 16-bit absolute address, the upper 8 bits are sign-extended. That is, if bit 15 of the 16-bit absolute address is 0, bits 23 to 16 of the address are all 0s, and if bit 15 is 1, bits 23 to 16 of the address are all 1s. Accordingly, usable addresses are 64 kbytes of H'000000 to H'007FFF and H'FF8000 to H'FFFFFF.

  In the program counter relative shown in (9) and (10) of FIG. 8, the address on the memory is designated by using the result of adding the displacement included in the instruction code to the 24-bit address of the contents of the program counter. . The addition result is stored in the program counter. Although there is no particular limitation, the displacement is 16 bits or 8 bits, and when these displacements are added, the upper 8 bits or 16 bits are sign-extended. That is, the addition is performed assuming that the upper 8 bits of the displacement are the same as the bit 15 of the 16-bit displacement, or the upper 16 bits are the same as the bit 7 of the 8-bit displacement. Program counter relative is used only for branch instructions.

  In the minimum mode, the upper 8 bits of the effective address are ignored. In addition to the above, addressing modes such as immediate, register direct, and memory indirect are executed, but since these are not directly related to the present invention, detailed description thereof is omitted.

  In the data transfer instruction of the first lower CPU, register indirect, register indirect with 16-bit displacement, post-increment / pre-decrement register indirect, and 8 / 16-bit absolute address can be used. The calculation method of the effective address is the same as that of the upper CPU 2, but the upper 8 bits are ignored and the lower 16 bits are valid.

  In the data transfer instruction of the second lower CPU, register indirect, register indirect with 16-bit displacement, post-increment / pre-decrement register indirect, and 8 / 16-bit absolute address can be used. The 24-bit absolute address can be used in a branch instruction.

  FIG. 9 illustrates a machine language instruction format of the CPU 2 according to the present invention. The instruction set of the first lower CPU and the second lower CPU is a subset of the instruction set of the upper CPU 2.

  The instruction of the CPU 2 is in units of 2 bytes (word). Each instruction includes an operation feed (op), a register field (r, gr), an EA extension (EA), and a condition field (cc). Although not particularly limited, the instruction format is the same as the CPU described in “H8S / 2600 Series H8S / 2000 Series Programming Manual” published by Hitachi, Ltd. in March 1995.

  The operation field (op) represents the function of the instruction, and specifies the processing contents of the specified operand in the addressing mode. Always include the first 4 bits of the instruction. There may be two operation fields.

  The register fields (r, gr) specify general purpose registers. The register field (r) is 3 bits for the address register and 3 bits (32 bit register) or 4 bits (8 or 16 bit register) for the data register. There may be two register fields or no register fields.

  The register field (gr) holds information specifying which register set of group 0 to group 3 is selected. The register field (gr) has 4 bits, but according to the register configuration of FIG. 3, the lower 2 bits are validated although not particularly limited. The word including the register field (gr) can be omitted. If omitted, it is assumed that 0 is given, and it is considered that the register set of group 0 is specified, and the register field (r) The registers specified by are assigned register numbers 0 to 7, and general-purpose registers ER0 to ER7 can be selected.

  For example, it is obtained by register number n = gr [1: 0] << 3 + r [2: 0] (<< 3 indicates a 3-bit left shift). That is, a register having a number designated by 5 bits is designated, with gr being the higher order and the lower 3 bits r [2: 0] of r being the lower order. For example, when gr = 0 and r = 1, the register number n = 1, and when gr = 2 and r = 3, the register number n = 19. The register E, the register R, the register RH, and the register RL are designated by the portion that designates the size of the instruction code of the general-purpose register ERn corresponding to the register number n and the contents of r [3]. For example, whether the data size is a long word, a word, or a byte is specified by a predetermined bit in the operation field of the instruction code. When the data size is word or byte, the register position to be used is specified by r [3]. r [3] means bit data of the fourth bit from the lower order of r. When the data size is word, the register E is designated when r [3] = 1, and the register R is designated when r [3] = 0. When the data size is byte, r [3] = 1 designates the register RL, and when r [3] = 0, the register RH is designated.

  In addition, gr1 and r1 mean a register designation field of a source register or an address register, and gr2 and r2 mean a register designation field of a destination register or a data register. gr1 (bits 7 to 4 in the basic word of the instruction code) is replaced with r1 (bits 7 to 4 or 6 to 4 in the basic word of the instruction code) and gr2 (bits 3 to 0 in the basic word of the instruction code) Corresponds to r2 (bits 11 to 8 or bits 3 to 0 in the basic word of the instruction code).

  The EA extension unit (EA) specifies immediate data, an absolute address, or a displacement. It is 8 bits, 16 bits, or 32 bits.

  The condition field (cc) specifies the branch condition of the conditional branch instruction (Bcc instruction).

  FIG. 9 shows a machine language instruction format of the CPU 2. If a prefix instruction code (register extension prefix instruction code) having a register field (gr) is omitted, an existing instruction code is obtained. The register field (gr) is also referred to as a group designation field (gr). For example, when the instruction code “H′0901” exemplified in (2) of FIG. W R0 and R1, and as illustrated in (3) of FIG. 9, when a prefix instruction code “H'0012” having a group designation field is added thereto, the instruction code “H′00120901” is added to ADD. W R8, R17.

  The prefix instruction record “H′0000” that specifies the register set of group 0 that is used implicitly is not particularly limited, but is a NOP (no operation) instruction. The instruction code “H'00xx” (xx is 01 to FF) designates a group of register sets and executes the next consecutive instruction code (inhibits interrupts), as in the case of the NOP instruction. It is incremented and executed with the minimum number of states.

  Since the group designation field (gr) has 4 bits, the general-purpose register group can be logically expanded to 16. In this case, 128 32-bit general registers (or 256 16-bit general registers) can be used.

  There may be a plurality of operation fields corresponding to the group designation field (gr). For example, an operation code having both a function for simply specifying a register and a function for switching other functions (such as data size) may be prepared.

  The first lower CPU and the second lower CPU have a subset of the instruction code of the upper CPU 2. Specifically, the first lower CPU does not have a register designation field (gr). The second lower CPU uses the register designation field (gr) only when designating the stack pointer ER15.

  FIG. 10 illustrates a detailed instruction format of a transfer instruction for the memory of the CPU 2.

  Here, register indirect, post-increment / pre-decrement register indirect, register indirect with 16-bit displacement, and 16-bit absolute address are shown. Although other addressing modes are also provided, detailed description thereof is omitted.

  Register indirect (@ERn) designates an operand on the memory with the contents of the address register (ERn) designated in the register field (r) of the instruction code as an address.

  The register indirect with displacement (@ (d: 16, ERn)) is a 16-bit displacement (d) included in the instruction code in the contents of the address register (ERn) specified by the register field (r) of the instruction code. The operand in the memory is specified using the content of the addition as an address. Upon addition, the 16-bit displacement is sign extended.

  The post-increment register indirect (@ ERn +) designates an operand on the memory with the contents of the address register (ERn) designated in the register field of the instruction code as an address. Thereafter, 1, 2 or 4 is added to the contents of the address register, and the addition result is stored in the address register. 1 is added for the bisize, 2 for the word size, and 4 for the longword size.

  In the pre-decrement register indirect (@ -ERn), an operand on the memory is designated with the contents obtained by subtracting 1, 2 or 4 from the contents of the address register (ERn) designated in the register field of the instruction code. Thereafter, the subtraction result is stored in the address register. 1 is subtracted for the byte size, 2 for the word size, and 4 for the longword size.

  The absolute address (@aa: 16) is an absolute address (aa) included in the instruction code and designates an operand on the memory. Although not particularly limited, in the case of a 16-bit absolute address, the upper 16 bits are sign-extended. In this case, bits 8 to 10 are fields for specifying an addressing mode.

  FIG. 11 to FIG. 14 illustrate combinations of instruction codes in the instruction format of direct operation instructions for the memory by the upper CPU 2. The direct arithmetic instruction for the memory is an arithmetic instruction extended with respect to the existing instruction set. The instruction format shown in the figure is a format of an instruction to be processed as one instruction to which a prefix instruction code for instruction extension is added and a transfer instruction code, an operation instruction code, and the like are added. Although not shown, the first lower CPU and the second lower CPU have an instruction set that is a subset of the instruction set of the upper CPU 2.

  The direct operation instruction for the memory is composed of a combination of a control code (instruction extension instruction code), an EA1 code, an EA2 code, and an operation code.

  EA1 and EA2 are made the same as the instruction code of the transfer instruction in each addressing mode shown in FIG. The transfer direction is the read direction, and the unused register field (r2) is set to 0, although not particularly limited.

  The operation code is the same as the instruction code of the operation instruction between the general-purpose registers. The combination of the EA1 code, the EA2 code, and the operation code can be arbitrarily set as long as it has meaning. That is, the necessary EA1 code, EA2 code, and operation code are combined in accordance with the contents of desired processing.

  For example, only the destination side data is necessary for the increment processing and the like, and therefore the EA1 code for reading the source side data is not necessary. Therefore, the format of the increment process is configured by combining the prefix instruction code, the EA2 code, and the operation code.

  For the addition processing or the like, it is only necessary to combine EA1 and EA2 on the source side and the destination side that use the memory. When only the source side is data on the memory (for example, ADD.W @ ER1, R0), the instruction extension prefix instruction code and EA1 code (same as MOV.W @ ER1, Rx. Rx has meaning) As described above, R0) is combined with an operation code (same as ADD.W Rx, R0). When only the destination side is data on the memory (ADD.WR1, @ ER0), the instruction extension prefix instruction code, the EA2 code, and the operation code are combined. When both the source side and the destination side are data on the memory (ADD.W @ ER1, @ ER0), as shown in FIG. 11, the instruction code for instruction expansion, EA1, EA2 code, Combine operation codes. Note that when both the source side and the destination side are data on general-purpose registers (ADD.WR1, R0), they are existing instructions and only an operation code is required. In other words, no prefix instruction code is required.

  The operation of the immediate data and the data on the memory (for example, ADD.W #xx, @ ER1) is the same, but since the immediate data is on the source side, the EA1 code is as shown in FIG. It is not necessary, and an operation code between immediate registers (same as ADD.W #xx, Rx) is used as an operation code instead of the operation between registers.

  A transfer instruction between memories (for example, MOV.W @ ER1, @aa: 16) is a pre-instruction code for instruction expansion, an EA1 code, an EA2 code, and a transfer instruction code between registers, like the operation between the memories. However, in this example, as shown in FIG. 12, an instruction extension prefix instruction code, EA1 code (same as MOV.W @ ER1, Rx), EA2 code (MOV.W Rx, @ aa: same as 16). No operation code is required, the transfer direction of the EA1 code is the read direction, and the transfer direction of the EA2 code is the write direction. As a result, the instruction code length can be shortened (for the operation code), and the number of execution states (operation code read, destination side data read) can be shortened.

  Transfer of immediate data to memory (for example, MOV.W #xx, @ ER1) is a combination of an instruction extension prefix instruction code, an EA2 code, and an operation code, similar to the operation of the immediate data and the data on the memory. However, in this example, as shown in FIG. 14, a front instruction code for instruction expansion, an instruction code for transfer between immediate registers (same as MOV.W #xx, Rx), EA2 code ( MOV.W Rx, @aa: same as 16). As a result, the number of execution states (reading of data on the destination side) can also be shortened.

  FIG. 15 illustrates a format of a pre-instruction code (control code) for instruction extension. The instruction extension pre-instruction code shown in the figure has a bit for indicating whether or not the source side and the destination side are memories. For example, if the corresponding bit is a logical value “1”, a memory is specified, and if the corresponding bit is a logical value “0”, a general-purpose register is specified. Since the transfer instruction codes of EA1 and EA2 are the same, if the source side is a memory, the one following the instruction extension prefix instruction code is determined to be the EA1 code regardless of the destination side. On the other hand, if the source side is a general-purpose register and the destination side is a memory, it is determined as an EA2 code. In addition, it has information indicating the longword size.

  It also has information for changing the operation of the transfer instruction codes of EA1 and EA2. For example, when post-increment / pre-decrement register indirection is uniquely specified by the memory read / write direction, that is, post-increment is fixed at the time of writing, pre-decrement is at the time of reading, etc. In this case, the change information makes it possible to perform a post-increment operation at the time of reading and pre-decrement at the time of writing.

  16 and 17 show combinations of CPU addressing modes. FIG. 16 shows the data transfer instruction, and FIG. 17 shows the addition instruction. Operation instructions other than addition are the same as the addition instruction.

  The upper, middle, and lower stages in each column of “Source” in FIGS. 16 and 17 show the executable data sizes of the upper CPU 2, the first lower CPU, and the second lower CPU, respectively. Yes. B means byte (8 bits), W means word (16 bits), and L means long word (32 bits).

  In addition to the addressing modes shown in FIGS. 16 and 17, there are also program counter relative and memory indirect addressing modes used only for branch instructions, but these are not shown here.

  The host CPU 2 can arbitrarily combine the source / destination and data size addressing modes for both the data transfer instruction and the addition instruction. However, with regard to the 8-bit absolute address, only the byte size can be executed due to the characteristics of the abbreviated form and the characteristics of the 16-bit unit instruction code.

  The first lower CPU is limited to the addressing mode corresponding to the address space of 64 kB, and cannot execute the register indirect with 32-bit displacement and the 32-bit absolute address. Data size is in bytes and words. The data transfer instruction can be executed only when one of the source side and the destination side is a register directly. The addition instruction is limited to an immediate or general-purpose register on the source side and a general-purpose register on the destination side. That is, the memory has a so-called load / store type instruction set in which reading / writing of a memory is performed by a data transfer instruction and data processing is performed by a general-purpose register.

  Although the second lower CPU has an address space of 16 MB, the main purpose is to cope with an increase in the capacity of the program, and considering an application field in which high-speed processing of large-scale data is not required, Register indirect with 32-bit displacement and 32-bit absolute address cannot be executed. The data size is a byte and a word when specifying data on the memory. Longwords are possible only if the source side is an immediate or general purpose register and the destination side is a general purpose register.

  In the second lower CPU, although the number of general-purpose registers is small, any combination of the source / destination addressing modes can be used for both the data transfer instruction and the addition instruction. The data size of the transfer instruction between the general-purpose register and the memory is 8 to 16 bits long for the functional block data of the microcomputer, the internal data bus is 16 bits, and the single chip microcomputer is applied. Considering application fields that may be 16 bits (words) or 8 bits (bytes) due to characteristics such as resolution required for a microcomputer system, they do not have 32 bits (longwords). Naturally, 32-bit (long word) data can be realized by performing 16-bit (word) data transfer twice.

  On the other hand, in the second lower CPU, since the general-purpose register has a 32-bit configuration and the internal configuration of the CPU is 32-bit, there is no need to read / write data on the memory. 32-bit (long word) is also executable.

  The upper CPU, the first lower CPU 2 and the second lower CPU can be selected according to the application field and the requirements of the microcomputer system, for example, as follows.

  Regarding a functional system built in a single-chip microcomputer, that is, a microcomputer system that operates using only ROM, RAM, timer A, timer B, SCI, A / D converter, input / output port, If the program capacity is about 60 kB or less (64 kB including RAM and internal I / O registers), it is convenient to incorporate the first lower CPU.

  If the program capacity is about 60 kB or more (64 kB in total including RAM and internal I / O registers), it is convenient to incorporate a second lower CPU. The RAM, internal I / O registers, and some ROM are handled as data, and part of the address space (H'8000 to H'FF7FFF) has restrictions on access by data transfer / arithmetic instructions. However, since this part is a ROM and an unused area, there is no problem. Rather, it is desirable to delete unnecessary functions of the CPU to reduce the logical scale and reduce the cost.

  As a microcomputer system that operates using only a functional module built in such a single-chip microcomputer, there is a camera. For example, “Photo Industry” published in November 1994, “Photo Industry” pp 58-71. There is a description. It can be said that a large program capacity indicates that the function of the microcomputer system is high.

  Alternatively, a microcomputer system that operates by connecting a dedicated semiconductor integrated circuit having a relatively small address to an external bus of a single chip microcomputer in addition to a functional module built in the single chip microcomputer is also the same. An example of this is an optical disk drive, which is described in, for example, “Hitachi Microcomputer Technical Bulletin” pp38-39 published by Hitachi Microcomputer Systems in February 1996.

  On the other hand, in addition to the functional modules built into the single-chip microcomputer, that is, ROM, RAM, timer A, timer B, SCI, A / D converter, input / output port, program storage ROM and data storage DRAM, character generation ROM (CGROM), input / output circuit, control circuit, etc. are connected to operate and handle a large amount of data. For example, array processing can be considered. It is convenient to incorporate an upper CPU 2 that can use the entire address space without restriction. In addition, since a high-function bus controller for efficiently using an external memory or the like and a DMA controller for performing high-speed data transfer are also required, an upper CPU 2 having a relatively large logical scale is required. Even if used, the impact on the overall logical scale is considered to be small. Such a microcomputer system includes a printer.

  FIG. 1 shows a detailed example of the host CPU 2. The CPU 2 includes a control unit CONT and an execution unit EXEC. IDB and IAB are an internal data bus and an internal address bus included in the internal bus 30.

  The control unit CONT includes an instruction register IR1, an instruction register IR2, an instruction change unit CHG, an instruction decoder DEC, a register selector RSEL, and an interrupt control unit INTC. In particular, the control unit CONT performs a first control according to the presence / absence of an instruction extension pre-instruction code and a second control according to the presence / absence of a register extension pre-instruction code. The first control is direct arithmetic processing control of memory data, and by processing a plurality of instruction codes such as a data transfer instruction following an instruction extension pre-instruction code as one instruction, Control to enable direct calculation of data. The second control is a register designation control in consideration of upward compatibility. On the one hand, an extended general-purpose register is designated using a register instruction prefix instruction code, and on the other hand, an optional register designation field gr is designated. When (gr1, gr2) is omitted, control is performed so that register specification by the register specification field r (r1, r2), which cannot be omitted, is implicitly regarded as register specification included in the register group 0.

  The instruction decoder DEC is configured by, for example, a micro ROM, PLA (Programmable Logic Array), or a wiring logic. Part of the output of the instruction decoder DEC is fed back to the instruction decoder DEC. Such a feedback signal includes a stage code (TMG) used for transition in each instruction code and a control signal (MODS, MODD) used between instruction codes. An overview of the overall function of the first control in the instruction decoder is as follows. The instruction code for instruction extension generates a control signal (MODS, MODD), and the EA1 code and EA2 code refer to the control signal. And generating a control signal. The operation code also refers to the control signal to switch the data input / output source / destination and perform the operation processing. An instruction code is also generated internally in accordance with the control signal.

  Such a first control function of the instruction decoder DEC will be described in further detail. FIG. 1 conceptually shows a part of the function of the instruction decoder DEC. The decoding logic 200 of the instruction code (pf) for instruction extension includes a control signal (including mod: MODS and MODD), an interrupt A mask signal (mskint) is output. Other than that, it may be the same as a NOP (no operation) command, and does not perform any substantial operation. In short, the control signal mod is positioned as a signal that clearly indicates that the subsequent instruction code is an instruction code added to the instruction expansion front instruction code.

  The transfer instruction code (mov) decoding logic 201 outputs a state code signal (nxttmg), an interrupt mask signal (mskint), a general-purpose register write signal (Rdwr), and a temporary register write signal (TRDwr). The states of these signals are different depending on the control signals (mod: MODS, MODD). For example, the temporary register write signal (TRDwr) is selected when MODS = 1, and the general-purpose register write signal (Rdwr) is selected when MODS = 0. Other operations are the same as those in the case of the transfer instruction between the memory and the general-purpose register.

  The decoding logic 202 of the operation instruction code (exe) includes an interrupt mask signal (mskint), a source general-purpose register read signal (Rsrd), a destination general-purpose register read signal (Rdrd), a destination general-purpose register write signal (Rdwr), and read data A buffer read signal (RDBrd), a temporary register read signal (TRDrd), and a temporary register write signal (TRDwr) are output. The signal Rsrd reads the general register as the source register, Rdrd reads the general register as the destination register, and Rdwr instructs to write the general register as the destination register. The signal RDBrd reads a read data buffer (to be described later) of the execution unit EXEC, the signal TRDrd reads a temporary register of the execution unit EXEC (to be described later), and the signal TRDwr instructs to write a temporary register (to be described later) of the execution unit EXEC (to be described later). . The states of these signals are different depending on the control signal (mod: MODS, MODD). That is, the source general-purpose register read signal (Rsrd) and the temporary register read signal (TRDrd), the destination general-purpose register read signal (Rdrd) and the read data buffer read signal (RDBrd), the destination general-purpose register write signal (Rdwr) and the temporary register The write signal (TRDwr) is selected exclusively to select whether to use a general purpose register or a latch means such as a temporary register. In the case of the destination-side memory, a signal (mkmov) for generating an instruction code for performing an operation equivalent to executing a write transfer instruction in the CPU is output. Other operations are the same as the operation instruction for the general-purpose register.

  The instruction registers IR1 and IR2 temporarily store the read instruction. The instruction code stored in the instruction register IR1 is supplied to the instruction decoder DEC. The instruction changing unit CHG operates when an instruction code other than the read instruction is given to the instruction decoder DEC, and in other cases, the contents of the instruction register IR1 are given to the instruction decoder DEC. The instruction code other than the read instruction is equivalent to the write-type transfer instruction internally when exception processing such as an interrupt is executed according to an instruction from the interrupt control unit INTC or according to an instruction based on a control signal mkmov from the instruction decoder DEC. This is used to generate an instruction code for performing the above operation. That is, when the destination side is data on the memory, an instruction code for performing a memory write operation with an address generated by the EA2 code is automatically generated in the CPU and supplied to the instruction decoder DEC. The instruction code length of the instruction of the invention can be shortened, and the number of execution states can be shortened.

  The interrupt control unit INTC receives the interrupt request signal 31 output from the interrupt controller (INT) 3 in FIG. Further, referring to the interrupt mask signal mskint output from the instruction decoder DEC, if the interrupt is not masked, the interrupt is instructed to the instruction change unit CHG. In this case, the instruction change unit CHG generates a predetermined instruction code for interrupt exception handling according to the hardware.

  As described with reference to FIGS. 11 to 14, when a plurality of instruction codes are executed as a series, each instruction code indicates an interrupt mask via the control signal mskint, and a predetermined combination of instruction codes. Will not be interrupted.

  The register selector RSEL selects a general-purpose register based on an instruction from the instruction decoder DEC using signals Rsrd, Rdrd, Rdwr, and the like, and information on register fields r1, r2, gr1, and gr2 included in the instruction code.

  The execution unit EXEC includes general-purpose registers ER0 to ER7, a program counter PC, a condition code register CCR, temporary registers TRA and TRD, an arithmetic logic unit ALU, an incrementer INC, a read data buffer RDB, a write data buffer WDB, and an address buffer AB. including. These blocks are connected to each other by internal buses GB, DB, and WB.

  Of the registers included in the execution unit EXEC, those other than the general-purpose registers ER0 to ER31, the program counter PC, and the condition code register CCR, which are also shown in FIG. 3, cannot be referred to in programming, and are used only for the internal operation of the CPU 2. It is done. That is, the read data buffer RDB, the write data buffer WDB, the address buffer AB, and the like temporarily latch data in order to interface with the internal buses IAB and IDB. The temporary registers TRA and TRD are appropriately used for the internal operation of the microcomputer, and temporarily store, for example, intermediate results of operations.

  The read data buffer RDB temporarily stores instruction codes and data read from the ROM 4, RAM 5, internal I / O registers, or external memory (not shown). The write data buffer WDB temporarily stores write data to the ROM 4, RAM 5, internal I / O register, or external memory.

  The address buffer AB temporarily stores an address to be read / written by the CPU 2 and has an increment function for the stored contents. An address buffer having an increment function is described in JP-A-4-333153.

  The arithmetic logic unit ALU is used for various operations specified by instructions and effective address calculation. The incrementer INC is mainly used for addition of the program counter PC. In FIG. 1, the execution unit EXEC is shown as having an arithmetic logic unit ALU and an incrementer INC in units of general-purpose registers ER0 to ER31. However, in reality, E (16 bits) of the general-purpose register is shown. , H (8 bits), and L (8 bits) are divided and provided.

  When the data on the memory is directly calculated using an instruction code subsequent to the instruction extension pre-instruction code, temporary registers TRA and TRD, a read data buffer RDB, and the like are used. The temporary register TRA stores a read address (effective address) when the destination address is read when the destination side data is an operation instruction for the memory, and a destination address (when the data is written to the destination side memory). Output the same address as the read address).

  The temporary register TRD temporarily stores the source side data in the case of an arithmetic instruction in which the source side data becomes a memory, and outputs the source side data when the arithmetic instruction code is executed. In the case of an operation instruction in which the destination side data is a memory, the operation result is temporarily stored, and the write data is output when the data is written to the destination side memory.

  The read data buffer RDB further stores the destination side data temporarily in the case of an operation instruction in which the destination side data becomes a memory, and outputs the source side data when the operation code is executed.

  The registers TRA, TRD, RDB, etc. are used as appropriate in the execution of existing instructions. However, the detailed contents thereof are not directly related to the present invention, and the description thereof will be omitted.

  The CPU 2 has the two instruction registers IR1 and IR2 as described above in order to realize the second control. The register selector RSEL is supplied with the output signal of the instruction decoder DEC, the output signals of the instruction registers IR1 and IR2, and the output signal of the internal I / O register (CPUCR) 22 included in the SYSC 21.

  The instruction register IR1 is supplied with an instruction from the internal data bus IDB. The output of the instruction register IR1 is coupled to another instruction register IR2, to the instruction decoder DEC via the instruction changer CHG, and to the register selector RSEL. The output of the instruction register IR2 is coupled to the register selector RSEL. The output of the instruction decoder DEC is coupled to a register selector RSEL and the instruction register IR2. The instruction decoder DEC decodes the operation code in the operation field of the instruction fetched into the instruction register IR1. When the instruction code fetched to the instruction register IR1 is the register extension pre-instruction code, the instruction decoder DEC decodes the instruction code to register in the register group designation field (gr) of the register extension pre-instruction. The specified information is latched in the instruction register IR2. The latch signal at that time is output from the instruction decoder DEC. The register field designation information latched in the instruction register IR2 and the register designation information of the register field (r) included in the subsequent instruction fetched in the instruction register IR1 are decoded by the register selector RSEL and directly used as the information. A register in the designated register group is selected, and the subsequent instruction is executed using the selected register. After executing this instruction, the instruction decoder DEC supplies a set signal to the instruction register IR2 for clearing the latch information of the instruction register IR2 to all bit values “0” (register group 0 designation information). Therefore, even if an instruction without the register extension prefix instruction code is fetched to the instruction register IR1 thereafter, the output of the instruction register IR2 maintains the designation information of the register group 0. As a result, the register selector RSEL implicitly Assuming that the register group 0 is designated, a register according to the register designation information from the instruction register 31 is selected from the register group 0.

  The second lower CPU can be developed by deleting functional blocks and logic circuits that are not necessary for the instruction set from the configuration of FIG. The general-purpose registers are only ER0, ER1, ER7, and ER15, and the register selector RSEL can be deleted correspondingly. The address buffer increment function can also be deleted in response to the deletion of a long word size data transfer instruction for the memory.

  The instruction decoder DEC can also delete a 32-bit displacement indirect register indirect, 32-bit absolute address, memory indirect, etc., and delete a logic circuit necessary for this. An instruction in such an addressing mode has a long instruction code, inevitably increases the number of execution states, and long word size data transfer instructions and the like correspond to the internal data bus having 16 bits. Since the control logic is likely to be complicated by performing two word size data transfers, the logical scale can be reduced if these addressing modes and long word size data transfer instructions can be deleted. .

  When deleting a logic circuit, unnecessary function blocks such as general-purpose registers are deleted, the signal output by the deleted function block is fixed to the inactive level, and the deleted block is input. The signal that is connected may be disconnected or released. As described above, the logical scale can be automatically reduced if the remaining logic circuits are fixed to the inactive level, or are reconnected in a state of being disconnected or released. Whatever method is adopted, the development efficiency can be improved by using a subset of the upper CPU as compared with a new development.

  FIG. 18 shows a detailed block diagram of a part of the register selector RSEL and the instruction register IR2.

  The instruction register IR2 includes a latch circuit (LGR1) 321 and a latch circuit (LGR2) 322 as holding means. These latch circuits (LGR1, LGR2) 321, 322 latch the register group designation information in the register group designation fields gr1, gr2, as described above.

  According to FIG. 18, the latch circuits 321 and 322 are constituted by so-called reset type D flip-flops. An instruction execution end signal RSLGR designated from the instruction decoder DEC is input as the reset signal RSLGR. LGRCL designated from the instruction decoder DEC is input as a latch clock, and bits 7 to 4 and 3 to 0 of the instruction code held in the instruction register IR1 as data (in the case of four groups, bits 5 and 4 1 or 0) may be input. The latch clock LGRCL becomes active when an instruction code designating a register group (an optional instruction code for register extension) is executed, and bits 7 to 4 are register fields (gr) at that time. , 3 to 0 are latched. The latch circuits 321 and 322 are set to predetermined values based on the control signal (reset signal RSLGR) from the instruction decoder DEC at the end of execution of the instruction. In this embodiment, all bit values are cleared to “0”.

  Instructions that do not have a register extension prefix instruction code that designates a general-purpose register group are executed because the latch circuits (LGR1, LGR2) 321, 322 remain cleared to the value “0”. At this time, a general-purpose register of the register group 0 is designated.

  On the destination register designation side of the register selector RSEL, there are a latch circuit 331 for holding information of a register group designation field (gr2) output from the latch circuit (LGR2) 322, and a register designation field (from the instruction register IR1). A latch circuit 332 that latches the information of r2) is provided. The latch circuits 331 and 332 are latched by the inverted clock φ # of the system clock φ, and the destination register selection operation is performed later than the source register selection operation. As a result, the latch timing of the register designation information on the destination side, that is, the destination register selection timing is delayed by 0.5 state from the source register selection timing. The source register is selected in advance as an address register, and the destination register can be selected later for writing data.

  19 and 20 illustrate a part of the logical description of the register selector RSEL corresponding to the general-purpose register ER8. The description of FIG. 20 is the remaining logical description following FIG.

  The logic descriptions shown in FIGS. 19 and 20 are called RTL (Register Transfer Level) or HDL (Hardware Description Language) description, and can be logically expanded into a logic circuit by a known logic synthesis tool. HDL is standardized as IEEE 1364. The syntax of the logical description shown here conforms to the case statement, and when there is a change in the value or signal defined in () next to alwayss @, The description is to process. The symbol “!” Represents a logical sum, and “&” represents a logical product. “3′b001” means 001 having a 3-bit length.

  The logical description is a register selection description part beginning with alwayss @ (gr1, r1, gr2, r2) begin, an always @ (rs8 or rsgb or rsdb or wbrs or rd8 or rddbb or rddb or wbrd) bus description part. , Alwayss @ (wbr8 or r2 [3] or byte or word or long) is broadly classified into a register size designation description part beginning with begin.

  The register selection description part is a description for selecting the general-purpose register ER8 when the register field r [2: 0] = 0 and the register field gr [1: 0] = 1.

  That is, when the group field of the source register is gr1 = 1 (gr1 = 4′b0001) and the register field of the source register is r1 = 0 (r1 = 3′b000), the signal rs8 for selecting the register ER8 as the source register is Activated (rs8 = 1). Otherwise, the signal rs8 remains inactive (rs8 = 0).

  When the group field of the destination register is gr2 = 1 (gr2 = 4′b0001) and the register field of the destination register is r2 = 0 (r2 = 3′b000), the register ER8 is selected as the destination register. The signal rd8 is activated (rd8 = 1). Otherwise, the signal rd8 remains inactive (rd8 = 0).

  In the always statement of the bus selection description part, rsgb is a signal for instructing to output the contents of the source register to the bus GB, rsdb is a signal instructing to output the contents of the source register to the bus DB, and wbrs is a signal of the bus WB. A signal instructing to output the contents to the source register, rdgb is a signal instructing to output the contents of the destination register to the bus GB, and rdb is a signal instructing to output the contents of the destination register to the bus DB , Wbrd are signals instructing to output the contents of the bus WB to the destination register.

  The signal rs8 is activated when the instruction decoder (DEC) 33 is instructed to output the contents of the registers in the register specification fields (gr1, r1) indicating the source register to the internal bus GB (rsgb = 1). Or the signal rd8 is activated when it is instructed to output the contents of the registers in the register specification fields (gr2, r2) indicating the destination register to the internal bus GB (rdgb = 1). If there is, the signal r8gb instructing data output from the general-purpose register ER8 to the internal bus GB is activated (r8gb = 1).

  Similarly, the signal rs8 is activated when the instruction decoder DEC instructs to output the contents of the register in the register specification field (gr1, r1) indicating the source register to the internal bus DB (rsdb = 1). The signal rd8 is activated when it is instructed to output the register contents of the register designation fields (gr2, r2) indicating the destination register to the internal bus DB (rddb = 1). In this case, the signal r8db for instructing output from the general-purpose register ER8 to the internal bus DB is activated (r8db = 1).

  Further, when the instruction decoder DEC instructs to input data from the internal bus WB to the register in the register designation field (gr1, r1) indicating the source register (wbrs = 1), the signal rs8 is activated. Or the signal rd8 is activated when it is instructed to input data from the internal bus WB to the register in the register designation field (gr2, r2) indicating the destination register (wbrd = 1). In this case, the signal wbr8 that instructs the general-purpose register ER8 to input from the internal bus WB is activated (wbr8 = 1).

  In the always statement in the logical description part of the register size selection, r2 [3] means the value of the fourth bit from the lower order of the register field r2.

  When data input from the internal bus WB is instructed to the general-purpose register ER8, if the data size is a long word size (long = 1), the general-purpose register ER is written in 32 bits (wb8e = wb8h = wb8l = 1) ). The signal wb8e is the input gate signal of the 16-bit register E portion of FIG. 3, the signal wb8h is the input gate signal of the 8-bit register RH portion of FIG. 3, and the signal wb8l is the 8-bit register RL portion of FIG. Means input gate signal.

  In the case of the word size (word = 1), the general-purpose register E is written in 16 bits corresponding to the value of bit 3 of r2 (wb8e = 1, wb8h = wb8l = 0) or the general-purpose register R ( (RH, RL) is specified as 16 bits (wb8e = 0, wb8h = wb8l = 1). Further, in the case of byte size, corresponding to the value of bit 3 of r2, 8 bits are written as general register RH (wb8e = 0, wb8h = 1, wb8l = 0), or 8 bits as general register RL. It is specified whether to write (wb8e = wb8h = 0, wb8l = 1).

  Other register numbers are the same except for the portions of gr and r in the logical description. In the register selector 34, the decode logic of gr is added to the register selector of the existing lower CPU, and the decode logic corresponding to the new general-purpose registers ER8 to ER31 is added.

  Since the output destination of the register selector 34 is simply divided in units of eight general-purpose registers in accordance with the contents of gr, the number of general-purpose registers that can be specified can be increased in the same way for any instruction.

  FIG. 21 and FIG. 22 show an example of register selector selection logic related to the register ER7 that can also be used as a stack pointer in a logical description. The description of FIG. 22 is the remaining logical description following FIG. The description form is the same as in FIGS. Although not particularly limited, sspgr is information specifying a group of registers used as a stack pointer for a subroutine branch instruction, and ispgr is information specifying a group of registers used as a stack pointer for exception handling. . The information sspgr and ispgr are supplied from the control register (CPUCR) 22 included in the system controller (SYSC) 21 to the register selector RSEL.

  In addition to the logical description for register selection similar to FIG. 19, a register selection signal is generated by control signals (sspgb, wbssp, ispgb, wbisp) from the instruction decoder and stack pointer designation control bits sspgr, ispgr. The signal sspgb instructs to output the value of the register used for the subroutine stack pointer to the bus GB, the signal wbssp instructs to supply data from the bus WB to the register used for the subroutine stack pointer, The signal ispgb instructs to output the value of the register used for the exception handling stack pointer to the bus GB, and the signal wbisp instructs to supply data from the bus WB to the register used for the exception handling stack pointer. To do. Conventionally, when a subroutine branch and a stack pointer for interrupt exception processing are provided independently, they are separated into subroutine branch (sspgb, wbssp) and interrupt exception processing (ispgb, wbisp), and an instruction decoder. Need to be configured. In this method, functions that are originally collected for different processes are separated from each other, so that there is little increase in logical scale.

  In addition to this, the registers ER15, ER23, and ER31 that can serve as exception processing stack pointers can be similarly configured. That is, the register ER15 is selected when sspgr = 1 or ispgr = 1. Similarly, the register ER23 is selected when sspgr = 2 or ispgr = 2, and the register ER31 is selected when sspgr = 3 or ispgr = 3.

  Since the configuration of the control register (CPUCR) 22 is a known technique, a detailed description thereof is omitted. The control register (CPUCR) 22 is preferably selected so that register group 0 is selected at reset (sspgr = ispgr = 0).

  Also, a current group selection bit may be provided. That is, when the register extension prefix instruction code is not added, the current group selection bit is provided in the control register similar to the stack pointer group selection bit instead of register group 0, and the current group selection bit is set by the RSLGR signal. The contents are loaded into the instruction register IR2 (LGR1, LGR2).

  When a value other than 0 is set in the current group selection bit, the NOP instruction (H′0000) is used as a prefix instruction code for register group 0. After execution of this instruction code, the next instruction code may be executed without accepting an interrupt.

  In order to specify the register group 0, H'0000 is used, which is the same code as the existing NOP instruction, and the NOP instruction should not be used. Instead of the NOP instruction, BRA $ + 2 or the like may be used ("$ + 2" indicates the address of the second address, that is, the address of the next instruction) with respect to the address where the instruction exists.

  Since the target of the general-purpose register to be mainly used differs depending on the execution contents of the program at each time point, it is possible to increase the processing speed of the group to be mainly used, and to improve the processing speed of the CPU. For example, the general-purpose register of register group 3 is assigned to a predetermined interrupt process and is not used in other processes, and when the interrupt occurs, the current group is changed to 3, and a register extension prefix instruction The processing for the general register group 3 can be executed at high speed without code.

  For example, when the interrupt priority is set to 4 levels, interrupt nesting usually has 4 levels. That is, if the interrupt priority is 3 (high) to 0 (low), interrupts with the same priority will not be accepted at the same time, so interrupts with priority 0 will be masked first, and priority will be given during the execution of the main program. 1 interrupt occurs, a priority 2 interrupt occurs in the middle of this processing, and a priority 3 interrupt occurs in the middle of this processing, the maximum nest 4 occurs.

  For example, group 3 is reserved for interrupt 3 priority processing, group 2 is reserved for interrupt 2 priority processing, and groups 0 and 1 are used for other interrupts and general processing. If a program is built in the general-purpose register group 3, the general-purpose register group 3 can be used without saving the general-purpose registers when an interrupt of priority 3 occurs, so that the interrupt response speed can be improved. The same can be done when an interrupt of priority 2 occurs, and interrupt processing with higher priority can be processed at high speed.

  When the CPU processing is controlled by an operating system (OS) or the like, the CPU processing is divided into so-called tasks, and each task is managed independently. For example, the stack area is also managed independently for each task.

  When the task is switched, the stack area is also switched. Conventionally, the contents of the stack pointer in use must be saved and the contents of the stack pointer must be updated. In the case of updating, it is necessary to restore the contents of the stack pointer saved by the task last time.

  In the case of such task switching, in the above example, only the contents of the register (CPUCR) 22 need be rewritten. Since the contents of the stack pointer before switching can be retained, there is no need to save or restore. Substantial processing performance can be improved by omitting processing that does not directly affect the processing of the CPU.

  An interrupt occurs independently of task execution and cannot be predicted from the task. When interrupts are permitted in each task, a stack area (generally corresponding to the number of interrupt priorities) as many as possible multiple interrupts must be secured. In the past, this had to be done for each task, which undesirably increased stack usage. In this embodiment, the exception handling stack can be independently managed by using the exception handling stack pointer, so that each task does not need to secure an interrupt stack area. Thus, the stack usage can be suppressed. The stack is composed of RAM, and the capacity of RAM that can be built in a single-chip microcomputer is limited by the chip size, etc., so by enabling the use of a stack pointer for exception handling, even in a single-chip microcomputer. Make OS easier to apply.

  In addition, by making the initial value of the control register (CPUCR) 22 correspond to the register group 0 and making it possible to use the same stack pointer as that of the existing lower CPU in the initial state, existing software assets can also be used. It can be used effectively.

  When ER7, ER15, ER23, and ER31 are not used as stack pointers, they can be used as other general-purpose registers, thereby improving utilization efficiency and usability.

  23 to 25 exemplify the logic 201 for decoding the transfer instruction code (mov) included in the instruction decoder DEC. The logical descriptions shown in FIGS. 23 to 25 are described in the same RTL (Register Transfer Level) or HDL (Hardware Description Language) as in FIG. The symbol “!” Represents a logical sum, and “&” represents a logical product. “3′b001” means binary data 001 having a 3-bit length. IR [8] means the 9th bit logical value from the least significant bit of the instruction register IR.

  The logical descriptions in FIGS. 23 to 25 correspond to logical descriptions for decoding a code of a word size transfer instruction (MOV.W @aa: 16, Rn) using a 16-bit absolute address. In the logical description of FIGS. 23 to 25, 16'b0110_101? Described in the next line of the caseex (IR)? _? ? 00_? ? ? ? Means the code of the transfer instruction. Byte size when IR [8] = 0, Word size when IR [8] = 1, Memory when IR [7] = 0 → General-purpose register (read type), General-purpose register when IR [7] = 1 It means transfer of memory (write type). Whether the instruction is executed as an independent transfer instruction or as part of a direct processing instruction for data on the memory is indicated by the values of the signals MODS and MODD. 23 to 25, the control signal is generated according to the state code TMG, and the next state is determined according to the current state code TMG value and the MODS and MODD values at that time. The value of the code NEXTTMG is determined. The control of whether to execute as an independent transfer instruction or as part of a direct processing instruction for data on the memory is roughly classified by the MODS and MODD signals. Specifically, when MODS = MODD = 0, it is executed as an independent transfer instruction. The operation is the same as that of an existing transfer command. In particular, a portion not shown can be made in the same manner as an independent transfer command.

  When MODS = 1, it is executed as a read operation of the source side data. Read data is not written in the general-purpose register, but is written in the temporary register TRD.

  When MODD = 1 and MODS = 0 or MODSE = 1, the data is executed as a destination-side data read operation. The read address is written to temporary register TRA. After the read data is taken into the read data buffer RDB, execution is completed one state earlier. MODSE is a signal indicating that the execution of the read transfer instruction code on the source side is completed, and is generated by the decoding logic 201.

  The writing of the read data to the temporary register TRD and the writing of the read address to the temporary register TRA may be executed without distinction in any case (the operation is not affected even if it is not used. Can save logical waste).

  Therefore, as compared with an independent transfer instruction (existing transfer instruction), writing to the general-purpose register is prohibited when MODS = 1, and only one-state shortening difference exists when MODD = 1. The increase in logical scale can be minimized.

  As shown in FIG. 15, the long word size is designated by the LNG signal in the same manner as the MODS and the MODD by designating the long word size of the instruction extension prefix instruction code.

  In the figure, a lowercase signal is a signal generated and output by the instruction decoder DEC, and an uppercase signal is a signal input to the instruction decoder DEC.

  The state code TMG is generated in the first part (1-1) of the logical description shown in FIG. The state code TMG proceeds from 1 → 2 → 3. However, in the case of the destination side data read operation (MODD = 1, MODS = 0 or MODSE = 1), the TMG ends in 1 → 2.

  Note that the next state code in the case of NEXTTMG [5] = 0 is simply the value of the lower bits. The next state code in the case of NEXTTMG [5] = 1 is configured to be 5'b00001.

  Bus control is performed in the second part (1-2) of the logical description shown in FIG. When nop = 0, bus access is started, and when nop = 1, bus access is prohibited. Data = 0 indicates an instruction read, and data = 1 indicates a data access. long = 1 indicates a long word size, and when long = 0, byte = 0 indicates a word size, and byte = 1 indicates a byte size. “write = 0” indicates a read, and “write = 1” indicates a write.

  In the case of this transfer instruction, instruction read is performed using state codes 1 and 3 and data access is performed using state code 2. Data access read / write is instructed by IR [7]. In the case of instruction read, the contents of the internal data bus IDB are stored in the instruction register IR and the read data buffer RDB at a predetermined timing. In the case of data read, the contents of the internal data bus IDB are stored in the read data buffer RDB at a predetermined timing. In the case of data write, the contents of the write data buffer WDB are output to the internal data bus IDB at a predetermined timing.

  The effective address is calculated in the third part (1-3) of the logical description shown in FIG. In the case of this transfer instruction, the EA extension 16 bits of the instruction code held in the read data buffer RDB is sign-extended to 32 bits by the dbrext signal with the state code 2 (= 5′b00010), and then the internal bus GB. Output to. The contents of the bus GB are stored in the address buffer AB every state, and no particular control is required.

  The fourth part (1-4) of the logical description shown in FIG. 24 controls the transfer data. In the case of the read type (IR [7] = 0), the read data is output from the read data buffer RDB to the bus DB with the state code 3. When MODS = 0, it is sent to the general-purpose register. When MODS = 1, it is temporary. Store in register TRD.

  In the case of the write type (IR [7] = 1), state code 2 is output from the general-purpose register when MODS = 0, and is output from the temporary register TRD to the internal bus DB when MODS = 1. The data is output to the internal data bus IDB via the write data buffer WDB.

  The interrupt mask signal is controlled in the fifth part (1-5) of the logical description shown in FIG. Further, when the reading of the data on the source side is completed, the control signal MODSE is generated.

  23 and 25, when MODS = 1 or MODD = 1, a part of the input operation record may be different from the transfer command. For example, bit 15 of the opcode may be used for another definition.

  In order to reduce the logical scale, the bits (opcode bits 8 to 10) for determining the memory designation method such as the addressing mode are made common.

  FIG. 26 and FIG. 27 illustrate the decoding logic 202 of the operation instruction code (exe) included in the instruction decoder DEC by a logical description. The logical description shown by both FIG. 26 and FIG. 27 corresponds to the logical description for decoding the code of the inter-register addition instruction (ADD.W Rm, Rn).

  Similarly to the above, whether to execute as an independent transfer instruction or as a part of a processing instruction for data on the memory is instructed by the MODS and MODD signals. In particular, a portion not shown (ALU control or the like) can be performed in the same manner as an independent operation instruction.

  The state code TMG is generated in the first part (2-1) of the logical description shown in FIG. The state code TMG ends with 1 (= 5'b00001). Bus control is performed in the second part (2-2) of the logical description shown in FIG. The instruction read ends with state code 1.

  Operation data is controlled by the third part (2-3) of the logical description shown in FIG. When MODS = 0, the source side data is used as a general-purpose register, and the contents of the general-purpose register are read out to the DB (rsdb). When MODS = 1, the source side data is used as a memory, and the contents of the temporary register TRD are read out to the DB (trdb).

  When MODED = 0, the destination side data is used as a general-purpose register, the contents of the general-purpose register are read to GB (rdgb), and the operation result is written to the general-purpose register (wbrd). When MODED = 1, the destination side data is used as a memory, the contents of the read data buffer are read to the bus DB (rdbdb), and the operation result is written to the temporary register TRD (wbtrd).

  In the fourth part (2-4) of the logical description shown in FIG. 27, the interrupt mask signal is controlled. When the destination side is a memory, a control signal mkmov is generated to instruct the instruction change unit CHG to generate an instruction code that performs the same operation as the write type transfer instruction. Further, the long word size signal LNG and the byte size signal BYTE are continued.

  28 to 30 show logic logic for generating an instruction code that performs an operation equivalent to the internally generated write-type transfer instruction among the decoding logic 202 of the operation instruction code (exe) included in the instruction decoder DEC. The description is illustrated.

  The instruction code that performs the same operation as the internally generated write-type transfer instruction always performs the same operation, and does not refer to the MODS or MODD control signals.

  The state code TMG is generated in the first part (3-1) of the logical description shown in FIG. The state code TMG proceeds from 1 to 3. Bus control is performed in the second part (3-2) of the logical description shown in FIG. Data write is performed with state code 1 (= 5'b00001), and instruction read is performed with state code 3 (= 5'b00011). The data size is indicated by control signals LNG and BYTE generated by the operation instruction code.

  The effective address is reused in the third part (3-3) of the logical description shown in FIG. With the state code 1, the effective address held in the temporary register TRA is output to the internal bus GB. The transfer data is controlled by the fourth part (3-4) of the logical description shown in FIG. With the state code 3, the data is output from the temporary register TRD to the internal bus DB, and is output to the internal data bus IDB via the write data buffer WDB.

  In the fifth part (3-5) of the logical description shown in FIG. 30, all control signals are initialized. Interrupts are also permitted, and if an interrupt is requested, interrupt exception handling can be continued.

  The logic description of the logic circuit that decodes the instruction extension prefix instruction code (pf) is not particularly shown, but generates control signals such as mod and mskint according to the decoding result of the instruction extension prefix instruction code of FIG. Then, the logic operation as exemplified in FIGS. 23 to 30 is controlled by MODS, MODD, etc., and the instruction decoder DEC as a whole can directly control the operation of the data in the memory.

  FIG. 31 shows the execution timing of the first addition instruction (ADD.L ER0, ER1) without the register extension prefix instruction code.

  ADD. Since LER0 and ER1 use only general-purpose registers of group 0, they do not require a register extension prefix instruction code for specifying a general-purpose register group. For example, the existing lower CPU, for example, the March 1995 ( The instruction is the same one word as the CPU described in “H8S / 2600 Series H8S / 2000 Series Programming Manual” issued by Hitachi, Ltd.

  Although not particularly limited, the internal data bus (IDB) is 16 bits, and it will be described that the built-in ROM 4 and RAM 5 can be read / written in one state. The CPU executes instructions in a three-stage pipeline of instruction fetch, decode, and execution.

  In slot C2 of cycle T0 (φ # synchronization: φ # synchronization that is an inverted clock of the clock signal φ), an address is output from the address buffer AB of the CPU 2 to the bus IAB. Further, a bus command (BCMD) indicating instruction fetch (if) is output from the instruction decoder DEC.

  In slot C1 (φ synchronous) of cycle T1, the contents of the address bus IAB are output to the peripheral address bus (PAB), a read cycle is started based on the bus command, and data is output to the peripheral data bus (PDB). . In slot C2, the peripheral data bus (PDB) read data is obtained on the internal data bus IDB, and is latched in the instruction register IR1 in slot C1 of cycle T2. The above operation is performed by controlling the execution of the previous instruction. The peripheral data bus (PDB) and the peripheral address bus (PAB) are not shown for peripheral circuits connected to the internal data bus (IDB) and the internal address bus (IAB). The built-in ROM 4 and RAM 5 perform operations corresponding to the peripheral address bus and the peripheral data bus in the module.

  When the execution of the immediately preceding instruction is completed, when the execution of the instruction is started earliest, the instruction code is input to the instruction decoder DEC of the control unit CONT in the slot C1 of the cycle T2, and the content of the instruction is decoded. . The instruction decoder DEC outputs a control signal according to the decoding result to control each part. Part of the instruction (register designation field information: SEL1) is given to the register selector RSEL. In the figure, the source side register designation field information SEL1 = 0 and the destination side register designation field information SEL2 = 1. SEL1 corresponds to r1 [3: 0] of RSEL in FIG. 18, and SEL2 corresponds to r2 [3: 0].

  In the inter-register operation instruction, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC in the slot C2 of the cycle T2. An address signal is output from address buffer AB to address IAB. A control signal is given to the register selector 34. At this time, since the latch circuits (LGR1, LGR2) 321 and 322 are all cleared to 0, the signals from the register fields SEL1 and SEL2 and the control signal A (Rs-DB, Rd-GB) output from the control unit CONT. ), A register selection signal B (R0-DB, R1-GB) is generated.

  From cycle T3, the next next instruction is read. In slot C1 of cycle T3, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. A register selection signal C (selectC: WB-R1) is generated based on the input signal SEL2 and the control signal B (WB-Rd). The register selection signal B selects a register, and inputs the data of the source side and destination side registers (Rs, Rd) to the arithmetic logic unit ALU. The operation content of the arithmetic logic unit ALU is instructed by the control unit CONT by the control signal C (control C). Addition, logical operation, shift, etc. can be performed in one clock. For example, the instruction performs a 32-bit addition. Instructs the control unit CONT to load the next instruction.

  Clearing of the latch circuits (LGR1, LGR2) 321, 322 is instructed by the control signal B (RSLGR). The latch circuit (LGR1) 321 transmits the result cleared in the slot C1 of the cycle T3, and the latch circuit (LGR2) 322 transmits the result cleared in the slot C2 of the cycle T3.

  In slot C2 of cycle T3, the calculation result of the arithmetic logic unit ALU is written to the destination register (ER1) selected by the register selection signal via the internal bus WB. Although not shown, the condition code register CCR is updated by the control signal C.

  In the example of FIG. 31, the inter-register operation between the register groups 0 is substantially executed in one state.

  FIG. 32 shows the execution timing of the second addition instruction (ADD.L ER8, ER1) to which the register extension prefix instruction code is added.

  A 2-word instruction is added by adding a register extension prefix instruction code designating a general-purpose register group. The second word is the ADD. It is the same as L R0 and R1. That is, because gr1 = 1, the register number n = 8 is interpreted for the same r1 = 0.

  In slot C2 of cycle T0, the address buffer AB of CPU 2 or the address is output to the address bus IAB.

  In slot C1 (φ synchronization) of cycle T1, the contents of the address bus IAB are output to the peripheral address bus (PAB), and a read cycle is started. Read data is obtained on the internal data bus IDB in the slot C2, and is latched in the instruction register IR1 in the slot C1 of the cycle T2. This is an optional register extension prefix instruction code word with a register group field.

  Subsequently, the next address (the content that is +2) is output to the address bus IAB in the slot C2 of the cycle T2, and this read data is latched in the instruction register IR in the slot C1 of the cycle T3. The above operation is performed by controlling the execution of the previous instruction, and the relative relationship may be different.

  When the execution of the immediately preceding instruction is completed, when the execution of the instruction is started earliest, the instruction code (register extension pre-instruction code) is input to the control unit CONT in the slot C1 of cycle T2, and the instruction The contents are deciphered. According to the result of decoding, a control signal is output to control each part. The group field latch signal LGRCL is issued, and the register group designation field (bits 7 to 0 of IR1) is latched by the latch circuits (LGR1, LGR2) 321 and 322.

  In slot C2 of cycle T2, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address signal is output from address buffer AB to address bus IAB.

  From cycle T3, the next next instruction is read. In slot C1 of cycle T3, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. A continuous command signal (interrupt inhibition signal: continue = mskint) is output to the interrupt acceptance circuit by the control signal B (control B) for not dividing the first word and the second word. Even if an interrupt request or the like is generated, the execution of the instruction can be continued by this signal. The contents of the latch circuits (LGR1, LGR) 321 and 322 are held.

  On the other hand, an instruction code (instructing an addition instruction) is input to the instruction decoder (DEC) 33 in the slot C1 of the cycle T2, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since LGR1 = 1 and LGR2 = 0, the register selection signal B (R8-DB, R1) is selected based on SEL1 (and SEL2) and the control signal A (Rs-DB, Rd-GB) output from the instruction decoder DEC. -GB) is generated. Other operations based on the second word can be made the same as those of the first addition instruction (ADD.L ER0, ER1). Similar to the first addition instruction, the control signal B (RSLGR) instructs the latch circuits (LGR1, LGR2) 321 and 322 to be cleared. The latch circuit (LGR1) 321 transmits the result cleared in the slot C1 of the cycle T4, and the latch circuit (LGR2) 322 transmits the result cleared in the slot C2 of the cycle T4.

  Other than outputting latch signals and continuous instruction signals of the latch circuits (LGR1, LGR2) 321 and 322 corresponding to the first word (prefix instruction code for register expansion), the contents of the instruction decoder DEC are stored in the existing CPU instructions. Can be equivalent to a decoder. Needless to say, the portion of the instruction decoder DEC corresponding to the register extension prefix instruction code is relatively small. That is, the addition of logical scale can be minimized. In addition, since most of the instruction decoder DEC can be equivalent to the instruction decoder of the existing CPU, the conventional design assets can be used effectively.

  For other instructions, any general-purpose register can be specified by adding the same register extension prefix instruction code. The instruction code can be applied to an instruction having an instruction code having a register designation field.

  FIG. 33 shows the execution timing of a memory register type addition instruction (ADD.W @aa: 16, R9). That is, a register extension prefix instruction code having a register group field, an instruction extension prefix instruction code for a memory / register type operation, MOV. W @aa: 16, the instruction code corresponding to R0, ADD. The timing when an instruction regarded as one instruction is executed by combining instruction codes corresponding to W R0 and R1 is shown.

  A register extension prefix instruction code having a register group field is set to H'0001 so as to designate a general register of group 1. That is, since gr2 = 1, the register number n = 9 is interpreted for the same r2 = 1.

  Also, the memory instruction type instruction extension prefix instruction code is H'0108 according to FIG. 15, and the MODS signal indicates that the source side is a memory. Although this instruction has no direct relationship, when the EA1 instruction code is executed, the general-purpose register is selected by combining gr1 and r1. Further, when the operation instruction code is executed, the general-purpose register is selected by combining gr2 and r2.

  The transfer instruction code reads the memory as in the case of the existing transfer instruction, but stores the read data in the temporary register TRD based on the instruction to set the source side as the memory by the prefix instruction code. Continue the instruction to use the source side as memory.

  The operation instruction code reads the source-side data from the temporary register (TRD) instead of the general-purpose register in accordance with an instruction to set the source side as a memory. Other operations are the same as those of the existing operation instruction.

  In slot C2 of cycle T0 (φ # synchronization; # indicates inverted logic), the address is output from the address buffer AB of the CPU 2 to the IAB.

  In slot C1 (φ synchronization) of cycle T1, the contents of IAB are output to PAB, and a read cycle is started. In slot C2 of cycle T1, read data is obtained on the internal data bus, and this is latched into IR (IR1) in slot C1 of cycle T2. This is an optional instruction word (a register instruction prefix instruction code) having a register group field.

  Subsequently, the next address (the content that has been +2) is output to IAB in slot C2 of cycle T2, and this read data is latched in IR (IR1) in slot C1 of cycle T3. The above operation is performed by controlling the execution of the previous instruction, and the relative relationship may be different.

  When the execution of the immediately preceding instruction is completed, when the execution of the instruction is started earliest, an instruction code (register extension pre-instruction code) is input to the instruction decoder DEC in the slot C1 of cycle T2, and the instruction The contents are deciphered. According to the result of decoding, a control signal is output to control each part. A group field latch signal LGRCL is issued, and the register group designation field (bits 1 to 0 of IR1) is latched in the latches LGR1 and LGR2.

  In slot C2 of cycle T2, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. Address information is output from the address buffer AB to the address bus IAB.

  In the slot C2 of the cycle T1, the address buffer AB of the CPU 2 or the address information is output to the address bus IAB.

  In slot C1 (φ synchronization) of cycle T2, the contents of address bus IAB are output to PAB, and a read cycle is started. Read data is obtained on the internal data bus in slot C2 of cycle T2, and is latched into IR in slot C1 of cycle T2. This is a pre-instruction code (pf) for instruction expansion indicating an operation on the memory.

  In slot C2 of cycle T3, the next address (the content that is +2) is output to the address bus IAB, and this read data is latched in the instruction register IR (IR1) in slot C1 of cycle T4 (the first word of the MOV instruction). (Mov-1)).

  In slot C1 of cycle T3, the instruction code (instruction extension pre-instruction code pf) is input to the decoder DEC, the contents of the instruction are decoded, and in the case of such an instruction extension pre-instruction code, the source side data is Indicates that it exists in memory. That is, the MODS signal is set to 1 as the control signal C and fed back to the decoder DEC.

  In slot C2 of cycle T3, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. Address information is output from the address buffer AB to the address bus IAB.

  In slot C1 of cycle T4, the instruction code (first word (mov-1) of MOV instruction) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since the absolute address addressing mode is used, the absolute address, which is the EA extension unit, is subsequently read, the source data is read based on the absolute address, and the read result is stored in the temporary register TRD.

  In slot C1 of cycle T4, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. In slot C2 of cycle T4, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. Address information is output from the address buffer AB to the address bus IAB.

  From cycle T4, a read cycle is started, and this read data is latched in the read data buffer RDB in slot C1 of cycle T5 (the second word (mov-2) of the MOV instruction, that is, an absolute address that is an EA extension). ).

  In slot C1 of cycle T5, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. In slot C2 of cycle T5, the contents (absolute address) of the read data buffer RDB are read to the internal bus GB and input to the address buffer AB. Address information is output from the address buffer AB to the address bus IAB.

  Source data is read from cycle T6. In slot C2 of cycle T5, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. Address information is output from the address buffer AB to the address bus IAB.

  The read data (source data) is stored in the read data buffer RDB in the slot C1 of the cycle T7. Further, the data is output from the read data buffer RDB to the internal bus DB and input to the arithmetic logic unit ALU. The arithmetic logic unit ALU is not operated.

  In slot C2 of cycle T7, the read data is output from the arithmetic logic unit ALU to the internal bus WB, and the signal MODS is set to 1. Therefore, the read data is stored not in the general-purpose register but in the temporary register TRD.

  In slot C1 of cycle T7, an instruction code (ADD instruction (add)) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since the signal MODS is set to 1, the source side data is read from the temporary register TRD instead of the general purpose register. The destination side reads from the general-purpose register and stores the operation result in the general-purpose register.

  In slot C2 of cycle T7, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. Address information is output from the address buffer AB to the address bus IAB.

  In slot C1 of cycle T8, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. Further, the destination side is not changed, and the destination data is output from the general-purpose register (ER9) to the internal bus GB according to the register group field (gr2 = 1) and the register field (r2 = 1), and the source side data is changed. In accordance with the signal MODS, the data is output from the temporary register TRD to the internal bus DB, and both are input to the arithmetic logic unit ALU. The arithmetic logic unit ALU is set to an addition operation.

  In slot C2 of cycle T8, the operation result is output from the arithmetic logic unit ALU to the internal bus WB and stored in the general-purpose register (ER9).

  In addition, a continuous command signal is output with a control signal B for preventing the first word and the second word and thereafter from being divided. Even if an interrupt request or the like is generated, the execution of the instruction can be continued by this signal.

  That is, the output of the signal MODS corresponding to the instruction instruction prefix instruction and the output of the continuous instruction signal, the selection of the data storage destination according to the signal MODS corresponding to the transfer instruction code, the output of the continuous instruction signal, and the addition instruction code Except for the selection of the data reading source according to the signal MODS, the logical configuration of the instruction decoder DEC can be made equivalent to that of the instruction decoder of the lower CPU. Needless to say, the portions corresponding to these are relatively small. That is, logical additions and changes can be minimized. In addition, since most of the instruction decoder DEC can be made equivalent to the instruction decoder of the existing lower CPU, the conventional design assets can be used effectively.

  For other arithmetic instructions (addition, subtraction, multiplication, division, comparison, logical product, logical sum, exclusive logical sum, etc.), the same instruction extension prefix instruction code and transfer instruction code are added. , Memory and general-purpose register operations can be realized.

  In addition, when the addressing mode on the source side is set to register indirect or the like, a prefix instruction code for register expansion having a register group field is added to the head of the instruction so that one of gr1 = 1 to 3 is set. The general-purpose registers on the side can be grouped 1 to 3. That is, the register extension prefix instruction code gr1 having a register group field corresponds to the source side, and gr2 corresponds to the destination side.

  FIG. 34 shows the execution timing of the register / memory type addition instruction (ADD.WR1, @ aa: 16). That is, the instruction extension prefix instruction code, MOV. W @aa: 16, an instruction code corresponding to R0, and ADD. The timing when an instruction regarded as one instruction is executed by combining instruction codes corresponding to W R1 and R0 is shown. The pre-instruction code for instruction expansion at this time is H'0104 according to FIG. 15, and the signal MODED indicates that the source side is a general-purpose register and the destination side is a memory.

  Similar to the existing transfer instruction, the transfer instruction code is generated based on the instruction (MODD) that reads the memory from the slot C2 in cycle T4 and sets the destination side as the memory by the instruction extension prefix instruction code. The effective address (memory address) is stored in the temporary register TRA. Further, at the time when the read data is stored in the read data buffer DBR in the slot C1 of the cycle T6, the execution is completed one state earlier than the case of reading the existing transfer instruction or the data on the source side. For this reason, instruction fetch and PC increment are not performed. The instruction to set the destination side as a memory is continued. The operation instruction code (add) is input from the slot C1 in cycle T5 to the instruction decoder DEC.

  The operation instruction code reads the destination side data from the read data buffer RDB to the bus GB instead of the general-purpose register in slot C1 of cycle T6 in accordance with the instruction (MODD) for setting the destination side as a memory, and performs arithmetic logic operation. Input to the ALU. Since the general-purpose register is implicitly designated on the source side, the contents of the general-purpose register R1 are read to the bus DB and input to the arithmetic logic unit ALU. In slot C2 of cycle T6, the operation result is stored in temporary register TRD. Further, the MOV. An instruction code (mov-st: 16'b0111_1000_1 ?????????) similar to WR0, @ ER0 is generated in CHG and input from slot C1 in cycle T6 to the instruction decoder DEC. The bits may be arbitrary.

  The generated instruction code (mov-st) performs the same operation as the transfer instruction using the temporary register TRA as an address register and the temporary register TRD as a data register. In other words, in slot C2 of cycle T6, the effective address stored in the temporary register TRA is read to the bus GB, output to the internal address bus IAB via the address buffer AB, and a word data write bus command is issued. . In slot C2 of cycle T7, the operation result stored in the temporary register TRD is read to the bus DB, output to the internal data bus IDB via the write data buffer WDB, and the operation result is output to the destination memory address. Write. An instruction is fetched from the slot C2 in cycle T7 and the program counter PC is incremented. As a result, the execution of the transfer instruction code (mov-1) is shortened, and the amount of instruction fetch and increment of the program counter PC is recovered.

  When writing to the destination-side memory, the instruction code (mov-st) is generated inside the CPU 2, whereby the instruction code can be shortened and the processing time can be shortened. By referring to the contents of the temporary register TRA, it is not necessary to calculate the effective address again, and the processing time can be further reduced. MOV. By using an instruction code similar to WR0, @ ER0, design can be facilitated and an increase in logical scale can be suppressed.

  In the case of a comparison instruction, there is no need to write to the destination memory. In this case as well, the operation may be performed in the same manner as described above, and only the bus command in the slot C2 in cycle T6 is changed to no operation. That is, when the instruction code of the comparison instruction is executed, a control signal is issued so that the instruction code for writing to the destination-side memory is prohibited from performing a write operation. A common control method can be used to suppress an increase in logical scale. Alternatively, the instruction code generated internally may correspond to the instruction code of a no-operation (NOP) instruction. In this case, the processing time can be further shortened.

  In addition, the same instruction extension prefix instruction code and transfer instruction code are used for the operation instructions (addition, subtraction, multiplication, division, comparison, logical product, logical sum, exclusive logical sum, etc.) for the other two data. By adding, it is possible to realize the operation of the memory and general-purpose registers. In addition, for arithmetic instructions (sign inversion, logic inversion, shift, rotate, etc.) for one data, the same instruction expansion pre-instruction code and transfer instruction code are added to realize the operation of data on the memory. it can.

  Even in the execution of the instruction described with reference to FIG. 34, the control of the change of the condition code register CCR by the operation result in the middle of the execution of the operation instruction and the control of the interrupt suppression by the control signal mskint are performed in the same manner as described above. .

  FIG. 35 shows the execution timing of a memory / memory type addition instruction (ADD.W @ ER1, @aa: 16). That is, the instruction extension prefix instruction code (pf), MOV. Instruction code (mov-1) corresponding to W @ ER1, R0, MOV. W @aa: 16, an instruction code (mov2) corresponding to R0, and ADD. The timing when an instruction regarded as one instruction is executed by combining instruction codes (add) corresponding to W R0 and R1 is shown.

  In the case of FIG. 35, the pre-instruction code for instruction extension is H'010C according to FIG. 15, and the MODS and MODD signals indicate that both the source side and the destination side are memories.

  The transfer instruction code (mov-1) reads the memory from the slot C2 of cycle T3, and generates an effective address (memory) based on an instruction (MODS) that uses the instruction side for instruction expansion as the source side as a memory. Address) is stored in the temporary register TRA. Further, in the slot C1 of the cycle T5, the read data (data1) is output to the bus GB via the read data buffer RDB. The signal is output to the bus WB via the arithmetic logic unit ALU, and stored in the temporary register TRD in the slot C2 of the cycle T5. The instruction to store the source side and the destination side as memory is continued and the end of the source side data is instructed (MODSE).

  As in the case of the transfer instruction code of FIG. 34, the transfer instruction code (mov-2) reads the memory from the slot C2 in cycle T6, and designates the destination side by the instruction extension pre-instruction code as the memory ( The generated effective address (memory address) is stored in the temporary register TRA based on (MODD) and the source data end instruction (MODSE). Further, at the time when the read data is stored in the read data buffer RDB in the slot C1 of the cycle T8, the execution is completed one state earlier than the case of reading the existing transfer instruction or the data on the source side. Continue to instruct the source side and destination side to be memory.

  The operation instruction code reads the destination side data from the read data buffer RDB to the bus GB in the slot C1 of the cycle T8 in accordance with the instruction (MODS, MODD) for setting the source side and the destination side as memories. Input to ALU. Source-side data is read from the temporary register TRD to the bus DB and input to the arithmetic logic unit ALU. In slot C2 of cycle T8, the operation result is stored in temporary register TRD. Furthermore, MOV. An instruction code (mov-st) similar to WR0, @ ER0 is generated and input to the instruction decoder DEC from the slot C1 in cycle T6.

  The generated instruction code (mov-st) performs the same operation as the transfer instruction using the temporary register TRA as an address register and the temporary register TRD as a data register.

  Here, when an instruction (MODS, MODD) for setting the memory on the source side and the destination side is made, the transfer instruction code has the MODSE signal cleared to 0 for the first time, and the data on the source side is read. It is assumed that the MODSE signal is set to 1 for the second time and the destination side is read.

  Even in the execution of the instruction described with reference to FIG. 35, the control of the change of the condition code register CCR by the operation result in the middle of the execution of the operation instruction and the control of the interrupt suppression by the control signal mskint are performed in the same manner as described above. .

  FIG. 36 shows the execution timing of a memory / memory type transfer instruction (MOV.W @ ER1, @aa: 16). That is, the instruction extension prefix instruction code, MOV. Instruction code corresponding to W @ ER1, R0, MOV. A timing when an instruction regarded as one instruction is executed by combining instruction codes corresponding to W R0, @ aa: 16 is shown. The pre-instruction code for instruction expansion at this time is H'0108 according to FIG.

  The transfer instruction between the memory and the memory is the same as the addition instruction, and ADD. Instead of instruction codes corresponding to W R0 and R1, MOV. It can also be realized using instruction codes corresponding to W R0 and R1. In this case, reading on the destination side is performed, but due to the nature of the transfer instruction, reading on the destination side is not necessary, and processing time is wasted.

  In this example, the instruction extension pre-instruction code, the read type transfer instruction code, and the write type transfer instruction code are combined, and the instruction extension pre-instruction code indicates that the source side is a memory.

  The read type transfer instruction code reads the memory and stores the read data in the temporary register TRD based on the instruction of the pre-instruction code for instruction expansion. Continue the instruction to use the source side as memory.

  The write type transfer instruction code writes the memory as in the case of the existing transfer instruction, but takes out the write data from the temporary register TRD instead of the general-purpose register according to the instruction (MODS) for setting the source side as the memory.

  The operation instruction code can be omitted as compared with the case where an implementation method equivalent to the addition instruction is adopted. As a result, the instruction code length can be shortened by one word, and the number of execution states can be shortened by three states.

  FIG. 37 shows the execution timing of the immediate-memory type addition instruction (ADD.W #xx, @aa: 16). As shown in FIG. 34, the contents of FIG. W @aa: 16, an instruction code corresponding to R0, and ADD. The timing when an instruction that is defined as a combination of instruction codes corresponding to W # xx, R0 and regarded as one instruction is executed is shown. Although the destination side is a memory, in the case of immediate data, the read data is temporarily stored in the temporary register TRD. For this reason, the pre-instruction code for instruction expansion is set to H′0108 according to FIG. 15, and a control signal (MODS) using the source side as a memory is issued.

  In the operation of the instruction extension prefix instruction code and the transfer instruction code, the read data is read from the read data buffer RDB to the bus GB in the slot C1 of the cycle T6. The signal is output to the bus WB via the arithmetic logic unit ALU and stored in the temporary register TRD in the slot C2 of the cycle T6.

  In response to the instruction extension instruction instruction (MODS), the immediate data operation instruction code is the slot C1 in cycle T8, and the destination side data is transferred from the temporary register TRD to the bus GB instead of the general-purpose register. Read and input to arithmetic logic unit ALU. On the source side, immediate data is read from the read data buffer RDB to the internal bus DB and input to the arithmetic logic unit ALU. In slot C2 of cycle T8, the operation result is stored in temporary register TRD. Further, based on the instruction extension instruction code instruction (MODS), word size write is started from slot C2 of cycle T6. The address is read from the temporary register TRA in the slot C2 of the cycle T6 and output to the internal address bus IAB via the bus GB and the address buffer AB. The data is read from the temporary register TRD in the slot C1 of the cycle T8, and is output to the internal data bus IDB via the bus DB and the write data buffer WDB. In accordance with the instruction extension instruction instruction instruction (MODS), a write operation is added to the immediate data operation instruction.

  ADD. In the case of W # xx, @ aa: 16, the operation instruction code is 2 words, which is different from FIG. 34. However, in the case of byte-size immediate, if the operation instruction code is 1 word, FIG. The operation timing may be the same.

  Even in the execution of the instruction described with reference to FIG. 37, the control of the change of the condition code register CCR by the operation result in the middle of the execution of the operation instruction and the control of the interrupt suppression by the control signal mskint are performed in the same manner as described above. .

  FIG. 38 shows the execution timing of the immediate memory type transfer instruction (MOV.W #xx, @aa: 16). That is, the instruction extension prefix instruction code, MOV. W #xx, an instruction code corresponding to R0, and MOV. Timing is indicated when an instruction that is regarded as one instruction is executed by combining an instruction code (write transfer instruction code) corresponding to WR0, @ aa: 16. At this time, the pre-instruction code for instruction expansion is set to H′0104 according to FIG.

  In the slot C1 of the cycle T4 in FIG. 38, the immediate data is read from the read data buffer RDB to the bus DB, and is output to the bus WB in the slot C2 of the cycle T4 via the arithmetic logic unit ALU. The immediate data is stored in the temporary register TRD based on the instruction (MODD) of the instruction extension prefix instruction code.

  The write type transfer instruction code writes the memory in the same way as the existing transfer instruction. However, in slot C2 of cycle T7, the write data is not a general-purpose register according to the instruction extension instruction code instruction (MODD). , Taken out from the temporary register TRD.

  Setting immediate data in a memory including an internal I / O register is considered to have a relatively high appearance frequency. Therefore, it is desirable to reduce the instruction code length and the processing time.

  FIG. 39 to FIG. 41 show another example of the logical description regarding a part of the decoding logic 201 of the operation instruction code (exe) included in the instruction decoder DEC. The logical description shown in the figure corresponds to an add instruction (ADD.W #xx: 16, Rn) having a word size of 16-bit immediate data.

  In response to the MODS signal, the execution state is extended and a write operation is inserted. The state code TMG is generated in the first part (4-1) of the logical description shown in FIG. As a single instruction, the state code TMG proceeds from 1 to 3. When calculating the immediate data and the data on the memory, MODS = 1, and the state code TMG proceeds from 1 → 17 → 3.

  Bus control is performed in the second part (4-2) of the logical description shown in FIG. When MODS = 0, two instruction reads are performed. When MODS = 1, data write is performed with state code 1 and instruction read is performed with state codes 17 and 3. The data size is the word size that is the data size of the instruction (ADD.W #xx: 16, Rn) generated by the operation instruction code.

  The effective address is calculated in the third part (4-3) of the logical description shown in FIG. When MODS = 1, the effective address held in the temporary register TRA is output to the internal bus GB with the state code 1.

  The fourth part (4-4) of the logical description shown in FIG. 40 controls the transfer data. An operation is performed with state code 1. When MODS = 0, data is read from the general-purpose register and read data buffer RDB, and the operation result is stored in the general-purpose register. When MODS = 1, data is read from the temporary register TRD and the read data buffer RDB, and the operation result is stored in the temporary register TRD.

  In the fifth part (5) of the logical description shown in FIG. 41, all control signals are initialized. Interrupts are also permitted, and if an interrupt is requested, interrupt exception handling can be continued.

  Here, a description will be given of a compound instruction that can be expanded in the same manner as described above even if the pre-instruction code for instruction expansion is omitted. For example, the MOV. If the instruction code of W # xx, R0 has a margin and can have destination information indicating whether it is a transfer to a memory or a transfer to a general-purpose register, it is not necessary to provide a pre-instruction code for instruction extension. In short, there is a substantial free area in the instruction code, and even if information on whether the transfer to the memory or the transfer to the general-purpose register is incorporated in the free area, it can be distinguished from other instruction codes. Based on such destination information, immediate data may be stored in the temporary register TRD and a control signal for generating the destination side as a memory may be generated. If a composite instruction that can be executed as a single instruction by combining the transfer instruction code with the destination information and the operation instruction code is adopted, the same function as the case of providing a pre-instruction code for instruction expansion is provided. Further, the instruction code length can be shortened and the instruction execution time can be shortened by the amount that the pre-instruction code for instruction expansion is not provided.

  52 shows an instruction extension prefix instruction code, MOV. The timing when an instruction regarded as one instruction is executed by combining the instruction code corresponding to W #xx, R0 with the instruction code added with the destination information is shown. As is clear from comparison with FIG. 38, there is no processing for the pre-instruction code for instruction expansion (pf = H′0104).

  FIG. 42 shows an outline of a CPU development environment according to the present invention. The user of the development environment creates a program in C language or assembly language using various editors. This is usually created by dividing it into a plurality of modules.

  The C compiler 400 inputs each C language source program created by the user and outputs an assembly language source program or an object module.

  The assembler 401 inputs an assembly language source program and outputs an object module.

  The linkage editor 402 inputs a plurality of object modules generated by the C compiler 400 and the assembler 401, resolves external references and relative addresses of each module, combines them into one program, and loads a load module. Output.

  The load module is input to the simulator debugger 403 and can simulate the operation of the CPU 2 on a system development device such as a personal computer, display the execution result, and analyze and evaluate the program. Further, the load module is input to the emulator 404 and performs so-called in-circuit emulation that operates on an actual application system or the like, so that the actual operation of the entire microcomputer having the CPU 2 can be analyzed and evaluated.

  In addition, a general subroutine can be provided as a librarian.

  FIG. 43 shows a CPU selection method in the system development apparatus for CPU 2 according to the present invention.

  Here, a case where the maximum mode of the upper CPU 2 is selected is illustrated. In the case of (a), “SET CPU = CPU-UMAX” may be input while a prompt is displayed on a display on a system development apparatus such as a personal computer. In the case of (b), in the state where the prompt is displayed, a command “SET CPU” is input, and in response to this, a menu of the CPU type and operation mode is displayed, for example, “CPU NAME (1. CPU-UMAX). 2. CPU-UMIN, 3. CPU-L1, 4.CPUL2) "and requesting the input of the menu number so that the user can input any of menu numbers 1-4. To do. Here, CPU-UMAX indicates the maximum mode of the upper CPU 2, CPU-UMIN indicates the minimum mode of the upper CPU, CPU-L1 indicates the first lower CPU, and CPUL2 indicates the second lower CPU. .

  In addition, it may be made selectable from a window drop-down menu, or it can be input as a C shell command for a workstation or the like.

  Further, the CPU type and operation mode may be input as a control instruction of the source program such as the assembler 401 or the C compiler 400.

  The assembler 401 interprets the description in the input assembly language source program in accordance with the selected CPU type and operation mode, and generates an object module or displays it if there is an error. If a lower CPU is selected and an instruction that exists in the upper CPU and does not exist in the lower CPU is described, an error occurs. Because the instruction code itself is included in the upper CPU, an assembler for this purpose is developed, and the lower CPU is added to detect an instruction that exists in the upper CPU and does not exist in the lower CPU. Easy to develop.

  The C compiler 400 discriminates instructions, general-purpose registers, and address spaces indicated by combinations of operations, data sizes, and addressing modes according to the selected CPU type and operation mode, and executes a program in C language. Are converted into CPU instructions and output as assembly language programs or object modules.

  The C compiler 400 itself includes a step of optimizing the analysis of the program itself when converting a C language program into a CPU instruction, and a step of realizing the result with the CPU instruction. In addition, functions that are not directly related to the instruction set of the CPU, such as compiling a program in the C ++ language and optimization between modules, have been improved. However, individual compilers for each CPU depend on these CPUs. Unenhanced enhancements must be applied to all individual compilers. If a common C compiler including CPUs that are not compatible with each other as in the present invention is used, it is easy to improve functions that are not directly related to the instruction set of the CPU, and development efficiency is improved. Etc. can be improved.

  The simulator debugger 403 interprets the input load module program, simulates the operation of the CPU, and displays any errors in the simulation. For example, if a lower CPU is selected and an instruction that exists in the upper CPU and does not exist in the lower CPU is described, an error occurs. Since the instruction code and instruction execution function itself are included in the upper CPU, a simulator debugger is developed for this purpose, and the lower CPU is added to detect an instruction that exists in the upper CPU and does not exist in the lower CPU. Can be easily developed.

  FIG. 44 illustrates a list output by the assembler of the CPU 2 of the present invention. The list displays the line number, location counter, object code, source line number, and source statement.

  In the program shown in FIG. 44 (a), the CPU-UMAX, that is, the maximum mode of the host CPU is designated by the control instruction (.CPU). Note that an instruction starting with “.” On the source program is a control instruction, and is not directly related to the microcomputer program.

  SP represents ER7. This is a function notation as a stack pointer. Furthermore, in the present invention, as shown in FIG. 5, R0L may be expressed as AL and ER1 may be expressed as EBX. Whichever notation is used, it is not an error and is converted into the same object code.

  Further, since a label such as STACK cannot be resolved only by this program, the corresponding field on the object code is set to 0. These are solved by the linkage editor as described above.

  The program shown in FIG. 44 (b) shows an example in which the same program is assembled by designating the first lower CPU (CPU-L1). The first lower CPU includes MOV. Since there is no L instruction, an error is displayed and no object code is generated. Since the detailed content regarding the list of FIG. 44 is not directly related to the present invention, the description is omitted.

  FIG. 45 shows an emulator for a microcomputer having the CPU 2 according to the present invention.

  The emulation processor 410 is configured by adding an emulation interface to the microcomputer portion. The microcomputer portion corresponds to, for example, the configuration of the microcomputer 1 shown in FIG.

  The connector unit 411 is attached to the target microcomputer mounting area 413 of the application system (also referred to as target system or user system) 412 instead of the single chip microcomputer. The emulation processor 410 inputs / outputs signals to / from the application system using the target system interface via the connector unit 411 and the interface cable 414.

  Although not particularly limited, a user bus 415 exists in the application system 412 and a user memory 416 can be connected. In this case, the user memory 416 is read / written according to the user strobe signal output from the emulation processor 410 and supplied via the interface cable 414.

  On the other hand, the emulation processor 410 is connected to the emulation bus 420 using the emulation interface. The emulation bus 420 includes state signals and control signals not shown. Using the emulation bus 420, information corresponding to the internal state of the application system 412 and the emulation processor 410 is output from the emulation processor 410, and various signals for emulation are sent to the emulation processor 410. Entered. An emulation mode terminal (not shown) of the emulation processor 410 is fixed to the power supply level, and the emulation mode is set inside the emulation processor 410.

  Further, an emulation memory 421, a break control circuit 422, a real-time trace circuit 423, and the like are connected to the emulation bus 420. Although the emulation memory 421 is not particularly limited, the emulation memory 421 is configured by a RAM or the like, and has an area for storing the user program and an area for storing a program for emulation. The break control circuit 422 monitors the state of control by the emulation processor 410 and the state of the emulation bus 420, and when the state reaches a preset state, inputs the emulator-dedicated interrupt, Execution of the user program by the CPU 410 (denoted as CPU 2 for convenience) is stopped, and a transition to the emulation program execution state is made (break). The real-time trace circuit 423 sequentially stores a signal indicating the read operation or write operation of the CPU 2, a signal indicating a command read operation (CPU status signal), an address and data given to the emulation bus, and a control signal.

  The emulation memory 421, the break control circuit 422, and the real-time trace circuit 423 are also connected to the control bus 424, and are controlled by the control processor 425 via the control bus 424. The control bus 424 is connected to the control processor 425 and is connected to a system development device 427 such as the personal computer through the host interface circuit 426, although not particularly limited.

  For example, when the program (load module) input from the system development device 427 is transferred to the user program storage area of the emulation memory 421 and the CPU 2 reads the program to be placed on the built-in ROM, the program on the emulation memory 421 is read. Is read and executed. In addition, a break condition, a real-time trace condition, and the like can be given from the system development device 427.

  The control processor 425 stores a program for selecting the type of CPU originally used in the application system 412 in the emulation program storage area of the emulation memory 421. The CPU 2 executes such a program in a state where the program is broken under a predetermined condition, and performs setting necessary for emulation by setting the control register 449 in the emulation interface 442. In this case, it is convenient to enable writing only in the execution mode of the emulation program, so-called break mode. It is possible to prevent erroneous setting due to malfunction of the software of the user who is still developing. Further, by using the control register, even if the number of CPU types to be originally used in the application system 412 increases, it is only necessary to change the configuration of the control register, and there is no need to change the emulation interface. There is no need to change the hardware of the emulator.

  By making the emulation processor 410 and the emulator support a plurality of CPUs, it is only necessary to develop an actual microcomputer, and the development efficiency can be improved.

  In the emulator as well, the CPU type can be selected. The selection method may be performed on a system development apparatus such as a personal computer as in FIG. The selected content is stored as a predetermined program in the emulation program storage area of the emulation memory 421 via the control processor 425, and the CPU 2 executes the program and sets the control register in the emulation interface. Then, the selection is performed.

  At this time, the operation mode of the single chip microcomputer may be specified at the same time. The operation mode of the single-chip microcomputer includes, for example, a single-chip mode, a built-in ROM valid expansion mode, a built-in ROM invalid expansion mode, and the like, which can be designated in combination with the operation mode of the CPU 2. Further, the display method of the general-purpose register may be selected together. When disassembling on the trace list or the like, it is switched whether to display ER0 or EAX.

  By making it possible to specify the type of CPU that is originally used in the application system 412, it is possible to specify many types of singles using combinations of built-in function modules and built-in memory capacity using the same emulation processor or the same emulator. A chip microcomputer can be emulated. Even after the development of an emulation processor or emulator, if it can be realized with a combination of built-in functions, only a single-chip microcomputer that matches the trend of the application field can be developed without developing the emulation processor or emulator. Can continue. Development efficiency can be improved.

  Since the cost of the emulation processor occupying the emulator is small, it is only necessary to incorporate as many function modules as possible in the emulation processor.

  FIG. 46 illustrates a trace list by an emulator for the CPU according to the present invention.

  The trace list includes a line number (BP), an address bus (AB), a data bus (DB), an address decode (MA), a read / write (R / W), a status (ST), and an interrupt signal (NMI, IRQ). A list of executed instructions in assembly language is displayed. This is analyzed by the data bus state and a CPU instruction execution state signal (not shown) and displayed by the disassembler. The line number is 0 at the end of the trace list. The address decode (MA) ROM indicates access to the built-in ROM, the read / write (R / W) R indicates a read cycle, and the status (ST) PRG indicates an instruction.

  Further, the LIR and LID signals shown in (a) are trace results of the instruction analysis signal included in the emulation interface. Normally, such a signal is not displayed on the trace list, but is stored in the trace memory and used for analysis of a disassembler or the like. Also, it can be displayed to the user by a command that is not normally disclosed.

  The LIR signal indicates that the bus cycle is an instruction read. The LID signal indicates the start of instruction execution.

  For example, the 200th line indicates that the instruction is read from address 100 and the instruction code H′7A07 is read. 199, 198 and MOV. L # FFFFFF0E: 32 and ER7 are displayed. The disassembler determines the first word of the instruction using the LID signal, and replaces H′7A07FFFFFF0E with the MOV. L # FFFFFF0E: 32, ER7 is interpreted and displayed.

  When the lower CPU is emulated, the disassembler displays an undefined instruction when it executes an instruction that the upper CPU has but the lower CPU does not have. When displaying as an undefined instruction, an instruction code is displayed as data.

  In FIG. 46, the instruction code corresponding to “MOV.L ER0, @ ER1” of the upper CPU is read from the address 200 on the 80th and 79th lines, and the undefined instruction ( DATA.L H'01006990) is shown as an example.

  FIG. 47 is a block diagram of a microcomputer emulation processor to which the present invention is applied.

  The emulation processor 410 includes the part (microcomputer core 441) of the single chip microcomputer 1 of FIG. 2 are represented as I / O, and details of the internal bus and the bus controller are shown. The timers 6 and 7 and the input / output ports 11 to 19 in FIG. 2 are represented as I / O 443 and user buffer (user BUF) 444. Also, in FIG. Details of IAB, PDB, and PAB and a bus controller (BSC) 445 are shown. The user interface 446 is a generic name for an interface circuit connected to a user system (a target system that is an emulation target system) including the I / O 443, the user buffer 444, an input / output buffer (not shown), and the like.

  The microcomputer core 441 has an undefined instruction detection circuit 448 added to the microcomputer 1 of FIG. The emulation interface 440 includes a control register 449. The control register 449 can be written only in the break mode. Signals input and output from the emulation interface 440 include a bus status signal indicating the bus status such as an address bus, a data bus, a read signal, a write signal, a data size signal, and an instruction fetch signal, a signal indicating the start of instruction execution, and an interrupt It includes a CPU status signal indicating the execution state of the CPU 2 such as a signal indicating the start of processing execution, etc., and is used for operation analysis of the microcomputer by the emulator.

  The undefined instruction detection circuit 448 analyzes the instruction code input to the CPU 2 and, when detecting that the instruction that does not exist in the selected CPU 2 has started execution, requests the CPU 2 to make a break interrupt. Which function is selected for the CPU 2 is instructed from the control register 449. For example, when the first lower CPU is selected, when a prefix instruction code having a register group field is executed, it is detected as an undefined instruction. Specifically, if the instruction code is latched with the LIR signal, analyzed, and decoded as undefined, it is easy to request a break interrupt when the LID signal is generated. .

  As described above, the emulation processor 410 incorporates the upper CPU 2 (CPU-U), and uses this to act as a substitute for the first lower CPU and the second lower CPU having a subset function. As a result, it is not necessary for the lower CPU to have a function for emulation, so that development efficiency can be improved, and the lower CPU does not need to include a logic circuit for emulation, and the logical scale can be reduced. The host CPU 2 also has the undefined instruction detection circuit 448 as an independent function block, so that it is not necessary to change the CPU 2 and development efficiency is not impaired.

  In any case, if the emulation interface is made common, even if the CPU or other functional blocks are changed, there is no need to change the hardware on the emulator side, and only the emulation processor 410 is changed. Thus, it is only necessary to indicate which CPU is targeted for the disassembler when analyzing and displaying the operation of the instruction. The instruction to the disassembler can be designated by the user from the system development device, or can be automatically selected by input information from the assembler. This improves emulator development efficiency and provides an emulator development environment quickly.

  FIG. 48 shows another programming model of the second lower CPU. In this programming model, the total number of bits of the general-purpose registers is the same, but only four general-purpose registers are used. The function of the general register is the same as described above. As in FIG. 5, R0, R1, R2, and R3 can be expressed as AX, BX, CX, DX, and the like. The PC is equivalent to 24 bits. Although not shown, long word size data including direct registers and immediate data is not handled. By configuring the general-purpose register to have a 16-bit configuration, the configuration of the effective part of the CPU, such as the arithmetic logic unit ALU, can be configured to have a 16-bit configuration, excluding the program counter PC and the incrementer, and the logical scale can be further reduced.

  FIG. 49 shows another example of the CPU address map. The address map of the second lower CPU has a 16 MB address space corresponding to the maximum mode. At the time of data access, an effective address is generated with 16 bits, and 0 to H'7FFF and H'FF8000 to H'FFFFFF are designated. Accordingly, the RAM and internal I / O registers can be specified up to 32 kB, and the ROM can be specified up to 32 kB. As described above, the capacity of 32 kB including the RAM and the internal I / O register is sufficient for a single-chip microcomputer or a microcomputer system that operates only with a built-in functional module.

  Although the ROM addresses that can be specified at the time of data access are limited, as described above, the constants assigned to the ROM can be rearranged by inter-module optimization even when described by a C compiler or the like.

  The program counter PC has a 24-bit configuration. When an instruction is read, an address is generated with 24 bits and a 16 MB address space can be used. For branch instructions, program counter relative and memory indirect or absolute address 24 bits may be executed. Since a branch instruction does not have a register field, it is possible to have an instruction address of 2 words and an absolute address of 24 bits. The 16 MB address space can be used continuously without any software load.

  Further, the vector for exception processing is 24 bits (32 bits on the memory and the upper 8 bits are ignored), and the program counter PC saved / restored in a subroutine branch or the like is also 24 bits.

  On the other hand, the quasi-maximum mode is also added to the upper CPU so that the operation equivalent to that of the second lower CPU having an address map corresponding to the maximum mode can be performed.

  50 and 51 exemplify the effective address calculation method in the address map of the second lower CPU shown in FIG.

  The method for calculating the effective address is almost the same as in FIGS. 7 and 8, but at the time of data access, the effective address is calculated with 16 bits, and the upper 8 bits are sign-extended to 0 to H'7FFF. And H'FF8000 to H'FFFFFF are designated.

  The program counter relative is used for a branch instruction and is calculated with 24 bits as described above. Although not shown in the figure, when a memory indirect or 24-bit absolute address can be used for a branch instruction, the effective address is calculated with 24 bits.

  In the quasi-maximum mode of the upper CPU, the address map of the second lower CPU is set in FIG. Actually, the effective address calculation itself is the same as in FIG. 7 and FIG. 8, and the post-increment / pre-decrement register indirect writing to the general-purpose register E is suppressed, and when the effective address is used, the upper 8 The bits may be sign extended. Regardless of the individual addressing mode, unified control is possible and the logical scale can be reduced. On the other hand, since only the general-purpose register R is used for calculation of the effective address because of the specification, the general-purpose register E can be used for data, which effectively increases the number of general-purpose registers.

  In the case of the second lower CPU, the number of general-purpose registers is limited as compared with the upper CPU, so that the merit of substantially increasing the general-purpose registers without reducing the program address space is relatively large.

  By providing the upper CPU 2 together with the first lower CPU and the second lower CPU described above, the following operational effects are obtained.

  [1-1] A plurality of CPUs having different instruction sets can respond to various demands of application fields or users with respective unique characteristics while reducing the logical scale.

  [1-2] By including the register configuration of the lower CPU, the instruction set, and the instruction execution function of the lower CPU, the program developed for the lower CPU can be used by the upper CPU at least at the source program level. Thus, at least, upward compatibility at the source program level can be realized.

  [1-3] By preparing in advance an operation mode for switching the number of bits of a valid address and the unit size of a vector and a stack, upward compatibility at the object program level can be easily realized.

  [1-4] The first and second lower CPUs are provided by providing upper CPUs that realize upward compatibility at the source program level or the object program level for both the first and second lower CPUs. The development efficiency can be improved as compared with the development of each upward compatible CPU. Furthermore, even when the function or performance is improved, if the compatibility with the upper CPU is maintained, the upper compatibility can be maintained with respect to the first and second lower CPUs, so that the future expandability can be maintained. Also, development efficiency can be improved. For example, if the upper CPU can be speeded up by making the internal data bus 32 bits or the like, it is possible to enjoy the speedup while effectively using the software assets of the first and second lower CPUs.

  [1-5] A CPU that is upwardly compatible with the first lower CPU and is backward compatible with the upper CPU by sharing the internal configuration, or a CPU that is further backward compatible with the second lower CPU, etc. It is possible to easily provide various compatible CPUs.

  [1-6] By developing the second lower CPU by using the instruction set of the second lower CPU as a subset of the upper CPU and deleting the logic circuit corresponding to the deleted instruction set from the upper CPU. Development efficiency can be improved.

  [1-7] A part of the instruction set added by the upper CPU is inherited by the second lower CPU with respect to the first lower CPU, thereby allowing the first and second lower CPUs to communicate with each other. It is possible to respond to various requests as a whole by using an instruction set that is not included.

  [1-8] By realizing upward compatibility at the source program level or the object program level, software assets can be used effectively, and the software development efficiency of the user can be improved.

  [1-9] Software development costs can be reduced by making it possible to commonly use software development apparatuses including a plurality of CPUs having different instruction sets and providing means for selecting CPUs. In addition, since the assembler and the like need only be developed for the upper CPU and detect undefined instructions for the other CPUs, the development efficiency of the software development apparatus can be improved. By improving the development efficiency, it is possible to reduce the resources required for development and increase the frequency of function improvement with the reduced resources.

  [1-10] A software development apparatus and a description format in an assembly language can be commonly used by the first and second lower CPUs, and software assets can be ported between the first and second lower CPUs. It can be made relatively easy. By using any one of the lower CPUs, the cost does not increase as much as the higher CPU is migrated.

  [1-11] By making it possible to use a plurality of general-purpose register descriptions having only general-purpose functions on the software development apparatus, porting of programs from other CPUs can be performed relatively easily.

  [1-12] By sharing the emulation interface of the emulation processor corresponding to a plurality of CPUs, the hardware of the same emulator can be shared. By making the emulation interface common and the emulator hardware common, the development environment can be quickly prepared, and the resources necessary for emulator development can be minimized.

  [1-13] Having emulation logic for the upper CPU, and by using the emulation logic for the upper CPU, the emulation processors of the first and second lower CPUs can be configured. Efficiency can be improved.

  According to the host CPU 2 described above, the following operational effects are obtained.

  [2-1] A register group is specified by a register extension prefix instruction code, the register extension prefix instruction code can be omitted, and an instruction code when no register extension prefix instruction code is added By using the same instruction code as that of an existing CPU, the number of general-purpose registers can be increased without losing compatibility. Software assets can be used effectively, usability can be improved, and processing speed can be improved. By using the register extension pre-instruction code, all general purpose registers can be specified at the same time, so it is not necessary to consider the arrangement of data on the general purpose registers and the creation of the program can be facilitated.

  [2-2] By placing the group designation field before the existing instruction code, the number of general-purpose registers can be increased for all instructions using the general-purpose registers. By making this designation method common, an increase in necessary logical and physical scales can be suppressed, and an increase in manufacturing cost can also be suppressed. Since most of the existing logic can be shared, design assets can be used effectively to improve design quality and shorten development time. In addition, when there is a CPU with a wide address space and a CPU with a narrow address space that maintain compatibility, it is possible to add general-purpose resters to both while maintaining compatibility.

  [2-3] The operation code map is enabled by making the operation code corresponding to the one specifying an existing register group in the lower CPU (pre-instruction code for register expansion) the same as the NOP (no operation) instruction. In addition, the logical configuration can be shared and the increase in logical scale can be suppressed.

  [2-4] By providing a margin in the group designation field, it is possible to increase the number of general-purpose registers while maintaining compatibility in accordance with the progress of the semiconductor manufacturing process. Usability can be further improved and processing speed can be improved. Development efficiency can be improved because the method can be the same. In addition, it is possible to improve development efficiency by designing software tools such as an assembler, a C compiler, a simulator, and a disassembler in consideration of the extension, or by corresponding to the extension in advance. it can.

  [2-5] By providing a control register such as CPUCR and specifying a group such as a stack pointer that is used implicitly, the stack pointer can be changed, and stack relocation can be easily performed. Can do. The stack pointer can also be changed for interrupt exception handling to which a register extension prefix instruction code cannot be added. Stack pointers for subroutine handling and exception handling such as interrupts can be separated. A subroutine stack area and an interrupt stack area can be provided separately. As a result, it is not necessary for each task realized by a subroutine branch or the like to secure a stack in order to cope with an unexpected interrupt exception process, and the amount of use of the stack can be suppressed.

  [2-6] The upper CPU executes the transfer instruction code and the operation instruction code existing in the first lower CPU in combination with the instruction instruction prefix instruction code to execute as one instruction. Since the operation is performed, existing instruction execution is not hindered. Also, existing software assets created using the first lower CPU and using only existing instructions can be used as they are. In other words, it is possible to perform direct computation on data in the memory without impairing compatibility with the first lower CPU. In addition to operations between the memory and the register, it is possible to directly transfer data between the memories. Software resources can be used effectively, and undesired general-purpose register saving / restoring operations can be suppressed to improve usability, program capacity can be reduced, and processing speed can be improved. By reducing the program capacity, it is possible to reduce the memory capacity of the ROM for storing the program, thereby saving costs.

  [2-7] Since the instruction code of the transfer instruction and the instruction code of the operation instruction existing in the first lower CPU are combined with the instruction code for instruction expansion, the conventional design assets of the instruction decoder are reduced. It can be used effectively, minimizing logical scale additions and changes, and minimizing logical and physical scale increases. In addition, the time required for development can be shortened and resources can be saved. Since all of the existing addressing modes for data access can be supported, any addressing mode can be combined to facilitate the creation of a program.

  [2-8] Since the instruction code to be added to the instruction set of the first lower CPU can be stopped at the pre-instruction code for register extension and instruction extension, the instruction of the upper CPU 2 can be minimized with minimal change of the instruction set. A set can be configured.

  [2-9] When the destination is a memory, the effective address at the time of reading the destination data is secured in the temporary register, the calculation of the effective address at the time of writing the destination data of the operation result is not required, and the write is immediately performed. The operation can be executed, and the execution time can be shortened. In addition, the instruction code for writing the destination data is automatically generated inside the CPU, the instruction length is shortened, and the instruction code is instructed to save the necessary instruction code. By making the instruction code similar to the operation of the transfer instruction, the design can be facilitated and the logic scale of the control circuit can be reduced. For instructions that do not require a destination data write operation, such as a comparison instruction, the write cycle is made empty so that the operation can be shared with other instructions, making the design easier, and the logic scale of the control circuit Can be reduced. By facilitating the design, the development period can be shortened.

  [2-10] Transfer between the memory and the memory can be realized by combining the front instruction code for instruction extension, the instruction code of the transfer instruction for reading the memory, and the instruction code of the transfer instruction for the memory.

  [2-11] By combining the instruction code of the immediate data transfer instruction and the instruction code of the transfer instruction for the memory, transfer between the immediate memories can be realized.

  [2-12] By including other information in the pre-instruction code for instruction expansion, the instruction code length can be shortened and the execution time can be shortened. For example, in an existing CPU, when there is an instruction implemented by combining a prefix instruction code that performs an instruction other than an operation with respect to a memory and an operation code, an instruction other than the operation with respect to the memory is performed. By including it in the pre-instruction code for instruction extension to be instructed, the instruction code length can be shortened and the execution time can be shortened.

  [2-13] Since a new instruction function is realized by combining existing instructions, the future expansion margin can be maintained at the same level as that of the existing CPU. For example, when it is possible to further expand the instruction set and further increase the speed of an existing CPU, such a technique can be used for a CPU to which the present invention is applied. The new instruction function can be realized by combining the above-described technique with an existing instruction that implements a new instruction function.

  According to the second lower CPU described above, the following operational effects are obtained.

  [3-1] In the second lower CPU, the address space and the program counter are made the same as those of the upper CPU, the capacity of the program is increased, and the data transfer addressing mode is set so that relatively small data can be handled. By reducing the size or limiting the data size of the transfer data, the logical scale of the CPU can be reduced without impairing usability in a desired application field.

  [3-2] The logical scale can be further reduced by reducing the address space that can be used during data access. In addition, by dividing the address space that can be used during data access into two, the compatibility of the address space with the upper CPU is maintained without impairing the usability, and the effective address calculation method is switched to the upper CPU. By preparing the mode in advance, software compatibility can be maintained.

  [3-3] By making the address space for the program as large as the upper CPU, the suitability for programming using a high-level language such as C language can be improved. In addition, by making the stack pointer switchable, an undesired increase in the capacity of the stack during task management such as an OS can be suppressed.

  [3-4] The effective address for data access is calculated with a bit length (16 bits) shorter than the bit length corresponding to the address space, and sign-extended to obtain the effective address. (General purpose register E) can be used as a data register, and the number of general purpose registers can be substantially increased.

  Although specific examples of the invention relating to the means for solving the problems A to C have been described, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the scope of the invention.

  For example, the target CPU is not limited to the upper CPU and the first and second lower CPUs. There may be a CPU that is upwardly compatible with the first lower CPU and is backward compatible with the upper CPU. Alternatively, a lower compatible CPU may exist in the second lower CPU. The two embodiments of the second lower CPU are not exclusive and may exist simultaneously. In addition, various compatible CPUs can be provided.

  The register configuration (programming model), that is, the number of bits of the general-purpose register or the number of registers can be arbitrarily selected. Various changes can be made to the addressing mode and the effective address calculation method. The specific logic circuit example of the CPU is not limited. The EA1 code or the like may not be exactly the same as the transfer instruction code. It is sufficient to perform an equivalent operation at least in the execution inside the CPU. The meaning of some bits of the transfer instruction code can be changed according to the prefix code to obtain an EA1 code. The general-purpose registers need not be commonly used for addresses and data, and some or all of them may be dedicated for addresses or data.

  The type of prefix instruction code is not particularly limited. The pre-instruction code for instruction extension may include other control information other than information for combining the transfer instruction and the operation instruction and information for combining the transfer instruction and the transfer instruction. For example, information indicating the data size may be included. Also, it is not necessary to limit the basic unit of the instruction code to 16 bits, and any bit width such as 8 bits or 32 bits can be used. For the instruction code combination, the instruction extension prefix instruction code, the first read type transfer instruction code, the second read type transfer instruction code, the operation instruction code, and the write type transfer instruction code are combined. Data of two different addresses can be input and operated, and the result can be stored in another memory address designated by the write type transfer instruction code. The first and second read type transfer instruction codes can be omitted and the data on the general-purpose register can be used as input. A combination of the pre-instruction code for instruction expansion, the first read type transfer instruction code, and the second read type transfer instruction code, and the data read by the first read type transfer instruction code is used as the second read type transfer instruction. It can also be used for code address calculation.

  In addition, only the group 0 general-purpose registers may be used for operation instructions for data on the memory. There are no restrictions on the other functional blocks of the single-chip microcomputer.

<< Embodiment Regarding Solution to Study Problem D >>
Next, a specific example of the invention relating to the means for solving the examination problem D will be described. The microcomputer described here has a CPU 2A exemplified in FIG. 53, although not particularly limited. The module configuration of the microcomputer is not particularly limited, but is the same as that shown in FIG. The CPU 2A has the register configuration of FIG. 3, the address space of the CPU 2A is the same as that of FIG. 6, and the effective address calculation method by the CPU 2A is as shown in FIGS. The machine language instruction format of the CPU 2A conforms to FIG.

  FIG. 54 illustrates an instruction format of the bit test instruction of the CPU 2A. The bit test instruction inspects a predetermined bit of data on the general-purpose register or address space, and reflects the inspection result in the Z flag of the CCR.

  In the bit test instruction, the data on the general-purpose register is designated directly by the register as illustrated in (5) of FIG. The bit test instruction at this time is an instruction code having an operation feed (op), a register field (r), and a bit field (n) for specifying a bit number.

  In the bit test instruction, the designation of data on the pan address space is as follows: absolute address 8 bits, 16 bits, 32 bits, as exemplified in (1), (2), (3), (4) of FIG. , And register indirection can be used. That is, in the case of an absolute address, it has a word having an operation field (op) and an EA extension (EA), and in the case of register indirect, it has a word having an operation feed (op) and a register field (r). It has an instruction format followed by a word corresponding to a register direct bit test instruction.

  55 to 57 show a conditional branch for a predetermined bit of data on the address space as an instruction format of a composite instruction that reads data from the address space of the CPU 2A and performs processing according to the state of the predetermined bit of the data. Indicates the instruction format of an instruction (bit conditional branch instruction). The instruction format shown here is an example different from an example described later using an instruction extension prefix instruction code. In a single conditional branch instruction, the condition code field (cc) specifies a branch condition. In a bit condition branch instruction in which a branch instruction is incorporated as a composite instruction, the branch condition is specified in the bit condition field (bc).

  As shown in FIGS. 55 to 57, the designation of data on the address space can use absolute address 8 bits, 16 bits, 32 bits, and register indirect. This is not completely identical to the instruction code (word) for data designation in the case of the bit test instruction, but has a common code. That is, the instruction code for specifying data is a data transfer instruction such as a “MOVE instruction”, for example. One or more surplus bits exist in the instruction code, and appropriate information is set in the surplus bits. However, it can be distinguished from other instruction codes on the instruction set. Such an instruction code for designating data loads data referenced in the memory space into a register not released in the program, for example, the temporary data register TRD.

  The instruction code for data designation is followed by a word corresponding to a conditional branch instruction or a subroutine branch instruction instead of an instruction word corresponding to the bit test instruction directly in the register. For specifying the branch address, a displacement 8-bit, 16-bit program counter relative can be used. This is an instruction code common to existing conditional branch instructions, and the condition field (cc) is a bit condition field (bc). Further, the subroutine branch can use only the displacement 16-bit program counter relative.

  In the CPU having a small address space or a low-order CPU, if there is no absolute address of 32 bits in the bit test instruction, it is only necessary to have a combination in a possible range.

  In the bit condition field (bc), the lower 3 bits bc [2: 0] specify the bit number of the temporary data register TRD, and the upper 1 bit bc [3] specifies a branch condition (set / clear). That is, the bit number for the data that is referred to in the address space by the first instruction code of the bit conditional branch instruction and loaded into the temporary data register TRD is designated by the lower 3 bits bc [2: 0], and the designated bit The upper value 1 bit bc [3] designates the true value (True) of the number value, and when the reference value is the true value, the branch value is instructed.

  According to the bit conditional branch instruction as the compound instruction in FIGS. 55 to 57, the instruction that branches when the bit n of the address aa is set to 1 may be described as BBS #n, @aa, d. An instruction that branches when the bit n of the address aa is cleared to 0 may be described as BBC #n, @aa, d, and when the bit n of the address aa is set to 1, the subroutine branches An instruction to be executed may be described as BSSR #n, @aa, d, and an instruction for branching a branch when bit n of address aa is cleared to 0 should be described as BCSR #n, @aa, d. Good. As described above, n = bc [2: 0]. For the displacement d, a label may be described in the assembly language, and the relative value is calculated by the assembler.

In a CPU that does not support the bit conditional branch instruction, for example, BBS #n, @aa, d
BTST #n, @aa
BNE d
As described above, it is necessary to describe a bit test instruction (BTST) and an instruction (BNT) that branches according to the execution result of the instruction. BSSR #n, @aa, d is, for example,
BTST #n, @aa
BEQ NEXT
BSR d
NEXT:
As described above, it is necessary to describe a bit test instruction (BTST), an instruction (BEQ) that branches according to the execution result of the instruction, and a subroutine branch instruction (BSR) by PC relative. The same applies when a bit transfer instruction (BLD) and an instruction (BCS or BCC) branching according to the execution result of the instruction are used instead of the bit test instruction.

  In the bit conditional branch instruction shown in FIG. 55 to FIG. 57, the data referred to in the address space is loaded into the temporary data register TRD instead of the general-purpose register, and branching is controlled according to the value of the predetermined bit. Can do. Therefore, the instruction code can be shortened by one word and the number of execution states can be shortened by one state. In the bit condition subroutine branch instruction, the instruction code can be shortened to 2 words and the number of execution states can be shortened to 3 states.

  As described above, in the case of device control, these conditional branch instructions are combined (configured in a tree shape), and branch destinations are often determined from a large number of branch conditions. In reality, it becomes even larger.

  FIG. 58 illustrates combinations of instruction codes in another instruction format when a bit conditional branch instruction in the CPU 2A is considered. The example shown here is an example in which the function based on the instructions in the instruction format described with reference to FIGS. 55 to 57 is realized by using the instruction instruction prefix instruction code. That is, the instruction code used to specify data in the address space is the same as the instruction code (word) for specifying data in the case of the bit test instruction, and a prefix instruction code is added as a prefix code before that word. By doing so, the composite instruction can be executed as a single instruction using the temporary data register TRD or the like as described above.

  58 is combined with FIG. 12 to FIG. 14, the instruction code in the instruction format of the direct operation instruction combined with the front instruction code for instruction extension and the transfer instruction explained based on FIG. 11 to FIG. It is expressed including the combination of. The instruction format of the transfer instruction example for the memory of the CPU 2A is the same as the instruction format described with reference to FIG.

  In the instruction format of FIG. 58, the bit condition branch instruction is realized by combining the instruction extension prefix instruction code, the EA1 code, and the branch code. In the figure, the EA2 code can be combined with the EA2 code. However, the EA2 code means a code having a memory address as a destination address.

  In the instruction format of FIG. 58, a bit test instruction as a compound instruction can be realized by combining a pre-instruction code for instruction expansion, an EA1 code, and a bit test instruction code. The bit test instruction code at this time is a bit test instruction for a desired bit on the general-purpose register, that is, an instruction code corresponding to the register direct addressing mode in (5) of FIG. In addition, when an operation instruction for a desired bit and carry is provided, it can be realized in the same manner as the bit test instruction. In the figure, a combination with the EA2 code is also possible, but in the same way as described above, there is no actual meaning.

  In the instruction format of FIG. 58, the function of the bit set instruction can be expanded. A single bit set instruction is an instruction to set a designated bit of designated data. In the instruction format of FIG. 58, a bit set instruction as a compound instruction is a combination of an instruction extension prefix instruction code, an EA2 code, and a bit test instruction code. The bit set instruction code at this time is an instruction code corresponding to a bit set instruction for a desired bit on the general-purpose register, as described above. In the figure, a combination with the EA1 code is also possible, but the EA1 code means a code having a memory address as a source address, and therefore has no meaning in practice.

  The format of the instruction extension prefix instruction code (control code) in the CPU 2A is the same as the format described with reference to FIG. According to this format, the source side and the destination side have bits indicating information indicating the memory. For bit conditional branch instructions and bit manipulation instructions, specify that the source side is memory. Since the transfer instruction codes of EA1 and EA2 are the same, if the source side is a memory, the one following the instruction extension prefix instruction code is determined to be EA1 regardless of the destination side. On the other hand, if the source side is a general-purpose register and the destination side is a memory, it is determined as EA2. As described with reference to FIGS. 55 to 57, the temporary data register TRD is used to exchange data between instruction codes when the instruction format shown in FIG. 58 is executed as one instruction. It is.

  By the combination of instruction codes according to FIG. 58, an addressing mode equivalent to a transfer instruction can be used to designate an address where a desired bit exists. Since any addressing mode can be used in the instruction set, programming can be facilitated. For example, by adding register indirect with displacement and indirect pre-decrement / post-increment register to existing CPUs that have only register direct, register indirect and absolute address, manipulate bits that exist in multiple addresses. Or the number of program steps can be reduced or the processing speed can be improved. At this time, the existing instruction code of the transfer instruction and the instruction code of the bit manipulation instruction operate in combination, so that the conventional design assets of the instruction decoder can be effectively used, and the logical scale is added. Minimize changes and minimize the increase in logical and physical scale.

  As for the bit conditional branch instruction, the format shown in FIGS. 55 to 57 and the format shown in FIG. 58 can be arranged. For instructions (a combination of data and branch destination addressing modes) that can achieve equivalent functions in both, the instruction code length and the execution state number that are shorter may be employed.

  FIG. 53 shows a detailed example of the CPU 2A. Although not shown in particular in the CPU 2 in FIG. 1, the value of the condition field (cc) is input to the condition code register CCR, and the value of a predetermined bit in the condition code register CCR matches the value of the condition field (cc). A determination circuit (CMP) 35 for determining whether or not to perform is provided, and a branch control logic (BRC) 37 for generating a branch control signal 36 in response to the determination result is provided.

  In the bit conditional branch instruction as the compound instruction described in the instruction format of FIGS. 55 to 58, the value of the bit condition field (bc) is input to the temporary data register TRD, and the value of the bit position specified thereby is branched. A determination circuit (CMP) 38 for determining whether or not the conditions are met is provided, and the determination result is supplied to the branch control logic 37. The branch control logic 37 validates the input from the determination circuit 35 or the determination circuit 38 according to the logical value of the control signal MODS. That is, when executing a bit conditional branch instruction as a compound instruction and referring to data from the address space, the instruction decoder DEC sets MODS = 1, and when MODS = 1, the temporary register write signal TRDwr is enabled, and the general-purpose register Instead, reference data is written to temporary data register TRD. The instruction decoder DEC sets MODS = 0 when the instruction is other than the above compound instruction. When MODS = 0, the general-purpose register write signal Rdwr is validated, and the CCR flag is manipulated according to the operation result written to the general-purpose register. The branch control logic 37 adopts information output from the determination circuit 38 of the temporary data register TRD when MODS = 1, and performs branch control accordingly. When MODS = 0, the branch control circuit 37 performs branch control by using information output from the determination circuit 35 of the condition code register CCR.

  When the interrupt control unit INTC executes a plurality of instruction codes (words having an operation field) as a series as shown in FIGS. 55 to 58, each instruction code indicates an interrupt mask. The execution of the predetermined combination of instruction codes is not interrupted.

  The arithmetic operator AU is used to generate a branch address for a branch instruction / subroutine branch instruction relative to the program counter. Specifically, the output of the program counter PC used for the previous instruction read is input, and the displacement held in the read data buffer RDB is input, and these are added. At the start of execution of an 8-bit displacement program counter relative branch instruction / subroutine branch instruction, a branch address is obtained.

  The incrementer INC is used to increment the program counter PC. As described above, in the bit conditional branch instruction, the temporary data register TRD and the determination circuit 38 are used.

  In addition, circuit blocks having the same functions as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 59 illustrates the logical configuration of the determination circuit 38 of the temporary data register TRD and the branch control logic 37 by a logical description.

  In the part (5-1) of FIG. 59, the bit condition field (bc) is any one of bits 11 to 8 and bits 7 to 4 of the instruction code according to the instruction code. The result selected by the control signal bcc1 is defined as an internal signal bc1. In the internal signal bc1, the most significant bit bc1 [3] designates a bit state (set / clear), and the lower bit bc1 [2: 0] designates a bit number.

  In the portion (5-2) in FIG. 59, a desired bit of TRD is selected (trdsel) by the selector based on bc1 [2: 0].

  In the part (5-3) of FIG. 59, when bc [3] = 0, the selected bit is inverted, and when bc [3] = 1, the selected bit is output as it is. (Bout). This is the determination result of the bit condition.

  In the part (5-4) of FIG. 59, the determination result (cout) of the condition code CCR of the existing conditional branch instruction and the output (bout) are selected by the MODS signal, and the result of branch / non-branch is obtained. Bcout. When the result is 1, the branch is established, and when the result is 0, the branch is not established. Although not particularly limited, it is set to 1 when the branch condition determination signal (logical sum of bcc1 and bcc2) is not active.

  60 to 62 show the logical configuration of the instruction decoder DEC for the bit test instruction and a part of the bit conditional branch instruction (first word) by the logical description. In the logic description of the decoder DEC, lowercase signals are signals generated and output by the instruction decoder DEC, and uppercase signals are signals input to the instruction decoder DEC. The logical description in FIG. 6 illustrates a case where data reading is performed with an 8-bit absolute address and the read data is stored in the temporary data register TRD.

  The state code TMG is generated at the portion (6-1) in FIG. The state code TMG proceeds from 1 to 2. When NEXTTMG [5] = 0, the next TMG is NEXTTMG [4: 0]. When NEXTTMG [5] = 1, the next TMG is set to 5'b00001.

  In the second part (6-2) of FIG. 60, bus control is performed. When nop = 0, the bus access is started, and when nop = 1, the bus access is prohibited. Data = 0 indicates an instruction read, and data = 1 indicates a data access. long = 1 indicates a long word size, and when long = 0, byte = 0 indicates a word size, and byte = 1 indicates a byte size. Write = 0 indicates read, and write = 1 indicates write. In the case of instruction read, the contents of the bus IDB are stored in IR1 and the read data buffer RDB at a predetermined timing. In the case of data read, the contents of the bus IDB are stored in the read data buffer RDB at a predetermined timing. In the case of data write, the contents of the write data buffer WDB are output to the bus IDB at a predetermined timing. In the case of this instruction, data access is performed with state code 1, and data access read and byte access are instructed. Instruction read is performed with state code 2.

  The effective address is calculated at (6-3) in FIG. In the case of this transfer instruction, with the state code 1 and dbragb = 1, the EA extension part 8 bits of the instruction code held in the DBRA is expanded by 1 to 32 bits (all the upper 24 bits are set to 1). Output to the internal bus GB. The contents of GB are stored in the address buffer AB every state, and no control is required.

  The transfer data is controlled at (6-4) in FIG. In state code 2, dbrdb = 1 is set, read data is output from DBR to DB, and wbtrd = 1 is set via the arithmetic logic unit ALU and stored in the temporary data register TRD.

  The interrupt mask signal is controlled at (6-5) in FIG. Further, the control signal MODS is generated.

  63 to 65 show a logical configuration of the instruction decoder DEC for a part of the conditional branch instruction by a logical description. This logical description corresponds to an 8-bit displacement conditional branch instruction (Bcc d: 8).

  In the part (7-1) of FIG. 63, the state code TMG is generated. The state code TMG proceeds from 1 to 2. Bus control is performed at (7-2) in FIG. In the case of this instruction, instruction reading is performed using state codes 1 and 2, and in state code 1, instruction reading of a branch address is performed based on the branch address calculated by the arithmetic unit AU. As will be described later, it is determined whether or not to branch before the completion of reading. If the branch is not branched, the read instruction is not fetched. In state code 2, according to the determination result, instruction read of the next address of the branch address or the next address of the branch instruction is performed.

  The effective address is calculated at (7-3) in FIG. In state code 1, augb = 1 is set, and the result of the arithmetic operator AU (the effective address of the branch address) is output to the internal bus GB. Also, bcc1 = 1 is set and branch determination is instructed. The actual determination is made according to the contents of the condition code register CCR when MODS = 0 and according to the contents of the temporary data register TRD when MODS = 1. Note that bcc1 and bcc2 are different in the bit position of the instruction code used as the condition field (cc / bc). In the case of bcc1, bits 11 to 8 are used, and in the case of bcc2, bits 7 to 4 are used.

  The transfer data is controlled in the portion (7-4) in FIG. 64, but no operation is performed by this command. In the part (7-5) in FIG. 64, all control signals are initialized. Interrupts are also permitted, and if an interrupt is requested, interrupt exception handling can be continued.

  66 to 68 show the logical configuration of the instruction decoder DEC for a part of the subroutine branch instruction by the logical description. This logical description corresponds to a 16-bit displacement subroutine instruction (BSR d: 16). The MAX signal indicates the maximum mode. Actually, the stack pointer (ER7) is decremented and the output to the GB is controlled. However, the illustration is omitted because it is not directly related to the present invention.

  The operation varies depending on whether the condition is met or not. Further, the bit length of the program counter PC to be stacked differs in the maximum / minimum mode.

  The state code TMG is generated in the logic description part (8-1) in FIG. When the minimum mode condition is satisfied, the state code TMG proceeds in the order of 1 → 14 → 2 → 3. When the conditions for the maximum mode are satisfied, the state code TMG proceeds in the order of 1 → 14 → 2 → 11 → 3. If not established, the state code TMG proceeds from 1 → 14 → 3.

  Bus control is performed in the logic description part (8-2) in FIG. In the case of this instruction, instruction reading is performed with the state codes 14 and 3, and the state codes 2 and 11 perform writing to the stack. State code 1 does not perform bus access. The instruction read by the state code 14 is performed based on the branch condition determination result.

  The effective address is calculated in the logical description part (8-3) in FIG. bcc2 = 1 is set and branch determination is instructed. The actual determination is made according to the contents of the temporary data register TRD when MODS = 1. In state code 1, the 16 bits of the EA extension part of the instruction code held in the read data buffer RDB are sign-extended to 32 bits by the dbrext signal and output to the internal bus DB. Although not shown, the contents of the program counter PC are output to the internal bus GB and added by the arithmetic logic unit ALU. In state code 2, according to the determination result (BCOUT), if BCOUT = 1, output from ALU to internal bus GB is performed. Although not shown, if BCOUT = 0, output from the PC to the internal bus GB is performed.

  The transfer data is controlled by the logical description part (8-4) in FIG. 67, but no operation is performed by this instruction. In the logic description part (8-5) in FIG. 68, all control signals are initialized. Interrupts are also permitted, and if an interrupt is requested, interrupt exception handling can be continued.

  The instruction decoder DEC can control the bit conditional branch instruction by combining the logical descriptions described with reference to FIGS.

  The logical description of a part of the transfer instruction in the instruction decoder DEC is the same as the example in FIGS. The logical description of a part of the operation instruction in the instruction decoder DEC is the same as that in FIGS.

  69 and 70 illustrate logical descriptions of the logical configuration of the instruction decoder DEC for other operation instructions. This logical description corresponds to a bit test instruction (BTST #n, Rn). Similarly to the above, whether to execute as an independent bit test instruction or as part of a processing instruction for data on the memory is instructed by the MODS signal. In particular, a portion not shown (such as control of the arithmetic logic unit ALU) can be performed in the same manner as an independent bit test instruction.

  The state code TMG is generated at the logical description portion (9-1) in FIG. The state code TMG ends with 1. In the logical description portion (9-2) in FIG. The instruction read ends with state code 1.

  In the logic description part (9-3) in FIG. 70, the operation data is controlled. When MODS = 0, the data is used as a general-purpose register, and the contents of the general-purpose register are read out to the DB (rsdb). When MODS = 1, the data is used as a memory, and the contents of the temporary register TRD are read out to the DB (trdb). All the control signals are initialized in the logic description portion (9-4) in FIG. Interrupts are also permitted, and if an interrupt is requested, interrupt exception handling can be continued.

  71 and 72 exemplify the logical configuration of the instruction decoder DEC with respect to other arithmetic instructions in a logical description. This logical description corresponds to a bit set instruction (BSET #n, Rn). Similarly to the above, whether to execute as an independent bit set instruction or as a part of a processing instruction for data on the memory is instructed by the MODD signal. Parts not particularly shown (such as control of the arithmetic logic unit ALU) can be performed in the same manner as independent bit set instructions.

  The state code TMG is generated at the logic description portion (10-1) in FIG. The state code TMG ends with 1. Bus control is performed in the logical description portion (10-2) in FIG. The instruction read ends with state code 1.

  The operation data is controlled by the logic description portion (10-3) in FIG. When MODED = 0, the data is used as a general-purpose register, the contents of the general-purpose register are read to GB (rdgb), and the operation result is written to the general-purpose register (wbrd). When MODED = 1, the data is used as a memory, the contents of the read data buffer are read to the bus DB (DBRdb), and the operation result is written to the temporary data register TRD (wbtrd).

  In the logic description portion (10-4) in FIG. 72, the interrupt mask signal is controlled. When the destination side is a memory, the control signal MKMOV is generated to instruct the instruction change unit CHG to generate an instruction code that performs the same operation as the write type transfer instruction. Further, the long word size signal LNG and the byte size signal BYTE are continued.

  Next, an example of the execution timing of a compound instruction such as the bit conditional branch instruction will be described. Although not particularly limited, the internal data bus is 16 bits, and the built-in ROM and RAM can be read / written in one state. The built-in ROM and RAM use the bus IAB as an address bus and the bus IDB as a data bus. Although PAB and PDB described later are not connected, it should be understood that the same timing is generated internally.

  FIG. 73 illustrates the execution timing of the first example (BBS # 0, @FFFFFE, $ + 20) of the bit conditional branch instruction. In slot C2 of cycle T0, the address is output from the address buffer (AB) of CPU 2A to bus IAB.

  In slot C1 of cycle T1, the contents of bus IAB are output to bus PAB, and a read cycle is started. In slot C2, read data is obtained on the internal data bus, and this is latched in register IR1 in slot C1 of cycle T2. This is a word common to the first word of the bit test instruction (bld), and stores the data at the designated address in the temporary register.

  Subsequently, in slot C2 of cycle T2, the next address (+2 contents) is output to the bus IAB, and this read data is latched in register IR1 in slot C1 of cycle T3 (instruction code (bcc) of conditional branch instruction) ). The above operation is performed by controlling the execution of the previous instruction, and the relative relationship may be different.

  When the execution of the immediately preceding instruction is completed, when the execution of the instruction is started earliest, the instruction code (bld) is input to the instruction decoder DEC in the slot C1 of the cycle T2, and the content of the instruction is decoded. According to the decoding result, as described with reference to FIGS. 60 to 62, a control signal is output to control each unit. That is, since the addressing mode is an 8-bit absolute address, the source data is read based on the absolute address, and the read result is stored in the temporary register TRD. The control signal MODS = 1.

  In slot C2 of cycle T2, the contents (absolute address) of the read data buffer RDB are read to the internal bus GB and input to the address buffer AB. An address is output from address buffer AB to address bus IAB.

  Data is read from cycle T3. In slot C2 of cycle T3, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. The arithmetic operator AU receives the contents of the bus GB and calculates a branch address from the slot C1 in the cycle T4.

  The read data is stored in the read data buffer RDB in the slot C1 of the cycle T4. Further, the data is output from the read data buffer RDB to the internal bus DB and input to the arithmetic logic unit ALU. The arithmetic logic unit ALU is not operated.

  In slot C2 of cycle T4, the read data is output from the arithmetic logic unit ALU to the internal bus WB and stored in the temporary data register TRD.

  In slot C1 of cycle T4, an instruction code (conditional branch instruction (bcc)) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the decoding result, as described with reference to FIGS. 63 to 65, a control signal is output to control each unit. Since the MODS signal is set to 1, a test is performed on a predetermined bit of the temporary data register TRD, not the condition code register CCR.

  In slot C2 of cycle T4, as described above, the contents of the branch address calculated by the arithmetic operator AU are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB.

  In slot C1 of cycle T5, the result incremented (+2) by the incrementer INC is written to the temporary register TRA via the internal bus WB. A branch condition test is directed.

  In slot C2 of cycle T5, the contents of temporary address register TRA are read to internal bus GB when the branch condition is satisfied, and the contents of program counter PC when the branch condition is not satisfied, and address buffer AB and incrementer are read. Input to INC. An address is output from address buffer AB to address bus IAB. As a result, the address of the next instruction code is switched.

  On the other hand, if the branch condition is satisfied in slot C1 of cycle T6, the contents of bus IDB are latched in register IR1 (branch destination instruction code). If not, the contents of the register IR1 are retained and the instruction code next to the bit conditional branch instruction is saved. As a result, the next instruction code is switched.

  Note that a continuous instruction signal (mskint) is output so that the first word and the second word and thereafter are not divided. Even if an interrupt request or the like is generated, the execution of the instruction can be continued by this signal.

  FIG. 74 shows the execution timing of an example of a bit condition subroutine branch instruction (BBSR # 5, @ FFFE00, $ + 300).

  In slot C1 of cycle T2, the instruction code (bld-1) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. That is, since the addressing mode is a 16-bit absolute address, after reading the absolute address as the EA extension unit, the source data is read based on the absolute address, and the read result is stored in the temporary data register TRD. . The control signal MODS = 1.

  In slot C2 of cycle T1, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. A read cycle is started from the cycle T2, and this read data is latched in the read data buffer RDB in the slot C1 of the cycle T3 (absolute address (bld-2) which is an EA extension unit).

  In slot C2 of cycle T2, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. From cycle T3, a read cycle is started, and this read data is latched in the read data buffer RDB in slot C1 of cycle T4 (subroutine branch instruction (bsr-1)).

  In slot C2 of cycle T3, the contents (absolute address) of the read data buffer RDB are read to the internal bus GB and input to the address buffer AB. An address is output from address buffer AB to address bus IAB. Data is read from the cycle T4, and the read data is stored in the read data buffer RDB in the slot C1 of the cycle T6. Further, the data is output from the read data buffer RDB to the internal bus DB and input to the arithmetic logic unit ALU. The arithmetic logic unit ALU is not operated.

  In slot C2 of cycle T6, the read data is output from the arithmetic logic unit ALU to the internal bus WB and stored in the temporary data register TRD.

  In slot C1 of cycle T5, the instruction code (subroutine branch instruction (bsr-1)) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the decoding result, as described based on FIG. 66 to FIG. 68 based on 8, a control signal is output to control each part. Since the MODS signal is set to 1, a predetermined bit of the temporary register TRD is tested.

  In cycle T5, a branch condition test is instructed. In state C1 of cycle T6, the contents of the program counter PC are read to the internal bus GB and the contents (displacement) of the read data buffer RDB are read to the internal bus DB, respectively, and the addition is performed by the arithmetic logic unit ALU. In slot C2 of cycle T6, when the branch condition is satisfied, the contents of the arithmetic logic unit ALU are read to the internal bus GB when the branch condition is not satisfied, and the contents of the address buffer AB and the increment are read out. Input to the INC. An address is output from address buffer AB to address bus IAB. As a result, the address of the next instruction code is switched. In slot C1 of cycle T7, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB.

  The contents of the stack pointer SP (ER7) are read to the internal bus GB at the slot C1 in the cycle T7, and decremented by the arithmetic logic unit ALU (4 is subtracted in the maximum mode and 2 is subtracted in the minimum mode). In slot C2 of cycle T7, the contents of the arithmetic logic unit ALU are read to the internal bus GB and input to the address buffer AB, and the address is output from the address buffer AB to the address bus IAB. Generates a word size write bus command. In slot C2 of cycle T8, the contents of the program counter PC are output to the internal bus IDB via the internal bus DB and the write data buffer WDB. In the maximum mode, another word size write is performed. If the condition is not satisfied, this stack operation is not performed.

  If the condition is not satisfied in the slot C2 of the cycle T8, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC in the slot C2 of the cycle T8. An address is output from address buffer AB to address bus IAB. A read cycle starts from the next state.

  FIG. 75 shows the execution timing of the first example (BTST # 0, @FFFFFE) of the bit test instruction. This is the case of an existing single instruction.

  The instruction code (bld) is input to the instruction decoder DEC in the slot C1 of the cycle T2, and the contents of the instruction are decoded. According to the decoding result, as described with reference to FIGS. 60 to 62, a control signal is output to control each unit. That is, since the addressing mode is an 8-bit absolute address, the source data is read based on the absolute address, and the read result is stored in the temporary data register TRD. The control signal MODS = 1.

  In slot C2 of cycle T2, the contents (absolute address) of the read data buffer RDB are read to the internal bus GB and input to the address buffer AB. An address is output from address buffer AB to address bus IAB.

  Data is read from cycle T3. In slot C2 of cycle T3, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. The arithmetic operator AU receives the contents of the bus GB and calculates a branch address from the slot C1 in the cycle T4.

  The read data is stored in the read data buffer DBR in slot C1 of cycle T4. Further, the data is output from the read data buffer DBR to the internal bus DB and input to the arithmetic logic unit ALU. The arithmetic logic unit ALU is not operated.

  In slot C2 of cycle T4, the read data is output from the arithmetic logic unit ALU to the internal bus WB and stored in the temporary data register TRD.

  In slot C1 of cycle T4, an instruction code (bit test instruction (btst)) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since the MODS signal is set to 1, data is read from the temporary data register TRD instead of the general-purpose register.

  In slot C2 of cycle T4, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. The address IAB is output from the address buffer AB. In slot C1 of cycle T5, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB.

  In slot C1 of cycle T5, data is output from the temporary register TRD to the internal bus GB according to the MODS signal and input to the arithmetic logic unit ALU. Select the specified bit.

  In slot C2 of cycle T7, the bit test result is stored in the Z flag of the condition code register CCR. When the selected bit is 0, Z = 1, and when it is 1, Z = 0.

  FIG. 76 shows the execution timing of the second example (BTST # 1, @ ER0 +) of the bit test instruction. This is an example in which the addressing mode is extended. Prefix instruction code, MOV. The instruction code corresponding to B @ ER0 +, R0 and the instruction code corresponding to BTST # 1, R0H are executed in combination. The prefix instruction code is H'0108 according to FIG. 15, and the MODS signal indicates that the source side is a memory.

  The transfer instruction code reads the memory as in the case of the existing transfer instruction, but stores the read data in the temporary data register TRD based on the instruction to set the source side as the memory by the prefix instruction code. Continue the instruction to use the source side as memory. The operation instruction code reads the source-side data from the temporary data register TRD instead of the general-purpose register in accordance with an instruction to set the source side as a memory. Other operations are the same as those of the existing operation instruction.

  In slot C1 of cycle T2, the instruction code (prefix instruction code pf) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. In the case of such a prefix instruction code, it indicates that the source side data exists on the memory. That is, the MODS signal is set to 1 as the control signal controlC and fed back to the instruction decoder DEC.

  In slot C2 of cycle T2, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. Read the next instruction.

  An instruction code (MOV instruction (mov)) is input to the instruction decoder DEC in the slot C1 of the cycle T3, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since this is the post-increment register indirect addressing mode, the source data is read based on the address register ER0, and the read result is stored in the temporary data register TRD.

  In slot C1 of cycle T3, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. In slot C2 of cycle T3, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB.

  From cycle T3, a read cycle is started, and this read data is latched in read data buffer RDB in slot C1 of cycle T4 (bit test instruction (btst)). The result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB.

  In slot C2 of cycle T4, the contents (EA) of the address register ER0 are read to the internal bus GB and input to the address buffer AB. An address is output from address buffer AB to address bus IAB. In the slot C1 of the cycle T5, the contents (EA) of the address register ER0 are read again to the internal bus GB and input to the arithmetic logic unit ALU to perform increment processing. This result is stored in the address register ER0 in slot C2 of cycle T5.

  Data is read from cycle T5. The read data is stored in the read data buffer RDB in the slot C1 of the cycle T6. Further, the data is output from the read data buffer RDB to the internal bus DB and input to the arithmetic logic unit ALU. The arithmetic logic unit ALU is not operated. In slot C2 of cycle T6, the read data is output from the arithmetic logic unit ALU to the internal bus WB, and the MODS signal is set to 1. Therefore, the read data is stored not in the general-purpose register but in the temporary data register TRD.

  In slot C2 of cycle T5, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. Read the next instruction.

  In slot C1 of cycle T6, the instruction code (BTST instruction (btst)) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since the MODS signal is set to 1, data is read from the temporary data register TRD instead of the general-purpose register.

  In slot C2 of cycle T6, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. In slot C1 of cycle T7, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB.

  In slot C1 of cycle T7, data is output from the temporary data register TRD to the internal bus GB according to the MODS signal and input to the arithmetic and logic unit ALU. The specified bit is selected.

  In slot C2 of cycle T7, the bit test result is stored in the Z flag of the condition code register CCR. When the selected bit is 0, Z = 1, and when it is 1, Z = 0.

  FIG. 77 shows the execution timing of an example of a bit set instruction (BSET # 2, @ ER0 +). This is an example in which the addressing mode is extended. Prefix instruction code, MOV. The instruction code corresponding to B @ ER0 +, R0 and the instruction code corresponding to BSET # 2, R0H are executed in combination. The prefix instruction code is H'0104 according to FIG. 15, and the MODD signal indicates that the destination side is a memory.

  Similar to the existing transfer instruction, the transfer instruction code reads the memory from the slot C2 in cycle T4, and generates an effective address (MODD) based on the instruction (MODD) for setting the destination side as the memory by the prefix instruction code. Memory address) is stored in the temporary address register TRA. Further, at the time when the read data is stored in the read data buffer DBR in the slot C1 of the cycle T6, the execution is completed one state earlier than the case of reading the existing transfer instruction or the data on the source side. For this reason, instruction fetch and program counter PC are not incremented. The instruction to set the destination side as a memory is continued. The bit set instruction code (bset) is input to the instruction decoder DEC from the slot C1 in cycle T5.

  The operation instruction code reads the destination side data from the read data buffer DBR to the bus GB instead of the general-purpose register in slot C1 of cycle T6 in accordance with the instruction (MODD) for setting the destination side as a memory, and performs arithmetic logic operation. Input to the ALU. In slot C2 of cycle T6, the bit set result is stored in temporary data register TRD. Furthermore, MOV. An instruction code (mov-st) similar to WR0, @ ER0 is generated and input to the instruction decoder DEC from C1 in cycle T6.

  The generated instruction code (mov-st) performs the same operation as the transfer instruction using the temporary address register TRA as the address register and the temporary data register TRD as the data register. That is, in slot C2 of cycle T6, the effective address stored in the temporary register TRA is read to the bus GB, output to the bus 7IAB via the address buffer AB, and a bus command for byte data write is issued. In slot C2 of cycle T7, the operation result stored in the temporary data register TRD is read to the bus DB, output to the bus IDB via the write data buffer, and the operation result is written to the memory address of the destination. . An instruction is fetched from the slot C2 in cycle T7 and the program counter PC is incremented. As a result, the execution of the transfer instruction code (mov-1) is shortened, and the amount of instruction fetch and program counter PC increment is not recovered.

  When writing to the destination memory, the instruction code (mov-st) is generated inside the CPU 2A, whereby the instruction code can be shortened and the processing time can be shortened. By referring to the contents of the temporary register TRA, it is not necessary to calculate the effective address again, and the processing time can be further reduced. MOV. By using an instruction code similar to WR0, @ ER0, design can be facilitated and an increase in logical scale can be suppressed.

  FIG. 78 shows the execution timing of the second example (BBC # 0, @ ER0 +, $ + 20) of the bit conditional branch instruction.

  Prefix instruction code, MOV. The instruction code corresponding to B @ ER0 +, R0 and the instruction code corresponding to BRA $ + 20 are executed in combination. The prefix instruction code is H'0108 according to FIG. 15, and the MODS signal indicates that the source side is a memory. The transfer instruction code reads the memory as in the case of the existing transfer instruction, but stores the read data in the temporary data register TRD based on the instruction to set the source side as the memory by the prefix instruction code. Continue the instruction to use the source side as memory.

  In slot C1 of cycle T3, an instruction code (conditional branch instruction (bcc)) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since the post-increment register indirect addressing mode is used, the source data is read based on the address register ER0, and the read result is stored in the temporary register TRD.

  In slot C1 of cycle T3, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. In slot C2 of cycle T3, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB.

  From cycle T3, a read cycle is started, and this read data is latched in the read data buffer RDB in slot C1 of cycle T4 (conditional branch instruction (bcc)). The result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB.

  In slot C2 of cycle T4, the contents (EA) of the address register ER0 are read to the internal bus GB and input to the address buffer AB. An address is output from address buffer AB to address bus IAB. In the slot C1 of the cycle T5, the contents (EA) of the address register ER0 are read again to the internal bus GB and input to the arithmetic logic unit ALU to perform increment processing. This result is stored in the address register ER0 in slot C2 of cycle T5.

  Data is read from cycle T5. The read data is stored in the read data buffer RDB in the slot C1 of the cycle T6. Further, the data is output from the read data buffer RDB to the internal bus DB and input to the arithmetic logic unit ALU. The arithmetic logic unit ALU is not operated. In slot C2 of cycle T6, the read data is output from the arithmetic logic unit ALU to the internal bus WB, and the MODS signal is set to 1. Therefore, the read data is stored not in the general-purpose register but in the temporary data register TRD.

  In slot C2 of cycle T5, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB. Read the next instruction.

  In slot C1 of cycle T6, an instruction code (conditional branch instruction (bcc)) is input to the instruction decoder DEC, and the contents of the instruction are decoded and a control signal is output in the same manner as in FIG. 74 to control each part. Do. Since the MODS signal is set to 1, a test is performed on a predetermined bit of the temporary data register TRD, not the condition code register CCR.

  In slot C2 of cycle T6, as described above, the contents of the branch address calculated by the arithmetic operator AU are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address is output from address buffer AB to address bus IAB.

  In slot C1 of cycle T8, the result incremented (+2) by the incrementer INC is written to the temporary address register TRA via the internal bus WB. A branch condition test is directed.

  In slot C2 of cycle T7, the contents of the temporary address register TRA are read to the internal bus GB when the branch condition is satisfied, and the contents of the program counter PC are read to the address bus AB and the incrementer when the branch condition is not satisfied. Input to INC. An address is output from address buffer AB to address bus IAB. As a result, the address of the next instruction code is switched.

  On the other hand, if the branch condition is satisfied in slot C1 of cycle T8, the contents of the bus IDB are latched in the instruction register IR1 (branch destination instruction code). If not, the contents of the instruction register IR1 are retained and the instruction code next to the bit conditional branch instruction is saved. As a result, the next instruction code is switched.

  An addressing mode that can be used for a transfer instruction can be used to specify an address where a bit to be tested exists in a bit test instruction, a bit condition branch instruction, and a bit condition subroutine branch instruction.

  Note that the CPU 2A realizes the execution timings of FIGS. 31 to 41 in the same manner as the CPU 2 of FIG. Further, the instruction decoder DEC of the CPU 2A realizes the control logic of the logic description illustrated in FIGS. 39 to 41 as with the PPU 2 of FIG. Further, the development environment of the CPU 2A can be configured as shown in FIG. The method described in FIG. 43 can be applied as it is to the CPU selection method in the system development apparatus at this time. Further, FIG. 44 can be exemplified as a list output by the assembler of the CPU 2A. Further, the same configuration as that shown in FIG. A microcomputer for emulating a microcomputer using the CPU 2A can be configured as described with reference to FIG.

  According to a specific embodiment of the invention relating to the means for solving the examination subject D, the following operational effects are obtained.

  [1] Since the instruction codes such as the first word and the second word (conditional branch instruction) are already existing, they operate independently as before and do not hinder the execution of existing instructions. Also, if only existing instructions are used, existing software assets can be used effectively. The advantages of existing CPUs such as general-purpose registers and load / store architecture are not impaired. If the first word and the second word (conditional branch instruction) have a plurality of types in the bit length of the absolute address, the bit length of the displacement, etc., these can be combined by the same method. In other words, all the existing addressing modes for data access and the conditional branch instruction addressing modes can be supported, so that any combination of addressing modes can be made possible. By making these combinations possible, program restrictions can be eliminated and usability can be improved. Moreover, it becomes possible to combine with a subroutine branch instruction by the same method, and usability can be improved. Combining existing independent bit test instructions and conditional branch instructions can contribute to shortening the instruction code length and improving the processing speed.

  An addressing mode equivalent to that of the transfer instruction can also be specified for an addressing mode such as a bit operation instruction such as a bit test instruction and a bit set instruction, and usability can be improved. By making it possible to specify various addressing modes, the optimum addressing mode can be selected when branching to multiple processes or setting multiple bits according to the state of multiple bits. It can be used and can contribute to the reduction of the overall program capacity and the improvement of the processing speed.

  [2] Since it operates by combining the instruction code of the existing transfer instruction and the instruction code of the operation instruction, the existing design assets of the instruction decoder can be used effectively, and the logical scale is added or changed To minimize the increase in logical and physical scale. In addition, the time required for development can be shortened and resources can be saved. A MOD signal, which is a control signal for changing the operation content of the instruction code, can be shared. That is, the instruction code for transferring data is made common, and the instruction code that follows is combined with the operation instruction code or the branch instruction code. The instruction set can be optimized to prevent an increase in logical scale.

  [3] A latch means such as a temporary register is provided with means for judging the state of a designated bit so that the state of a predetermined bit can be judged without reading it to an ALU or the like. Since it can be realized without changing the overall operation of the branch instruction, the portion to be changed can be reduced and the increase in logical scale can be minimized.

  [4] By stopping the instruction code to be added to the front instruction code, the change of the instruction set can be minimized, and can be applied to a general CPU or an instruction set. Since the prefix instruction code can be used in common regardless of the addressing mode and the content of the operation, the instruction code to be added can be minimized. Further, by providing the prefix instruction code with other information such as data size, the overall instruction code length can be shortened. By including other information in the prefix instruction code, the instruction code length can be shortened and the execution time can be shortened. For example, in an existing CPU, when there is an instruction implemented by combining a prefix instruction code that performs an instruction other than an operation with respect to a memory and an operation code, an instruction other than the operation with respect to the memory is performed. By including it in the instructed prefix instruction code, the instruction code length can be shortened and the execution time can be shortened.

  Data read from memory to latch means, operation, and write to memory based on the contents of latch means are different from existing instructions and used registers. it can. As a result, an increase in the logical scale due to the operation on the data on the memory can be minimized.

  [5] When there is a CPU with a wide address space and a CPU with a small address space while maintaining compatibility at the object level, the CPU can achieve backward compatibility by realizing the instructions with a CPU with a wide address space. Even in a CPU with a small address space, data on the memory can be operated. In other words, in the same method, while maintaining compatibility at the object level, a CPU with a wide address space and a CPU with a small address space can be operated on data in the memory. Both the advantage of maintaining compatibility at the object level and the advantage of enabling computation on data in the memory can be enjoyed.

  [6] Since a new instruction function is realized by combining existing instructions, new problems are rarely caused to the existing CPU when the instruction set is further expanded and further speeded up. In other words, if there is a technique for further expanding the instruction set or further speeding up (invented) for an existing CPU, the present invention is applied to the existing CPU. The same technique can be applied to a CPU whose instruction set is expanded. The technique may be applied to each of the existing instructions used for realizing the new instruction function and combined again. The prefix instruction code has a simple operation and can be easily changed by making the operation similar to an existing instruction.

  [7] Since the new instruction function is realized by combining the existing instructions, the existing CPU and the emulation interface can be shared, and the hardware of the same emulator can be shared. By making the emulator hardware common, the development environment can be quickly established, and the resources required for emulator development can be minimized.

  The embodiment of the invention relating to the means for solving the examination problem D is merely an example, and various modifications can be made without departing from the scope of the invention.

  For example, the instruction code to be combined is not limited to a bit test instruction or a conditional branch instruction. When considering a new instruction set, an appropriate instruction code may be appropriately combined, for example, when an existing instruction set is upwardly compatible. At least in one operation field, or in a single instruction decode, a complicated operation such as executing a bit conditional branch instruction is not performed, and the address where the bit exists is read, the bit is tested, branch determination, and branch Individual operations such as these may be shared with similar instructions.

  The addressing mode of the bit conditional branch instruction is not limited to the embodiment. The designation of the branch address is not limited to relative to the program counter, and may be an absolute address or register indirect. This may be adapted to the overall instruction set.

  The CPU architecture may not be a load store architecture. The general-purpose registers need not be commonly used for addresses and data, and some or all of them may be dedicated for addresses or data. The data size of the general-purpose register can also be set arbitrarily.

  The type of prefix instruction code is not particularly limited. The prefix instruction code may include other control information in addition to information combining the transfer instruction and the conditional branch instruction or the operation instruction. For example, information indicating the data size may be included.

  Also, it is not necessary to limit the basic unit of the instruction code to 16 bits, and any bit width such as 8 bits or 32 bits can be used. The control signal uses MODS or MODD, but can be divided into other control signals.

  Combine the prefix instruction code, first read type transfer instruction code, second read type transfer instruction code, operation instruction code, write type transfer instruction code, and input the data of two different addresses on the memory , And the result can be stored in another memory address specified by the write type transfer instruction code. The first and second read type transfer instruction codes can be omitted and the data on the general-purpose register can be used as input.

<< Embodiment Regarding Solution to Study Problem E >>
Next, a specific example of the invention related to the means for solving the examination problem E will be described. The microcomputer described here has the configuration described with reference to FIG. 2 and will not be described in detail because it is repeated. Therefore, the CPU 2 built in the microcomputer 1 has a general-purpose register and a control register as shown in FIG. Of course, CPU 2 will contain the general purpose registers and instruction set of the lower CPU having the programming model of FIG. The CPU 2 as the upper CPU has the address space shown in FIG. The method described with reference to FIGS. 7 and 8 is employed for calculating the effective address of the CPU 2.

  An example of the microcomputer described here is shown in FIG. The microcomputer 501 executes a command to control the entire microcomputer 501, a central processing unit (CPU) 502, a system controller (SYSC) 514 that controls an operation mode of a single chip microcomputer, an interrupt controller (INT) 503, a bus controller 510, a DMA controller (DMAC) 511, an external bus DMAC (EXDMAC) 512, a read only memory (ROM) 504 that is a memory for storing processing programs of the CPU 502, a work area of the CPU 502, and a temporary storage of data Random access memory (RAM) 505, timer 506, pulse output circuit 507, serial communication interface (SCI) 508, A / D converter (A / D) 509, It has functional blocks or circuit modules of output ports IOPA to IOPF, input / output ports IOP1 to IOP5, and clock oscillator (CPG) 513, and is formed on one semiconductor substrate (semiconductor chip) by a known semiconductor integrated circuit manufacturing technique. Yes.

  The CPU 502 mainly fetches instructions from the ROM 504 and decodes them to perform arithmetic operations and control operations. The DMAC 511 shares a bus with the CPU 502 and performs data transfer control on behalf of the CPU 502. The EXDMAC 512 is a transfer control device specialized for data transfer control on the external bus, and enables data transfer control on the external bus in parallel with the access operation on the internal bus of the CPU 502 or the DMAC 511. The

  The bus controller 510 has an internal bus controller, an external bus controller, a refresh timer, and the like. The internal bus controller performs bus arbitration between the CPU 502 and the DMAC 511. The external address is divided into, for example, eight areas, and the bus width and the number of access states can be set for each area in the external bus controller. During continuous access such as high-speed page mode such as DRAM or ROM, A shortened bus cycle can be realized. For example, in the case of an external DRAM, high-speed page 2-state is used for normal 4-state access. The external bus controller arbitrates for the bus right request from each of the CPU 502, the DMAC 511, and the EXDMAC 512 and the bus right request from the outside.

  The various functional blocks of the microcomputer 501 are connected to each other by an internal bus. In addition to the address bus and data bus, the internal bus is not shown, bus right request signal, bus acknowledge signal, bus command, external bus command, ready signal, external bus ready signal, read signal / write signal, bus size signal, system Includes clock signals and the like. There are IAB, PAB, and EXAB in the internal address bus. IDB and PDB exist in the internal data bus.

  These buses are interfaced by a bus controller 510. The internal buses IAB and IDB are connected to the CPU 2, DMAC 11, ROM 504, RAM 505, and bus controller 510, and the address bus IAB is connected to the input / output ports IOPA to IOPC to interface with the address bus of the external bus, and the data bus The IDB is connected to the input / output ports IOPD and IOPE in order to interface with the data bus of the external bus.

  The peripheral buses PAB and PDB are connected to the bus controller 510, EXDMAC 512, timer 506, pulse output circuit 507, SC5I8, A / D converter 509, interrupt controller 503, input / output ports IOPA to IOPF and input / output ports IOP1 to IOP5. The Control registers included in these functional blocks are collectively referred to as internal I / O registers.

  The address bus EXAB connects the EXDMAC 512, the bus controller 510, and the input / output ports IOPA to IOPC. Note that the bus controller 510 determines the address of the address bus EXAB and refers to it in order to execute an operation according to the bus specification. Therefore, the bus controller 510 only needs to input upper bits that determine the area or determine the row address of the DRAM.

  The CPU 502 and the DMAC 511 can use the internal bus as an internal bus master, and the bus controller (internal bus arbiter) 510 arbitrates in accordance with each bus right request signal. For the external bus, the bus controller (external bus arbiter) 510 arbitrates according to the external bus access by the internal bus master, EXDMAC 512, external bus right release request, and refresh request bus right request signal.

  ROM 504, RAM 505, timer 506, pulse output circuit 507, SCI 508, A / D converter 509, input / output ports IOPA to IOPF and IOP1 to IOP5, each functional block of interrupt controller 503 and EXDMAC 512 are used as internal bus slaves. Operation control information and the like can be read / written by the CPU 502 or the DMAC 511.

  The interrupt controller 503 inputs an interrupt signal output from the timer 506, the SCI 508, the A / D converter 509, and the input / output port IOP5, receives an interrupt request signal 531 in the CPU 502, and an activation request signal (not shown) in the DMAC 511. ) Is output. Also, a clear signal (not shown) output from the DMAC 511 is input, and an interrupt clear signal (not shown) is output.

  The input / output port is also used as an external bus signal and an input / output signal of the input / output circuit. The input / output ports IOPA to IOPC are also used as address bus outputs, the input / output ports IOPD and IOPE are used as data bus inputs / outputs, and the input / output port IOPF is also used as bus control signal input / output signals. External addresses and external data are connected to buses IAB and IDB via buffer circuits included in these input / output ports, respectively. The buses PAB and PDB are used for reading / writing the registers of the input / output ports, and are not directly related to the external bus. The bus control signal output includes an address strobe, a high / low data strobe, a read strobe, a write strobe, and a bus acknowledge signal. The bus control input signal includes a wait signal and a bus request signal. These input / output signals are not shown. The expansion of the external bus is selected by an operation mode or the like, and the functions of these input / output ports are also selected.

  The input / output port IOP1 is a timer input / output, the input / output port IOP2 is a pulse output, the input / output port IOP3 is an input / output of the SCI508, the input / output port IOP4 is an analog input, and the input / output port IOP5 is also used as an EXDMAC512 and DMAC511 input / output. ing. The EXDMAC 512, the DMAC 511, the timer 506, the SCI 508, the pulse output 507, the input / output signals between the A / D converter 509 and the input / output ports IOP1 to IOP5, internal interrupt request signals, and the like are not shown.

  When an interrupt factor occurs, the interrupt controller 503 determines whether the CPU 502 or the DMAC 511 makes a request, and determines the priority order. When an interrupt request is generated in the CPU 502, the CPU 502 interrupts the process being executed, branches to a predetermined processing routine through an exception processing state, performs a desired process, and clears the interrupt factor. . At the end of the predetermined processing routine, a normal return instruction (RTE instruction) is provided, and the interrupted process is resumed by executing this instruction.

  In addition to the ground level (Vss), power supply voltage level (Vcc), analog ground level (AVss), analog power supply voltage level (AVcc), and analog reference voltage (Vref) input terminals, the microcomputer 501 has power supply terminals. As dedicated control terminals, there are terminals for reset (RES), standby (STBY), mode control (MD0, MD1, MD2), and clock input (EXTAL, XTAL).

  An oscillation signal from a crystal oscillator or an external clock signal is input to the CPG 513 via the terminals EXTAL and XTAL, and a reference clock signal (system clock) φ is generated based on the oscillation signal. The microcomputer operates in synchronization with the reference clock signal φ. One cycle of the reference clock signal φ is called a state.

  When a reset signal is applied to the RES terminal, the SYSC 514 takes in the operation mode given by the mode terminals MD0 to MD2, and the microcomputer 501 enters a reset state. The operation mode set by the mode terminal is selected from single chip / expansion, address space, validity / invalidity of built-in ROM, initial value of data bus width 8 bits / 16 bits, and the like.

  When the reset is released, the CPU 502 reads a start address from a predetermined address, and performs reset exception processing to start reading an instruction from the start address. Thereafter, the CPU 502 sequentially reads and decodes instructions from the ROM 504, etc., and processes data based on the decoded contents or RAM 505, timer 506, SCI 508, input / output port, etc., or memory connected to an external bus. And data transfer with I / O. That is, the CPU 502 performs processing based on instructions stored in the ROM 504 or the like while referring to data input from the input / output port, the A / D converter 509, or instructions input from the SCI 508 or the like. Based on the result, an input / output port, a timer 506 and the like are used to output signals to the outside to control various devices.

  FIG. 3 is also a drawing showing a programming model of the host CPU 502 as a configuration example (programming model) of general-purpose registers and control registers built in the CPU 502.

  The CPU 502 has 32 general-purpose registers having a 32-bit length. The general purpose registers ER0 to ER31 all have the same function, and can be used as an address register or a data register.

  As a data register, it can be used as a 32-bit, 16-bit and 8-bit register. The address register and the 32-bit register are used as general registers ER (ER0 to ER31) at once. As 16-bit registers, the general-purpose register ER is divided and used as general-purpose registers E (E0 to E31) and general-purpose registers R (R0 to R31). These have equivalent functions, and up to 64 16-bit registers can be used. Note that the general-purpose registers E (E0 to E31) may be particularly referred to as extension registers. As an 8-bit register, the general-purpose register R is divided and used as general-purpose registers RH (R0H to R31H) and general-purpose registers RL (R0L to R31L). These have equivalent functions, and up to 64 8-bit registers can be used. The usage method can be selected independently for each register.

  The general-purpose registers ER7, ER15, ER23, and ER31 are assigned a function as a stack pointer (SP) in addition to a function as a general-purpose register, and are used implicitly in exception processing, subroutine branching, and the like. Exception handling includes the interrupt exception handling.

  In terms of the internal logical configuration, ER0 to ER7 are group 0, ER8 to ER15 are group 1, ER16 to ER23 are group 2, and ER24 to ER31 are group 3. Group 0 is the same as the general-purpose register of the existing CPU (lower CPU relative to CPU 502).

  These general-purpose registers can be used equally without any difference in programming specifications. At least, when writing in assembly language, it can be described as, for example, R0H, E8, R16, ER31, etc. without regard to the group. For example, if written according to the assembler format of “H8S / 2600 Series H8S / 2000 Series Programming Manual” published by Hitachi, Ltd. in March 1995, “MOV.L ER0, ER31” or “ADD.W E8, R16” And can be described only by register numbers.

  The CPU 502 further includes, as control registers, a 24-bit program counter PC illustrated in FIG. 3, an 8-bit extended register EXR, and an 8-bit condition code register CCR.

  The program counter PC indicates an address of an instruction to be executed next by the CPU 502. Although not particularly limited, since all the instructions of the CPU 502 are in units of 2 bytes (words), the least significant bit of the address signal instructing the byte as the minimum unit is invalid, and at the time of instruction read, the least significant bit of the instruction address is Considered zero.

  The condition code register CCR is an 8-bit register and indicates the internal state of the CPU 502. It consists of 8 bits including interrupt mask bit (I) and half carry (H), negative (N), zero (Z), overflow (V) and carry (C) flags.

  The extended register EXR is an 8-bit register and controls exception processing such as interrupts. It includes interrupt mask bits (I2 to I0) and trace (T).

  FIG. 4 is also a drawing showing a programming model of a CPU that is backward compatible with the CPU 502. The upper CPU 502 having the programming model of FIG. 3 includes general registers and instruction sets of the lower CPU having the programming model of FIG.

  A backward compatible CPU has eight 16-bit general-purpose registers. The general-purpose registers R0 to R7 all have the same function, and can be used as an address register and a data register.

  It can be used as a 16-bit and 8-bit register as a data register. The address register and 16-bit register are used as general-purpose registers R (R0 to R7) at once. As an 8-bit register, the general-purpose register R is divided and used as general-purpose registers RH (R0H to R7H) and general-purpose registers RL (R0L to R7L). These have equivalent functions, and up to 16 8-bit registers can be used. The usage of each register can be selected independently.

  As described above, the general-purpose register R7 is assigned a function as a stack pointer (SP) in addition to a function as a general-purpose register, and is used implicitly in exception processing, subroutine branching, and the like.

  FIG. 80 shows the address space of the CPU 502. As the address map of the microcomputer 501, the ROM 504 is arranged from the address 0, while the RAM 505 and the internal I / O register are arranged at both ends of the address space from the address H'FFFF or the address H'FFFFFF. .

  The host CPU 502 has a 16 MB address space maximum mode and a 64 kB address space minimum mode. The selection of the maximum mode and the minimum mode is performed according to the state of the mode control input terminals MD0 to MD2 of the microcomputer 501.

  In the maximum mode, the absolute space is 24 bits (the upper 8 bits are reserved and 32 bits in the instruction code), and the entire space is designated by 16 bits and 0 to H'7FFF and H'FF8000 to H'FFFFFF are designated. Further, the vector for exception processing is 24 bits (32 bits on the memory and the upper 8 bits are ignored), and the program counter PC saved / restored in a subroutine branch or the like is also 24 bits.

  In the minimum mode, both the absolute address and the register indirect addressing mode use only the lower 16 bits and ignore the upper bits. The vector at the time of exception processing is 16 bits, and the program counter PC saved / restored at a subroutine branch is also 16 bits.

  The lower CPU has an address space of 64 kB corresponding to the minimum mode. An absolute address has only 16 bits, and in the register indirect, a 16-bit register designates the entire space. The vector and stack structure are the same as the minimum mode of the host CPU 502, the vector during exception processing is 16 bits, and the program counter PC saved / restored at subroutine branching is also 16 bits.

  FIGS. 7 and 8 are also diagrams illustrating an effective address calculation method in the maximum mode of the host CPU 502.

  The register indirect shown in (1) of FIG. 7 includes a part (register field) for designating a register in the instruction code, and a total of 32 bits of the contents of the general-purpose register ER designated by the instruction code are stored in the memory. Specify an address. Since the address may be 24 bits, the upper 8 bits are ignored.

  The register indirect with displacement shown in (2) and (3) of FIG. 7 uses the result obtained by adding the displacement included in the instruction code to the 32-bit address obtained in the same manner as the register indirect. Specify an address in memory. The addition result is used only for address designation and is not reflected in the contents of the general-purpose register ER. Although there is no particular limitation, the displacement is 32 bits or 16 bits, and when the 16-bit displacement is added, the upper 16 bits are sign-extended. That is, the addition is performed on the assumption that the upper 16 bits of the displacement have the same value as bit 15 of the 16-bit displacement. In this case, the upper 8 bits are ignored.

  The post-increment register indirect shown in (4) of FIG. 7 designates an address on the memory with a 32-bit address obtained in the same manner as the register indirect. Thereafter, 1, 2 or 4 is added to this address, and the addition result is stored in the general-purpose register ER. 1 is added when byte data on the memory is designated, 2 is added when word data is designated, and 4 is added when address data is designated. In addition, in a multiple register transfer instruction, a result obtained by multiplying the number of registers is used. The upper 8 bits of the addition result are also stored in the extension register. In the case of a multiple general-purpose register transfer instruction to be described later, a value obtained by multiplying 2 (word size) or 4 (long word size) by the number of registers is used.

  In the pre-decrement register indirect shown in (5) of FIG. 7, the address on the memory is designated by a 24-bit address obtained by subtracting 1, 2, or 4 from the 32-bit address obtained in the same manner as the register indirect. To do. Thereafter, the subtraction result is stored in the general-purpose register ER. 1 is subtracted when byte data on the memory is designated, 2 is subtracted when word data is designated, and 4 is subtracted when address data is designated. In addition, in a multiple register transfer instruction, a result obtained by multiplying the number of registers is used. Similarly to the above, when the address may be 24 bits, the upper 8 bits of the subtraction result are also stored in the extension register, although there is no particular limitation. Similarly to (4), in the case of a later-described multiple general-purpose register transfer instruction, a value obtained by multiplying 2 (word size) or 4 (long word size) by the number of registers is used.

  The absolute addresses shown in (6), (7), and (8) of FIG. 8 designate an address on the memory by using an 8-bit, 16-bit, or 32-bit absolute address included in the instruction code as an address. In the 8-bit absolute address, the upper 16 bits are extended to a logical value 1 (one extension). That is, bits 23 to 8 of the address are all 1 bits. Therefore, usable addresses are 256 bytes of H'FFFF00 to H'FFFFFF. In the 16-bit absolute address, the upper 8 bits are sign-extended. That is, if bit 15 of the 16-bit absolute address is 0, bits 23 to 16 of the address are all 0s, and if bit 15 is 1, bits 23 to 16 of the address are all 1s. Accordingly, usable addresses are 64 kbytes of H'000000 to H'007FFF and H'FF8000 to H'FFFFFF.

  In the program counter relative shown in (9) and (10) of FIG. 8, the address on the memory is designated by using the result of adding the displacement included in the instruction code to the 24-bit address of the contents of the program counter. . The addition result is stored in the program counter. Although there is no particular limitation, the displacement is 16 bits or 8 bits, and when these displacements are added, the upper 8 bits or 16 bits are sign-extended. That is, the addition is performed assuming that the upper 8 bits of the displacement are the same as the bit 15 of the 16-bit displacement, or the upper 16 bits are the same as the bit 7 of the 8-bit displacement. Program counter relative is used only for branch instructions.

  In the minimum mode of the upper CPU 502, the upper 8 bits of the effective address are ignored and the lower 16 bits are valid. In addition to the above, addressing modes such as immediate, register direct, and memory indirect are executed, but since these are not directly related to the present invention, detailed description thereof is omitted.

  In the data transfer instruction of the backward compatible CPU having the programming model of FIG. 4, register indirect, register indirect with 16-bit displacement, post-increment / pre-decrement register indirect, and 8 / 16-bit absolute address can be used. The effective address calculation method is the same as described above.

  FIG. 81 shows the function of a multi-general register transfer instruction (MOVM) as a multi-register transfer instruction (multi-register / memory transfer instruction, multi-register / register transfer instruction). The data size can be word (W) or longword (L), and data transfer between general-purpose registers and between general-purpose registers and memories is possible. The addressing mode is the same as that of a conventional transfer instruction except for immediate.

  The general-purpose register can be selected from 2, 3, and 4. In the case of a long word size, two of ER0-ER1, ER2-ER3, ER4-ER5, ER6-ER7,. Three combinations, ER0-ER2, ER4-ER6,..., ER28-ER30, and four combinations ER0-ER3, ER4-ER7,. In the case of the word size, only the corresponding general purpose register R or only the general purpose register E is selected.

  In FIG. 81, Rns means a general-purpose register number that becomes a source, Rnd means a general-purpose register number that becomes a destination, EAs means an effective address that becomes a source, and EAd means an effective address that becomes a destination. .

  FIG. 82 shows a data arrangement of data transfer by a transfer instruction (MOVM) of a plurality of general purpose registers. (1) shows transfer between two registers of word size, between registers and memory, (2) shows transfer between two registers with word size, and (3) shows two transfers of long word size (4) shows the transfer between two registers of long word size between the register and the register.

  For example, in (3) of FIG. 82, the most significant data of the first general-purpose register ERn, for example, the upper 8 bits of En (indicated by a) is the memory (indicated by a) designated by the effective address EA. , The next data in the general-purpose register, for example, the lower 8 bits of En (indicated by b) corresponds to the memory (indicated by b) specified by the effective address EA + 1. Next to the lowest-order data of the first general-purpose register, for example, the data d of RLn, the second-most general-purpose register, for example, the highest-order data of ERn + 1, for example, the upper 8-bit data e of En + 1. In the case of the word size, although not shown, data transfer between two of En and En + 1 and two of Rm and Rm + 1 is also possible.

  FIG. 9 is also a diagram exemplifying a machine language instruction format and instruction code of the CPU 502. The instruction of the CPU 502 is in units of 2 bytes (word). Each instruction includes an operation feed (op), a register field (r, gr), an EA extension (EA), and a condition field (cc).

  The operation field (op) represents the function of the instruction, and specifies the processing contents of the specified operand in the addressing mode. The operation field (op) always includes the first 4 bits of the instruction. There may be two operation fields.

  The register fields (r, gr) are combined to specify a general purpose register. The register field (r) is 3 bits for the address register and 3 bits (32 bit register) or 4 bits (8 or 16 bit register) for the data register. There may be two register fields r1 and r2 or no register fields r1 and r2.

  There are 4 bits in the register field (gr), but the lower 2 bits are valid though not particularly limited. Words including register field (gr) (words including op, gr1, and gr2) can be omitted. If omitted, it is assumed that 0 is given, and a group 0 register set is specified. The registers specified in the register field (r) have register numbers 0 to 7, and general-purpose registers ER0 to ER can be selected. Such a word (instruction code including op, gr1, and gr2) is referred to as a register extension prefix instruction code.

  Register number n = gr [1: 0] << 3 + r [2: 0] (<< 3 indicates a 3-bit left shift). That is, a register having a number designated by 5 bits is designated, with gr being the higher order and the lower 3 bits r [2: 0] of r being the lower order. For example, when gr = 0 and r = 1, the register number n = 1, and when gr = 2 and r = 3, the register number n = 19. The register ER, the register E, the register R, the register RH, and the register RL are specified according to the portion of the general-purpose register ERn corresponding to the register number n that specifies the size of the instruction code and the content of r [3]. For example, whether the data size is a long word, a word, or a byte is specified by a predetermined bit in the operation field of the instruction code. When the data size is word or byte, the register position to be used is specified by r [3]. r [3] means bit data of the fourth bit from the lower order of r. When the data size is word, the register E is designated when r [3] = 1, and the register R is designated when r [3] = 0. When the data size is byte, r [3] = 1 designates the register RL, and when r [3] = 0, the register RH is designated.

  In addition, gr1 and r1 mean a register designation field of a source register or an address register, and gr2 and r2 mean a register designation field of a destination register or a data register. gr1 (bits 7 to 4 in the basic word of the instruction code) is replaced with r1 (bits 7 to 4 or 6 to 4 in the basic word of the instruction code) and gr2 (bits 3 to 0 in the basic word of the instruction code) Corresponds to r2 (bits 11 to 8 or bits 3 to 0 in the basic word of the instruction code).

  The EA extension (EA) designates immediate data, an absolute address or a displacement, and is 8 bits, 16 bits, or 32 bits. The condition field (cc) specifies the branch condition of the conditional branch instruction (Bcc instruction).

  The instruction code exemplified for each instruction format means a machine language expressed in hexadecimal. If the prefix instruction code (00) having the group designation fields gr1 and gr2 is omitted, an existing instruction code is obtained.

  For example, when H′0901 exemplified in (2) of FIG. W R0 and R1 are added, and when a prefix instruction code H′0012 having a group designation field illustrated in (3) of FIG. 9 is added thereto, H′00120901 becomes ADD. W R8, R17.

  Also, H'0000 that designates the group 0 that is used implicitly becomes a NOP (no operation) instruction. H'00xx (xx is 01 to FF) designates a group field, and continuously executes the next instruction code (inhibits interrupts), and increments the PC in the same manner as the NOP instruction. It is executed with the number of states.

  Since the register designation field (gr) has 4 bits, the general-purpose register group can be logically expanded to 16. In this case, 128 32-bit general registers (or 256 16-bit general registers) can be used.

  There may be a plurality of operation fields corresponding to the register designation field (gr). For example, an operation code having both a function for simply specifying a register and a function for switching other functions (such as data size) may be prepared.

  FIG. 10 is also a diagram exemplifying a machine language instruction code of a single general-purpose register data transfer instruction in the CPU 502. The calculation of the effective address of each addressing mode is in accordance with FIGS. 7 and 8, and the machine language instruction format is in accordance with FIG.

  FIG. 83 exemplifies a prefix instruction code (an instruction extension prefix instruction code) indicating an instruction such as a transfer instruction (MOVM) of a plurality of general-purpose registers. The multi-register transfer instruction is realized by combining a pre-instruction code for instruction extension and an existing transfer instruction code into a composite instruction.

  The pre-instruction code for instruction expansion is as follows. Bit 2 (third bit from the least significant) indicates the size of the register, B'0 (B 'means binary data) indicates the word size, and B'1 indicates the long word size. Bits 5 and 4 indicate the number of general-purpose registers, and B'01 is 2, B'10 is 3, and B'11 is 4. This instruction code is a new instruction code added to the instruction set of the lower CPU.

  A data transfer instruction using the pre-instruction code for instruction expansion is an instruction code of a word size such as a single general-purpose register and memory data transfer instruction (MOV) (for example, 2 words when the absolute address is 16 bits) ) To which an instruction code indicating a long word size is added (for example, a total of 3 words when the absolute address is 16 bits).

  According to FIG. 83, since the information for switching the size is held, the instruction extension prefix instruction code is added instead of the instruction code indicating the long word size of the data transfer instruction of the single general-purpose register and the memory. do it. A multi-purpose register data transfer instruction (MOVM) can be realized without increasing the instruction code length.

  The existing “STM ER0-3, @ -SP” which is a save instruction to the stack of a plurality of general-purpose registers and the “MOVM.L ER0-3, @ -SP” which is an instruction of the present invention are substantially the same. However, the order of general-purpose registers on the stack is different. In the STM instruction, data is arranged in the order of ER3, ER2, ER1, and ER0 from the top (effective address) of the stack, whereas in the MOVM instruction, in the order of ER0, ER1, ER2, and ER3 from the top of the stack. Data is placed. The processing by both of the above instructions is greatly different in the address calculation method as will be described later.

  In the case of adopting the pre-instruction code for instruction extension, there is no problem in operation even if it does not have an instruction to save to the stack, but it has both instruction codes from the viewpoint of effectively using software assets. It is desirable.

  Alternatively, if the general-purpose register read / write order in the transfer instruction of a plurality of registers is used from the one with the largest number, the instructions can be made to have the same operation. Further, the general-purpose register read / write order may be designated by an internal I / O register or the like.

  FIG. 84 shows a detailed example of the upper CPU 502. The CPU 502 includes a control unit CONT and an execution unit EXEC.

  The control unit CONT includes an instruction register IR1, an instruction register IR2, an instruction decoder DEC, a register selector RSEL, and an interrupt control unit INTC. An instruction register IR2 is added to the lower CPU, and the configuration of the register selector RSEL is different. The instruction decoder DEC is also changed corresponding to the addition of the instruction register IR2 and the change of the configuration of the register selector RSEL. In particular, the control unit CONT performs a first control according to the presence / absence of an instruction extension pre-instruction code and a second control according to the presence / absence of a register extension pre-instruction code.

  In the first control, a combination of a plurality of general-purpose registers that can be specified by an instruction is fixed, and data transfer is performed between a plurality of general-purpose registers in which the combination is fixed and a memory address in the address space or a general-purpose register. Take control that makes possible. The effective address of the transfer instruction is calculated only once by the arithmetic unit ALU, and subsequent addresses are dealt with by the increment or decrement function of the address buffer AB.

  The second control is a register designation control in consideration of upward compatibility. On the one hand, an extended general-purpose register is designated using a register instruction prefix instruction code, and on the other hand, an optional register designation field gr is designated. When (gr1, gr2) is omitted, control is performed so that register specification by the register specification field r (r1, r2) which cannot be omitted is implicitly specified as a register included in the register group 0.

  The instruction decoder DEC is configured by, for example, a micro ROM, PLA (Programmable Logic Array), or a wiring logic.

  The register selector RSEL is supplied with the output signal of the instruction decoder DEC, the output signals of the instruction registers IR1 and IR2, and the output signals ispgr and sspgr of the internal I / O register CPUCR included in the SYSC3.

  The instruction register IR1 is supplied with an instruction from the internal data bus IDB. The output of the instruction register IR1 is coupled to another instruction register IR2, the instruction decoder DEC, and the register selector RSEL. The output of the instruction register IR2 is coupled to the register selector RSEL.

  The output of the instruction decoder DEC is coupled to a register selector RSEL and the instruction register IR2. The instruction decoder DEC decodes the operation code in the operation field of the instruction fetched into the instruction register IR1.

  When the instruction code fetched into the instruction register IR1 is the register extension pre-instruction code, the instruction decoder DEC decodes the instruction code to read the register group specification field (gr) of the register extension pre-instruction code. The register designation information is latched in the instruction register IR2. The latch signal at that time is output from the instruction decoder DEC. The register field designation information latched in the instruction register IR2 and the register designation information of the register field (r) included in the subsequent instruction fetched in the instruction register IR1 are decoded by the register selector RSEL and directly used as the information. A register in the designated register group is selected, and the subsequent instruction is executed using the selected register. After executing this instruction, the instruction decoder DEC supplies a set signal to the instruction register IR2 for clearing the latch information of the instruction register IR2 to all bit values “0” (register group 0 designation information). Therefore, even if an instruction omitting the prefix instruction code is fetched to the instruction register IR1 thereafter, the output of the instruction register IR2 maintains the designation information of the register group 0. As a result, the register selector RSEL implicitly registers the register group 0. Is selected from the register group 0 according to the register specification information from the instruction register IR1.

  The execution unit EXEC further includes temporary registers TRA and TRD, an arithmetic logic unit ALU, an incrementer INC, a read data buffer RDB, a write data buffer WDB, and an address buffer AB. These circuit blocks are connected to each other by data buses GB, DB, and WB. The data buses GB and DB are positioned as data read buses for the registers ER0 to ER31, and the data bus WB is positioned as a data write bus for the registers ER0 to ER31. Although not shown in detail, each part of the execution unit EXEC is divided in accordance with the division E (16 bits), H (8 bits), and L (8 bits) of the general-purpose registers.

  The arithmetic and logic unit ALU uses various operations specified by instructions and effective address calculation. The incrementer INC is mainly used for addition of the program counter PC.

  The read data buffer RDB temporarily stores instruction codes and data read from the ROM 504, RAM 505, internal I / O register, or external memory (not shown). The write data buffer WDB temporarily stores write data to the ROM 504, RAM 505, internal I / O register, or external memory. The read data buffer RDB and the write data buffer WDB adjust the timing of the internal operation of the CPU 502 and the external read / write operation of the CPU 502.

  The address buffer AB temporarily stores an address of data read / written by the CPU 502, and has an increment function for the stored contents and a function for holding the increment result. The GB bus, DB bus, and WB bus are 32 bits, whereas the IDB is 16 bits. Therefore, when 32-bit data is accessed twice as 16-bit data, the second data access is performed. Prior to this, the contents of the address buffer AB are incremented.

  FIG. 85 shows a detailed block diagram of a part of the register selector RSEL and the instruction register IR2.

  The instruction register IR2 has latch circuits LGR1 and LGR2 as holding means. These latch circuits LGR1 and LGR2 latch the register group designation information in the register group designation fields gr1 and gr2, as described above.

  According to FIG. 85, the latch circuits LGR1 and LGR2 are constituted by so-called reset D flip-flops. An instruction execution end signal RSLGR designated from the instruction decoder DEC is input as the reset signal RSLGR. A latch clock LGRCL designated from the instruction decoder DEC is input as a latch clock, and bits 7 to 4 and 3 to 0 of the instruction code held in the instruction register IR1 as data (in the case of group 4, bit 5; 4, 1, 0) may be entered. The latch clock LGRCL becomes active when an instruction code designating a register group (an optional instruction code for register extension) is executed, and bits 7 to 4 are register fields (gr) at that time. , 3 to 0 are latched. The latch circuits LGR1 and LGR2 are set to a predetermined value, for example, all bits 0 based on a reset signal RSLGR, which is a control signal from the instruction decoder DEC, at the end of execution of the instruction, so that the register block 0 is designated. It is initialized. Since the latch circuits LGR1 and LGR2 remain cleared to the value “0”, an instruction that does not have the register instruction prefix instruction code that designates the general-purpose register group remains in the register group 0 when the instruction is executed. General-purpose registers are specified.

  On the destination register designation side of the register selector RSEL, there are a latch circuit LAT1 that holds information of a register group designation field (gr2) output from the latch circuit LGR2, and a register designation field (r2) output from the instruction register IR1. A latch circuit LAT2 for latching information is provided. These latch circuits LAT1 and LAT2 perform a latch operation with an inverted clock φ # of the system clock φ, and the destination register selection operation is performed later than the source register selection operation. As a result, the latch timing of the register designation information on the destination side, that is, the destination register selection timing is delayed by 0.5 state from the source register selection timing. The source register is selected in advance as an address register, and the destination register can be selected later for writing data.

  Further, the information in the register designation field r1 output from the instruction register IR1 and the information in the register designation field r2 output from the latch circuit LAT2 are input to the logic circuits LOG1 and LOG2, and the input register specification field r1, Bits 0 and 1 of r2 are controlled by the control signals s1 to s3, output from the logic circuits LOG1 and LOG2, and used for combination fixed register selection. The control signals s1 to s3 are output from the decoder DEC. The control signals s1 to s3 are used when a transfer instruction of a plurality of general purpose registers is executed, otherwise they are all set to 0, and the inputs r1 and r2 of LOG1 and LOG2 are output as they are.

  The functions of the control signals s1 to s3 are illustrated in FIG. The control signal s1 fixes bit 0 of information in the register designation fields r1 and r2. Similarly, the control signal s2 fixes bit 1 of information in the register designation fields r1 and r2 to 1 and bit 0 to 0. s3 fixes both bit 1 and bit 0 of the information in the register designation fields r1 and r2. When two general purpose registers are designated, the control signal s1 is output. In the case of three, it outputs in order of s1, s2, and in the case of four, it outputs in order of s1, s2, s3. As a result, if one register is first designated in the register designation fields r1 and r2 in a transfer instruction for a plurality of general purpose registers, the subsequent registers are selected in the prescribed order by the control signals s1 to s3. Is done. As a result, general-purpose registers are sequentially selected in a fixed combination. As is apparent from the output logic of the control signals s1 to s3, when a register is designated by the 3-bit or 4-bit register designation areas r1 and r2 in the transfer instructions of a plurality of general-purpose registers, the register designation areas r1 and r2 are designated. The initial value that can be set depends on the number of general-purpose registers to which the instruction is to be transferred, and must be *** 0 for two, *** 00 for three, or ** 00 for four. I must. The symbol * may take any value. As a result, the register selector SEL itself can be shared with other instructions to cope with the plural general-purpose register transfer instructions, so that an increase in logical scale can be suppressed as much as possible.

  FIG. 87 shows an example of the address buffer AB. The address buffer AB includes a latch circuit 521, an incrementer 522, and a selector buffer 523. The latch circuit 521 inputs the output of the internal bus GB and the incrementer 522. When the control signal mabinc is active, the output of the incrementer 522 is latched, and when it is inactive, the contents of the bus GB are latched.

  The incrementer 522 receives the output of the latch circuit 521 and adds +2. When the control signal mabinc is activated, the incremented value is repeatedly fed back from the latch circuit 21 to the incrementer 22, whereby a plurality of increments +4, +6,.

  The selector buffer 523 inputs the contents of the latch circuit 521 and the incrementer 522. When the control signal mabinc is active, the output of the incrementer 522 is selected. When the control signal mabinc is inactive, the output of the latch circuit 521 is selected. The selected content is output to the internal address bus IAB in accordance with the bus right acknowledge signal. When the bus right acknowledge is inactive, address buffer AB does not output to internal address bus IAB, and the output is set to a high impedance state.

  88 and 89 show a part of the control logic of the decoder DEC for a transfer instruction (MOV and MOVM instruction) of a word size between registers and registers by a logical description. The description of FIG. 9 is the remaining logical description following FIG. FIG. 93 is a flowchart corresponding to a control operation by transfer instructions (MOV and MOVM) of single and plural general-purpose registers between registers and registers by controlling the logical description shown in FIGS.

  The logic description shown in FIGS. 88 and 89 is called RTL (Register Transfer Level) or HDL (Hardware Description Language) description, and can be logically expanded into a logic circuit by a known logic synthesis tool. HDL is standardized as IEEE 1364. The syntax of the logical description shown here conforms to the case statement, and when there is a change in the value or signal defined in () next to alwayss @, The content is that processing is performed. “8′b00001000” means 00001000 having an 8-bit length. In the figure, a lowercase signal is a signal generated and output by the instruction decoder DEC, and an uppercase signal is a signal input to the instruction decoder DEC.

  In the logical description of FIG. 88, whether the transfer instruction uses a single general purpose register or a plurality of general purpose registers is instructed by signals MOD2 to MOD4. Signal MOD2 indicates the designation of two general purpose registers, signal MOD3 indicates the designation of three general purpose registers, and signal MOD4 indicates the designation of four general purpose registers. The signals MOD2 to MOD4 are generated according to the contents of the instruction extension prefix instruction code.

  88 and 89, the control signal is generated in accordance with the state code TMG (5-bit information), and the following is performed according to the current state code value and the MOD2 to MOD4 values at that time. The value of the state code NEXTTMG is determined.

  In the single register transfer instruction, the state code TMG is 1 (0001). On the other hand, the state codes TMG5 (00101), 9 (01001), 13 ( 01101) has been added.

  Multiple register transfer instructions are indicated by MOD2 to MOD4 signals. The state code TMG is generated in the first part (1) of the logical description of FIG. In the case of a single register, the state code TMG is 1. In the case of multiple registers, for example, when MOD4 = 1, TMG proceeds from 1 → 5 → 9 → 13. When MOD3 = 1, the state code 13 is omitted, and when MOD2 = 1, the state codes 9 and 13 are omitted.

  When NEXTTMG [5] = 0, the next TMG is NEXTTMG [4: 0]. When NEXTTMG [5] = 1, the next TMG is set to 5'b00001.

  Bus control is performed in the second part (2) of the logical description of FIG. When nop = 0, the bus access is started, and when nop = 1, the bus access is prohibited. Data = 0 indicates an instruction read, and data = 1 indicates a data access.

  In the case of this transfer instruction, instruction read is performed when the state code TMG is 1, and bus access is not performed when the state code TMG is 5, 9, or 13.

  In the case of instruction read, the contents of the internal data bus IDB are stored in the instruction register IR1 and the read data buffer RDB at a predetermined timing. In the case of data read, the contents of the internal data bus IDB are stored in the read data buffer RDB at a predetermined timing. In the case of data write, the contents of the write data buffer WDB are output to the IDB at a predetermined timing.

  In the third part (3) of the logical description of FIG. 89, the transfer data is controlled. In each state, the data is output from the general-purpose register to the internal bus DB, and the write from the internal bus WB to the general-purpose register is instructed via the arithmetic logic unit ALU.

  In any case, after designating the general-purpose register, the register designation field r2 is updated. When the signal s1 is 1, the bit 0 of the register field r1 is fixed to 1. Similarly, the signal s2 fixes bit 1 to 1 and bit 0 to 0. The signal s3 fixes bits 1 and 0 to 1.

  In the state code TMG 1, when a single register transfer instruction, that is, MOD2 to MOD4 is 0, the ccrset signal is set to 1, and a predetermined bit of the condition code register CCR changes to reflect the transfer data. To be done.

  90 to 92 show a part of the control logic of the decoder DEC for transfer instructions (MOV and MOVM instructions) with 16-bit absolute addresses. The description of FIG. 91 is the remaining logical description following FIG. 90, and the description of FIG. 92 is the remaining logical description following FIG. FIG. 94 is a flowchart corresponding to the control operation by single and plural general-purpose register transfer instructions (MOV and MOVM) with 16-bit absolute addresses under the control of the logical description shown in FIGS.

  As shown in “(4) 16-bit absolute address” in FIG. 10, the data size is IR [8] (the eighth bit from the least significant bit of the instruction register IR) = 0, the byte size, and IR [8] = 1. When IR [7] = 0, memory → general-purpose register (read type), and when IR [7] = 1, general-purpose register → memory (write type).

  Selection of word size / long word size, single register / multiple registers is instructed by signals LNG and signals MOD2 to MOD4. Signal LNG indicates the long word size. Signals MOD2 to MOD4 indicate 2 to 4 register selections, respectively, and are generated according to an instruction extension prefix instruction code.

  Single register transfer instruction flow (state code 1 → 2 → 3), multiple register transfer instruction specific data transfer state (state codes 6, 10, 14) and single / multiple register transfer The state (state codes 18, 22, 26, 30) at the time of the long word size of the instruction is added.

  The state code TMG is generated in the first part (1) of the logical description shown in FIG. In the case of a single register, the state code TMG proceeds from 1 → 2 → 3. In the case of multiple registers, for example, when MOD4 = 1, TMG proceeds as 1 → 2 → 6 → 10 → 14 → 3. When MOD3 = 1, the state code 14 is omitted, and when MOD2 = 1, the state codes 10 and 14 are omitted. In the case of a long word size, state codes 18, 22, 26, and 30 are added.

  In the second part (2) of the logical description of FIG. 91, bus control is performed. In the case of this transfer instruction, instruction read is performed with the state codes 1 and 3, and data access is performed with the state codes 2, 18, 6, 22, 10, 26, 14, and 30. Data access read / write is instructed by IR [7]. Except for the last data access, long = 1 is set, and bus right transfer prohibition is instructed.

  In the case of instruction read, the contents of the internal data bus IDB are stored in the instruction register IR and the read data buffer RDB at a predetermined timing. In the case of data read, the contents of the internal data bus IDB are stored in the read data buffer RDB at a predetermined timing. In the case of data write, the contents of the write data buffer WDB are output to the internal data bus IDB at a predetermined timing.

  The effective address is calculated in the third part (3) of the logical description shown in FIG. In the case of this transfer instruction, the 16-bit EA extension part of the instruction code held in the read data buffer RDB is sign-extended to 32 bits by the signal dbrex and output to the internal bus GB with the state code 2. The contents of the internal bus GB are stored in the address buffer AB every state, and no particular control is required. In the state codes 18, 6, 22, 10, 26, 14, and 30, the content held in the address buffer AB is incremented (+2) by the signal mabinc.

  In the fourth part (4) of the logical description shown in FIG. 92, transfer data is controlled. In the case of the read type (IR [7] = 0), the read data is output from the read data buffer RDB to the internal bus GB with the state codes 6, 10, 14, and 3, and the arithmetic logic unit ALU and the internal bus WB are output. And store in general-purpose registers. In the case of the write type (IR [7] = 1), the state code 2, 6, 10, 14 is output from the general-purpose register to the internal bus DB, and is output to the internal data bus IDB via the write data buffer WDB. . In any case, after designating the general-purpose register, the register designation field r1 is updated. When the signal s1 is 1, the bit 0 of the register field r1 is fixed to 1. Similarly, the signal s2 fixes bit 1 to 1 and bit 0 to 0. The signal s3 fixes bits 1 and 0 to 1. These are indicated as r2 +++ in FIG.

  In the state code 3, when a single register transfer instruction, that is, the signals MOD2 to MOD4 are all 0, the signal ccrset is set to 1, and a predetermined bit of the condition code register CCR changes to reflect the transfer data. To be.

  In the other addressing modes, in addition to the predetermined instruction read and effective address calculation, the data access operation corresponding to the state codes 18, 6, 22, 10, 26, 14, and 30 may be added in the same manner as described above. . These can be common to various addressing modes.

  FIG. 95 shows a first example of a register / register type first transfer instruction (MOV.L ER0, ER1), a second transfer instruction (MOV.L ER8, ER17), and a multiple register transfer instruction ( The execution timing of MOVM.W R0-R1, E28-E29) is illustrated.

  Since the register / register type first transfer instruction (MOV.L ER0, ER1) uses only the general-purpose register of group 0, the instruction code for specifying the general-purpose register group is not required. The instruction is the same one word.

  FIG. 95 shows the timing when the read / write of the internal ROM 504 and RAM 505 can be read / written in one state, although not particularly limited. In the following description, one state synchronized with the rise of φ is referred to as a φ synchronization state, and one state synchronized with the rise of φ # (which is an inverted clock signal of the clock signal φ and not shown) is referred to as a φ # synchronization state. Called.

  In the φ # synchronous state of cycle T0, the address is output from the address buffer AB of the CPU 502 to the internal address bus IAB. The instruction decoder DEC outputs a bus command BCMD indicating instruction fetch (if).

  In the φ synchronization state of cycle T1, the contents of internal address bus IAB are output to internal address bus PAB, a read cycle is started based on bus command BCMD, and data is output to internal data bus PDB. In the φ # synchronous state of cycle T1, the read data of the internal data bus PDB is obtained on the internal data bus IDB, and this is latched in the instruction register IR1 in the φ synchronous state of cycle T2. The above operation is performed by controlling the execution of the previous instruction (prefetch). Here, the built-in ROM 504 and RAM 505 are not connected to the internal address bus PAB and the internal data bus PDB, but the operations corresponding to the internal buses PAB and PDB are performed in the module. The operation is shown.

  When the execution of the immediately preceding instruction is completed, when the execution of the instruction is started earliest, the instruction code is input to the instruction decoder DEC in the φ synchronous state of cycle T2, and the content of the instruction is decoded. According to the result of decoding, a control signal is output to control each part. The circuits LOG1 and LOG2 receive the signals s1 to s3 formed by the values of the register designation feeds r1 and r2 that are part of the instruction and the number of registers of a plurality of registers, and control the values of the register fields r1 and r2. Output. The output of the circuit LOG1 is called a signal SEL1, and the output of the circuit LOG2 is called a signal SEL2.

  In the inter-register operation instruction, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC in the φ # synchronous state of the cycle T2. An address signal is output from address buffer AB to address bus IAB. At this time, since both the latch circuits LGR1 and LGR2 are cleared to 0, the register selector RSEL selects the register based on the signals SEL1 and SEL2 and the control signal B (Rs → DB) output from the instruction decoder DEC. A signal B (ER0 → DB) is generated.

  From cycle T3, the next next instruction (in this example, MOV.L ER8, ER17) is read. In the φ synchronization state of cycle T3, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. Based on the signals SEL1, SEL2 and the control signal C (WB → Rd), the register selector RSEL generates a register selection signal C (WB → ER1). The register selection signal B selects the register and inputs the data of the source side register (Rs) to the arithmetic logic unit ALU. The operation content of the arithmetic logic unit ALU is instructed by the control signal C by the instruction decoder DEC. Addition, logical operation, shift, and the like can be performed in one clock. For example, in the above instruction, 32-bit addition is instructed (the input on the bus GB side is set to 0).

  The instruction to load the next instruction to the instruction decoder DEC is instructed. Clearing of the latch circuits LGR1 and LGR2 is instructed by the control signal B (RSLGR). The latch circuit LGR1 transmits the result cleared in the φ synchronous state of cycle T3, and the latch circuit LGR2 transmits the result cleared in the φ # synchronous state of cycle T3.

  In the φ # synchronous state of cycle T3, the operation result of the arithmetic logic unit ALU is written to the destination-side register (ER1) selected by the register selection signal C via the internal bus WB. Although not shown, the condition code register CCR is updated by the control signal C. Further, the next instruction is fetched into the instruction register IR1. At the same time, execution of the next life is started. For example, the contents of the program counter PC are read out and input to the address buffer AB and the incrementer INC.

  Inter-register operations between groups 0 can be executed substantially in one state.

  The register / register type second transfer instruction (MOV.L ER8, ER17) is a two-word instruction by adding an instruction code designating a general-purpose register group. The second word is the MOV. It is the same as L R0 and R1. That is, because gr1 = 1, the register number n = 8 for the same r1 = 0, and because gr2 = 2, the register number n = 17 is interpreted for the same r2 = 1.

  In the φ # synchronization state of cycle T2, the address is output from the address buffer AB of the CPU 502 to the address bus IAB.

  In the φ synchronization state of cycle T3, the contents of the address bus IAB are output to the address bus PAB, and a read cycle is started. Read data is obtained on the internal data bus in the φ # synchronous state of cycle T3, and this is latched in the instruction register IR1 in the φ synchronous state of cycle T4. This is an optional instruction word (prefix instruction code) with a register group field.

  Subsequently, the next address (+2 content) is output to the address bus IAB in the φ # synchronous state of cycle T4, and this read data is latched in the instruction register IR1 in the φ synchronous state of cycle T5. The above operations are performed by controlling the execution of the first register / register type transfer instruction and the next instruction (not shown).

  In the φ synchronous state of cycle T4, an instruction code (prefix instruction code) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Group field latch signal LGRCL is issued, and the register group designation field (bits 7 to 0 of IR1) is latched by latch circuits LGR1 and LGR2.

  In the φ # synchronous state of cycle T4, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address signal is output from address buffer AB to address bus IAB.

  From cycle T5, the next instruction (in this example, MOVM.W R0-R1, E28-E29) is read.

  In the φ synchronous state of cycle T5, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB. A continuous command signal continue (same as the interrupt inhibition signal mskint) included in the control signal B (control B) for not dividing the first word and the second word is output to the interrupt control circuit INTC. Even if an interrupt request or the like is generated, the execution of the instruction can be continued by this signal. The contents of the latch circuits LGR1 and LGR2 are held.

  On the other hand, an instruction code (instructing a transfer instruction) is input to the instruction decoder DEC in the φ synchronous state of cycle T4, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since LGR1 = 1 and LGR2 = 2, the register selection signal B (ER8-DB) is generated based on the signals SEL1 and SEL2 and the control signal B (Rs-DB) output from the instruction decoder DEC. A register selection signal C (WB-ER17) is generated based on the signals SEL1 and SEL2 and the control signal C (WB-Rd). The other operations based on the second word can be the same as the first transfer instruction (MOV.L ER0, ER1) (LGR1 and LGR2 are instructed to be cleared by the control signal B (RSLGR) as in the first transfer instruction). The latch circuit LGR1 is transmitted in the φ synchronous state of cycle T6, and the latch circuit LGR2 is transmitted the result cleared in the φ # synchronous state of cycle T6).

  That is, the content of the instruction decoder DEC can be made equivalent to that of the instruction decoder of the existing lower CPU except that the latch signals LGR1 and LGR2 corresponding to the first word (prefix instruction code) and the continuous instruction signal are output. . Needless to say, the portion corresponding to the front instruction code of the instruction decoder DEC is relatively small. That is, the addition of logical scale can be minimized. Further, since most of the instruction decoder DEC can be made equivalent to the instruction decoder of the existing lower CPU, the conventional design assets can be used effectively.

  Next, an example of “MOVM.W R0-R1, E28-E29” which is a register-register transfer instruction of a plurality of registers is shown. The register designation field r1 is 3'b000, and r2 is 3'b100.

  This transfer instruction “MOVM.W R0-R1, E28-E29” adds a register extension prefix instruction code for specifying a general-purpose register group and an instruction extension prefix instruction code (also referred to as a prefix code) indicating MOVM. Thus, a 3-word instruction is obtained. The third word (mov) is MOV. It is the same as W R0 and R4. Since gr2 = 3, the register number n = 28 is interpreted for the same r1 = 4. Since the word size is r2 [3] = 1, the general-purpose register E is designated.

  In the φ # synchronous state of cycle T5, an address is output from the address buffer AB of the CPU 502 to the address bus IAB.

  In the φ synchronization state of cycle T6, the contents of the address bus IAB are output to the address bus PAB, and a read cycle is started. Read data is obtained on the internal data bus in the φ # synchronous state of cycle T6, and is latched in the instruction register IR1 in the φ synchronous state of cycle T7. This is an optional instruction word (prefix instruction code) with a register group field.

  Subsequently, the next address (+2 content) is output to the address bus IAB in the φ # synchronous state of cycle T7, and this read data is latched in the instruction register IR1 in the φ synchronous state of cycle T8. The above operation is performed by controlling the execution of the register / register type second transfer instruction and the next instruction (not shown).

  In the φ synchronous state of cycle T7, the first instruction code is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the decoding result, a group field latch signal LGRCL is issued, and the register group designation field (bits 7 to 0 of IR1) is latched in the latch circuits LGR1 and LGR2.

  In the φ # synchronous state of cycle T7, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address signal is output from address buffer AB to address bus IAB.

  From cycle T8, the next next instruction is read. The result incremented (+2) by the incrementer INC at φ in cycle T8 is written to the program counter PC via the internal bus WB. A continuous command signal (interrupt prohibition signal) is output to the interrupt control circuit INTC with the control signal B for preventing the first word and the second word and thereafter from being divided. The contents of the latch circuits LGR1 and LGR2 are held. Also, the second instruction code is input to the instruction decoder DEC, and the contents of the instruction are decoded. A control signal MOD2 is output according to the decoding result. In the φ # synchronous state of cycle T8, the contents of the program counter PC are read to the internal bus GB and input to the address buffer AB and the incrementer INC. An address signal is output from address buffer AB to address IAB.

  On the other hand, an instruction code (instructing a transfer instruction) is input to the instruction decoder DEC in the φ synchronous state of cycle T9, and the contents of the instruction are decoded. According to the result of decoding, a control signal is output to control each part. Since LGR1 = 0 and LGR2 = 3, the register selector RSEL uses the register selection signal B, based on the signals SEL1, SEL2 and the control signals B, C (Rs-DB, WB-Rd) output from the instruction decoder DEC. C (R0-DB, WB-E28) is generated. A control signal s1 is generated to instruct change of SEL1 and SEL2 (3'b100 → 101).

  Subsequently, based on the signals SEL1, SEL2 and the control signals B, C (Rs-DB, WB-Rd) output from the instruction decoder DEC, the register selector RSEL outputs the register selection signals B, C (R1-DB) according to the MOD2 signal. WB-E29).

  FIG. 96 shows an execution sequence of a second example (MOVM.L @aa: 16, ER0-ER1) of a multiple register transfer instruction.

  The above instruction is an example of reading data to two general purpose registers. The register designation field is 3'b000. The addressing mode is 16 bits of an absolute address, and the effective address is a content obtained by sign extension of aa. This sign extension is performed when reading from the read data buffer RDB. In the following, the content of sign-extended aa is also simply referred to as aa.

  Execution of the transfer instruction is started from cycle T2. Although there is no particular limitation, the first word of the instruction code is a prefix code indicating MOVM, and the operation of the next instruction code is designated (MOD2 signal output), and other operations for incrementing the program counter PC are not performed.

  The instruction code (mov-1) of the second word is MOV. L @aa: 16, common with ER0 instruction.

  The contents of the read data buffer RDB are output to the bus GB and stored in the address buffer AB in the φ # synchronization state of the cycle T4. The contents of address buffer AB are output to address bus IAB. At the same time, a bus command BCMD is output to indicate word data read and bus right transfer prohibition in the next bus cycle.

  In the φ # synchronization state of cycle T5, the upper 16 bits of the read data (contents of general-purpose register E) are output to the internal data bus IDB. Further, the output value of the address bus IAB is set to aa + 2 by the increment function of the address buffer AB. At the same time, a bus command BCMD is output to indicate word data read and bus right transfer prohibition in the next bus cycle.

  In the φ synchronous state of cycle T6, read data is stored in the read data buffer RDB.

  In the φ # synchronous state of cycle T6, the lower 16 bits of the read data (contents of general register R) are output to the internal data bus. Further, the output value of the address bus IAB is set to aa + 4 by the increment function of the address buffer AB. At the same time, a bus command BCMD is output to indicate word data read and bus right transfer prohibition in the next bus cycle.

  In the φ synchronization state of cycle T7, the content of the read data is transferred to the arithmetic logic unit ALU via the bus GB in 32 bits.

  In the φ # synchronization state of cycle T7, the upper 16 bits of the read data (contents of general register E) are output to the internal data bus. Further, the output value of the address bus IAB is set to aa + 6 by the increment function of the address buffer AB. At the same time, the bus command BCMD is output to indicate word data read and bus right transfer permission in the next bus cycle.

  In the φ # synchronization state of cycle T8, the lower 16 bits of the read data (contents of general-purpose register R) are output to the internal data bus. Also, bit 0 of the register selection signal is inverted by the second control signal B. The register to be transferred is selected by the first control signal A and the signal SEL2 (= 3'b001), and the register control signal B is generated.

  After the φ # synchronous state of cycle T8, the next next instruction is read and the program counter PC is incremented (+2) as described above.

  When three registers are specified, the number of execution states is increased by two, and the address buffer AB is incremented twice (+2) (total +6). When bit 1 of the signals SEL1 and SEL2 is inverted and the register designation field is 000, it is set to 010 and the general-purpose register ER2 is selected. The write operation is performed twice (6 times in total).

  When four registers are designated, the number of execution states is further increased by two states, and the address buffer AB is incremented twice (+2) (total +10). Further, when the bits 1 and 0 of the signals SEL1 and SEL2 are inverted and the register designation field is 000, it is set to 011 and the general purpose registers ER2 and ER3 are selected. The write operation is performed twice (8 times in total).

  Since the lower bits of the register number are fixed, it is easy to control to change this according to the execution of instruction processing. An adder or the like is unnecessary, and an increase in logical scale can be suppressed. For example, when saving two registers, the low-order bit of the register designation field on the instruction code is 0, so the first register designation is in accordance with the value of the register designation field, and the second register designation is an instruction According to the control of the decoder DEC, the lower 1 bit of the register designation field is changed to 1 so as to be performed.

  On the other hand, the MOV instruction is a read of one register, and the second read operation is not performed, so that the execution operation is shared.

  FIG. 97 shows an execution sequence of a third example (MOVM.W R10-R11, @ ER6) of a transfer instruction of a plurality of registers. The above instruction is an example of writing two general-purpose registers of word size. The register designation field is 3'b010.

  Execution of the transfer instruction is started from cycle T2. Although not particularly limited, the first word of the instruction code is a prefix code having a register group field, the register group designation field (bits 1 to 0 of IR1) is latched by the latch circuits LGR1 and LGR2, and the program counter PC is incremented. To do.

  The instruction code of the second word is a prefix code indicating MOVM, and specifies the operation of the next instruction code. A control signal MOD2 is output. The instruction code of the third word is MOV. Common to WR2, @ ER6 instruction.

  In the φ # synchronous state of cycle T4, the contents of register ER6 are output to bus GB and stored in address buffer AB. The contents of address buffer AB are output to address bus IAB. At the same time, a bus command BCMD is output to indicate word data write and prohibition of bus right transfer in the next bus cycle.

  Further, the register to be transferred is selected by the first control signal B, the latch information (= 3′b001) of the latch circuit LGR2, and the signal SEL2 (= 3′b010), and the register control signal B is generated. A control signal s1 is generated to instruct the change of the signal SEL2 (3'b010 → 011).

  In the φ synchronous state of the state cycle T5, the selected register (contents of R10) is transferred to the write data buffer WDB via the bus DB.

  In the φ # synchronous state of T5, the transferred data (contents of R10) is output to the internal data bus IDB. Further, the output value of the address bus IAB is set to EA + 2 by the increment function of the address buffer AB. Further, the register to be transferred is selected by the first control signal B, the latch information (= 3′b001) of the latch circuit LGR2, and the signal SEL2 (= 3′b011), and the register control signal B is generated.

  In the φ synchronization state of cycle T6, the contents of the selected register R11 are transferred to the write data buffer WDB via the bus DB.

  In the φ # synchronization state of cycle T6, the transferred data (content of R11) is output to the internal data bus IDB.

  After the φ # synchronous state of cycle T6, the next next instruction is read and the program counter PC is incremented (+2) as described above.

  When three registers are designated, the number of execution states is increased by one state, and the address buffer AB is incremented (+2) once more (total +4). When bit 1 of the signals SEL1 and SEL2 is inverted and the register designation field is 000, it is set to 010. The write operation is performed once (total 3 times).

  When four registers are designated, the number of execution states is further increased by one state, and the address buffer AB is incremented (+2) once more (total +6). When bits 1 and 0 of SEL1 and SEL2 are inverted and the register designation field is 000, 011 is set. The write operation is performed once (total 4 times).

  FIG. 98 shows an outline of the development environment of the CPU 502. This makes it possible to provide a common development environment between the existing lower CPU and the CPU 502 that is upwardly compatible with the existing lower CPU.

  The user creates a program in C language or assembly language using various editors. This is usually created by dividing it into a plurality of modules.

  The C compiler 540 inputs each C language source program created by the user, and outputs an assembly language source program or an object module. The assembler 541 inputs an assembly language source program and outputs an object module. The linkage editor 542 inputs a plurality of object modules generated by the C compiler 540 and the assembler 541, resolves external references and relative addresses of each module, combines them into one program, and loads a load module. Output.

  The load module can be input to the simulator debugger 543 to simulate the operation of the CPU on a system development apparatus such as a personal computer, display the execution result, and analyze and evaluate the program. Further, by inputting a load module into the emulator 544 and performing so-called in-circuit emulation that operates on an actual application system or the like, the actual operation of the microcomputer as a whole can be analyzed and evaluated. Furthermore, when the load module is input to the PROM writer 545 and the ROM 504 of the microcomputer 1 is an electrically writable memory such as a flash memory, the memory can be written. In addition, a general subroutine can be provided as a librarian.

  FIG. 43 is also a diagram illustrating a CPU selection method in the system development apparatus of the CPU 502. The contents described with reference to FIG. 43 also apply to the system development apparatus of the CPU 502 as it is. As a selection method of the CPU, the selection may be made by a drop-down menu of the window, or it may be input as a C shell command for a workstation or the like. Further, the CPU type and operation mode can be input as a control instruction of a source program such as an assembler or C compiler.

  The assembler interprets the description in the input assembly language source program according to the selected CPU type and operation mode, and generates an object module or displays it if there is an error. If an existing lower CPU is selected and an instruction (extended instruction) that exists in the upper CPU 502 and does not exist in the existing CPU is described, an error occurs. Since the instruction code itself is included in the CPU 502, an assembler 541 is developed for this purpose, and an existing lower CPU is added to detect an instruction that exists in the upper CPU 502 and does not exist in the existing lower CPU. It can be easily made common. Since there is an assembler for an existing lower CPU, it goes without saying that it can be easily modified and applied to the upper CPU 2.

  According to the selected CPU type and operation mode, the C compiler discriminates instructions, general-purpose registers, and address spaces indicated by combinations of operations, data sizes, and addressing modes that can be used. It is converted into CPU instructions and output as an assembly language program or object module.

  In addition to the function of converting C language programs into CPU instructions, the C compiler itself improves functions not directly related to the CPU instruction set, such as C ++ language program compilation and inter-module optimization. However, in an individual compiler for each CPU, these functional improvements must be applied to all the individual compilers. If the common C compiler 540 is used as in the present invention, it is easy to improve functions not directly related to the CPU instruction set, and to improve development efficiency.

  The simulator debugger interprets the input load module program, simulates the operation of the CPU, and displays any errors in it. For example, if an existing lower CPU is selected and an instruction that exists in the CPU 502 of the present invention and does not exist in the existing CPU is executed, an error occurs. Since the instruction code and the instruction execution function itself are included in the CPU 502 of the present invention, a simulator debugger 543 is developed for this purpose, and the existing lower CPU exists in the CPU 502 of the present invention and exists in the existing CPU. It can be easily shared, for example, by adding an instruction that detects an instruction that is not to be executed. Needless to say, if an existing CPU has a simulator debugger, it can be easily modified and applied to the CPU 502 of the present invention.

  FIG. 45 is also a drawing showing an emulator for a microcomputer having a CPU 502 according to the present invention. In FIG. 45, an emulation processor 410 is configured by adding an emulation interface to the microcomputer portion. The microcomputer portion corresponds to, for example, the configuration of the microcomputer 501 in FIG. For example, when the program (load module) input from the system development device 427 is transferred to the user program storage area of the emulation memory 421 and the CPU 502 reads such a program to be placed on the internal ROM 504, the program on the emulation memory 421 is read. Is read and executed. In addition, a break condition, a real-time trace condition, and the like can be given from the system development device 427.

  The control processor 425 stores a program for selecting the type of CPU originally used in the application system 412 in the emulation program storage area of the emulation memory 421. The CPU 502 executes such a program in a state where the program is broken under a predetermined condition, and performs settings necessary for emulation by setting the control register for emulation. In this case, it is convenient to enable writing only in the execution mode of the emulation program, so-called break mode. It is possible to prevent erroneous setting due to malfunction of the software of the user who is still developing. Further, by using the control register, even if the number of CPU types to be originally used in the application system 412 increases, it is only necessary to change the configuration of the control register, and there is no need to change the emulation interface. There is no need to change the hardware of the emulator.

  FIG. 99 is a block diagram of an emulation processor corresponding to the microcomputer 501. The emulation processor 50 includes a microcomputer 501 portion (microcomputer core 571) in FIG. 79 and an emulation interface 572. The timers and input / output ports of FIG. 79 are represented as I / O, and details of the internal bus and the bus controller are shown. Note that the timer 506, the pulse output circuit 507, the input / output ports IOP1 to IOP5, IOPA to IOPF, and the like in FIG. 79 are represented as an I / O 573 and a user buffer (user BUF) 574. The user interface 576 is a generic term for an interface circuit connected to a user system (a target system that is an emulation target system) including the I / O 573, the user buffer 574, an input / output buffer (not shown), and the like.

  In the microcomputer core 571, an undefined instruction detection circuit 578 is added to the microcomputer 501 in FIG. The emulation interface 572 includes a control register 579. The control register 579 can be written only in the break mode. Signals input / output from the emulation interface 572 include a bus status signal indicating the state of the bus such as an address bus, a data bus, a read signal, a write signal, a data size signal, and an instruction fetch signal, a signal indicating the start of instruction execution, and an interrupt A CPU status signal indicating the execution state of the CPU 502, such as a signal indicating the start of processing execution, and the like are used for analyzing the operation of the microcomputer by the emulator.

  The undefined instruction detection circuit 578 analyzes the instruction code input to the CPU 502, and when it detects that an instruction that does not exist in the function of the selected CPU has started execution, it requests the CPU 502 to make a break interrupt. Which function is selected by the CPU 502 is instructed from the control register 579. For example, when the function of an existing lower CPU is selected, when a prefix instruction code having a register group field is executed, it is detected as an undefined instruction. Specifically, if the instruction code is latched with the LIR signal, analyzed, and decoded as undefined, it is easy to request a break interrupt when the LID signal is generated. .

  As described above, the emulation processor 550 includes the upper CPU 502 and can be used as a substitute for other lower CPUs. Which one should be selected may be specified by the register 579.

  In any case, if the emulation interface is shared, even if the CPU or other functional blocks are changed, it is not necessary to change the hardware on the emulator side, and only the emulation processor 550 is changed. Thus, it is only necessary to indicate which CPU is targeted for the disassembler when analyzing and displaying the operation of the instruction. The instruction to the disassembler can be designated by the user from the system development device, or can be automatically selected by input information from the assembler. This improves emulator development efficiency and provides an emulator development environment quickly.

  FIG. 100 illustrates a microcomputer system using the microcomputer 501 to which the present invention is applied for printer control.

  The printer control system includes a microcomputer 501, a transmission / reception circuit (reception circuit or transmission / reception circuit) 580 such as a Centronics interface (or IEEE1284), a universal serial bus or an option, a buffer RAM (DRAM) 581, and a character generation ROM (CGROM). ), A program ROM 583, and a print control circuit 584, which are connected via an external bus 585 of the microcomputer.

  The address space connected to the external bus 585 is divided into areas of a predetermined size, and bus specifications (bus width, number of access states, address multiplex, burst operation, etc.) can be set for each. Such bus control for each area is performed by an external bus controller of the bus controller 510 included in the microcomputer 501.

  The program ROM 583 is connected to area 0, the buffer RAM 581 is connected to area 2, the CGROM 582 is connected to area 6, and the transmission / reception circuit 580 and the print control circuit 584 are connected to area 7. The buffer RAM 581 is a readable / writable memory and requires a refresh operation because of a dynamic memory, but is known to be inexpensive. The buffer RAM 581 describes the address arrangement. The buffer RAM 581 has a storage capacity of 2 MB (16 Mbits), and 1 Mbyte is used as a work buffer for the CPU 502, and the remaining is a 512 kB ring buffer.

  The system further includes a line feed motor 590 and a carriage return motor 591. These motors 590 and 591 are provided with an output of a timer 506 and an output of a pulse output device 507 via a buffer circuit 92, respectively. Controlled by. The line feed motor 590 and the carriage return motor 591 are stepping motors although not particularly limited.

  The DMAC 511 built in the microcomputer 501 outputs print data, and outputs a pulse for driving the line feed motor 590 and the carriage return motor 591. The DMAC 511 controls transfer of SCI 508 transmission data and reception data.

  Although not shown, the SCI 508 is used for communication with a host or the like, and the A / D converter 509 inputs sensor information such as the number of sheets.

  The EXDMAC 512 receives data by a plurality of transmission / reception circuits 580 such as a Centronics interface and a universal serial bus in parallel with the operation of the CPU 502. A transfer request signal is input to the EXDREQ input, and at the time of transfer, single address transfer can be performed by EXDACK output. For example, input strobe signal of Centronics interface is input to EXDREQ0, dual address transfer is performed on channel 0, reception signal of option interface is input to EXDREQ1, EXDACK1 output is given to option interface, and single address transfer is performed on channel 1 I do.

  The EXDAMC 512 can use either the destination or the source as a data register of the EXDMAC 512 instead of a memory or an internal I / O register in the address space. This selection is performed by a predetermined control bit of the control register of the EXDMAC 512.

  Prior to substantial data transfer, transfer information such as a packet command is transferred to the data register of the EXDMAC 512. The CPU 502 analyzes this information and, for example, if it only needs to be received continuously with the previous data transfer, set the destination as the memory, set the transfer count register, and start up. That's fine.

  In analyzing the information, for example, when the transfer information is 16 bytes, the transfer information can be stored in a general-purpose register by executing “MOVM.L @ EXD0DR0, ER0-3”. . Note that EXD0DR0 is a label indicating the start address of the data register of channel 0 of EXDMAC 512. In the MOVM instruction, a unique address can be easily accessed using an absolute addressing mode. If transfer data is stored in the buffer RAM 581 without using the EXDMAC 512 data register, “MOV.L @ EXDAR0, ER4, MOVM.L @ -ER4, ER0-3” may be used. . EXDAR0 is the label of the destination address register of channel 0. The destination address register indicates an address to be a destination for the next data transfer. The contents are stored in the general-purpose register ER4, and the pre-decrement register indirect addressing mode is used. By indirectly handling the address, an unfixed address on the memory can be easily accessed.

  Further, since the buffer RAM 581 is continuously read, the high speed page mode of the buffer RAM 581 and the like can be effectively used to increase the speed.

  By storing the transfer information in the general-purpose register at high speed and performing analysis on the general-purpose register, it is possible to shorten the time from reception of the transfer information to the start of processing based on the transfer information. As a result, it can contribute to speeding up the system.

  In the above system, when the printer status is read from the host side, the CPU 502 writes the status to the EXD2DR of channel 2 as needed, and outputs the status to the transmission / reception circuit 580 in accordance with the EXDREQ2 input. To the host. Also in this case, if there is a lot of data to be set, EXD2DR can be set using the MOVM instruction.

  For example, the CPU 502 sets a status indicating waiting for transfer information to EXD2DR0-7. When the transfer information of the packet command is received from the host, the busy status is set to EXD2DR0-7, the analysis of the transfer information is finished, and when the setting of EXDMAC 512 is completed, the status indicating data reception waiting is set to EXD2DR0-7. Like that. The host may transmit the transfer information and data while checking the status as needed.

  Print data on the buffer RAM 581 can also be manipulated. The speed can be increased by using a multiple register transfer instruction (MOVM) in various addressing modes. By prohibiting the transfer of the bus right with a multiple register transfer instruction, it is possible to suppress an undesired data change due to a conflict with the data transfer of the other DMACs 511 and EXDMAC 512.

  Note that, by improving the integration degree of the semiconductor integrated circuit, a part of the receiving circuit other than the option, the print control circuit 584, and the like can be integrated into one semiconductor integrated circuit. Further, a general-purpose memory such as the buffer RAM 581 can be integrated in one semiconductor integrated circuit. What is changed for each microcomputer system, such as the model of an individual printer, such as the program ROM 583 and the CGROM 582, is more preferably an individual semiconductor integrated circuit.

  According to the microcomputer and data processing system of FIG. 79 described above, the following operational effects can be obtained.

  [1] By transferring data between a plurality of general-purpose registers and memories or between a plurality of general-purpose registers with a single instruction, the number of instruction code reads can be relatively reduced and speeded up. it can. Further, by continuously reading / writing data, a burst operation for an external memory can be used effectively. When a plurality of bus masters process data, it is prohibited to transfer the bus right at the time of data access, thereby avoiding undesired data conflicts.

  The effective address of the transfer instruction is calculated only once, and the address buffer AB has an increment (or decrement) function and a function to hold the increment (or decrement) result, thereby simplifying the instruction operation and transferring Many controls for instructions can be shared with existing transfer instructions, and an increase in the logical scale of the instruction decoder DEC can be minimized. Speeding up can be achieved by reducing the number of effective address calculations. In addition, various addressing modes can be used in common, and an increase in logical scale can be minimized.

  By supporting multiple instructions with different numbers of registers in multiple register transfer instructions, and supporting multiple instructions with different data sizes such as word size and longword size, program creation is easy. Usability of the computer can be improved.

  In an architecture in which only the general-purpose registers can be processed directly by the CPU, the processing speed can be greatly improved by speeding up the transfer between the general-purpose registers and the memory.

  By providing a transfer instruction between a plurality of general-purpose registers and an address (memory) in the address space with a combination of a plurality of general-purpose registers fixed, even if the data is larger than the bit length of the general-purpose register, It can be handled easily, improves the usability of the microcomputer, and reduces the frequency of instruction read for data read / write, thereby speeding up data processing.

  Even if it is an existing CPU, the instruction code for instructing the transfer of multiple registers and the instruction code of the transfer instruction of an existing single general-purpose register are combined to realize a transfer instruction for multiple general-purpose registers. Can be easily added.

  [2] When the general-purpose register can be divided and there is a functional difference between the divided parts, a transfer instruction that uses the entire general-purpose register and a transfer instruction that uses the divided part are provided. Since it can be transferred to a general-purpose register that is easy to use, the processing can be facilitated and speeded up.

  If there is a CPU with a wide address space and a CPU with a small address space, or a CPU with a long general register bit length and a CPU with a short general register bit length, while maintaining compatibility at the object level, the latter A transfer instruction that can be used without waste to the CPU can also be provided.

  [3] A register group is specified by a prefix instruction code, the prefix instruction code can be omitted, and the instruction code when no prefix instruction code is added is the same as the instruction code of an existing CPU. Thus, the number of general-purpose registers can be increased without impairing compatibility.

  If only the implicitly specifiable general-purpose registers (existing general-purpose registers) are used, the optional word can be omitted, so the instruction code is not increased (at least the conventional general-purpose registers are used) In this case, the same instruction code may be used). By not increasing the instruction code, the processing speed is not reduced.

  By adding the omissible word, all of the general-purpose registers can be directly selected by an instruction, so that there are few parts that impair the ease of programming. In addition, by securing a part of an arbitrary amount of general-purpose registers for each desired task or desired interrupt processing (not used for other tasks or processing), the general-purpose registers can be set in the task or interrupt processing. There is no need to evacuate and speed up is achieved. In addition, since the number of general-purpose registers reserved for the task and interrupt processing can be arbitrarily set, it is easy to interchange the general-purpose registers to be used between tasks and processing.

  The general-purpose register that can be specified by adding the word can be accessed at a higher speed than the access of the memory such as the RAM. The processing speed of the CPU can be improved by enabling transfer between the register and the memory at high speed. For processors that have a so-called load store type instruction set and cannot directly operate on the memory contents, the amount of data that can be directly processed can be increased, and the memory access speed can be increased. Speed can be improved.

  When the number of general-purpose registers that can be specified by a multiple register transfer instruction is increased, it can be easily handled.

  [4] When there is a CPU having a wide address space and a CPU having a small address space while maintaining compatibility at the object level, a size corresponding to the address space (for example, 32 bits, MOVM. L instruction) for the general-purpose register and the transfer instruction for the general-purpose register of a size (for example, 16 bits, MOVM.W instruction) corresponding to the address space of the CPU having a small address space. The above transfer instruction can be easily realized even by a CPU having a backward compatibility and a small address space. In other words, by using the same method, it is possible to realize a transfer instruction for a plurality of general-purpose registers even with a CPU having a large address space and a CPU having a small address space while maintaining compatibility at the object level.

  By including the instruction set of the existing CPU at the source program level or the object program level and adding the above instructions, the software assets can be used effectively, and the software development efficiency of the user is improved. Can do. Both of the advantages of maintaining compatibility at the source program level or the object program level and the advantages of adding the transfer instruction can be enjoyed.

  [5] By making the existing CPU and the software development apparatus available in common and providing a means for selecting the CPU, it is possible to suppress undesired costs of the user. Further, since the C compiler and the like can improve the functions in common, the development efficiency of the software development apparatus can be improved. By improving the development efficiency, it is possible to reduce the resources required for development, and use the reduced resources to allocate functions.

  The existing CPU and the emulation interface can be shared, and the same emulator hardware can be shared. By making the interface for emulation common and the hardware of the emulator in common, the development environment can be quickly prepared, and the resources necessary for emulator development can be minimized.

  The embodiment of the invention relating to the means for solving the examination subject E is merely an example, and various modifications can be made without departing from the scope of the invention.

  For example, the CPU instruction set, register configuration, and address space can be changed. The CPU architecture is not limited to the load store architecture. However, it is desirable to have register means that can be used at a higher speed than most of the address space. The detailed specifications of the transfer instruction of a plurality of registers can be variously changed. The data size may have a byte size. Various modifications can be made to the logical configuration of the CPU and the logical implementation method of the transfer instruction of the plurality of registers. The address buffer may have a decrement function instead of increment, and may be accessed from the larger address. Furthermore, the internal bus width, internal bus configuration, and the like can be changed. Furthermore, CPUs that should maintain compatibility may differ in address space and the number of general-purpose registers, and may have different instruction sets as defined by instruction type, addressing mode, and data size. Good.

  There are no restrictions on other functional blocks of the microcomputer. An application field that is a data processing system is not limited to a printer. The EXDMAC and the like are shown as preferred examples, and needless to say, various changes can be made.

  In the above description, the case where the invention made mainly by the present inventor is applied to the single chip microcomputer which is the field of use behind the invention has been described. The present invention can be widely applied to data processing apparatuses such as system LSIs and system-on-chip VLSIs. The present invention can be applied to at least a data processing apparatus that decodes and processes instructions and performs arithmetic processing.

<< Effects of Invention on Examination A >>
The effects of the invention relating to the examination subject A are as follows. That is, the register specification field for specifying the general-purpose register is divided into two parts, these two parts are arranged in different words on the basic unit of the instruction code, and one word can be omitted, and can be omitted. If the word is omitted, an implicit specification is made. The optional word has only a part of the register specification field, and does not specify the type of operation. Therefore, if only general-purpose registers that can be specified implicitly are used, omissible words can be omitted, so the instruction code is not increased and the instruction code is not increased, thereby reducing the processing speed. There is no.

  By adding the omissible word, all of the general-purpose registers can be directly selected by an instruction, so that the programability is not impaired. In addition, by securing a part of an arbitrary amount of general-purpose registers for each desired task or desired interrupt processing (not used in other tasks or processing), the general-purpose registers can be set in the task or interrupt processing. There is no need to evacuate and speed up can be achieved. Furthermore, since the number of general-purpose registers reserved for the task and interrupt processing can be arbitrarily set, it is easy to interchange general-purpose registers to be used between tasks and processing.

  By adding the word, a general-purpose register that can be specified can be accessed generally faster than a memory such as a RAM. Therefore, by increasing the number of general-purpose registers, the amount of data that can be processed at a high speed is increased. The processing speed of the CPU can be improved. For processors that have a so-called load / store type instruction set and cannot directly operate on the contents of memory, the amount of data that can be directly processed can be increased by increasing the number of general-purpose registers. Can be reduced, and the processing speed can be improved.

<< Effects of Invention Regarding Examination Problem B >>
The effects of the invention relating to the examination subject B are as follows. In other words, one or a plurality of existing instruction codes for transfer between memory and registers, and a plurality of instruction codes among arithmetic instruction codes between registers and registers are combined, and a pre-instruction code is pre-coupled thereto. When executing the memory-register transfer instruction code combined with the prefix instruction code, it is not a general-purpose register, but is not released in the program like the temporary register in the CPU (in other words, the instruction code Data transfer is performed between the latch means and the memory. Further, when the operation instruction code between the register and the register coupled to the prefix instruction code is to be continuously executed, one or a plurality of data in the operation object is read from the latch means. When storing the operation result in the memory, the memory address used when the code of the transfer instruction is executed is stored in another latch means, and the operation result of the operation instruction is stored in the latch means. In addition, the code for the transfer instruction between the memory and the register is generated by itself (that is, generated even if it is not explicitly specified in the program), and the latch is stored with the operation result by using the content of the latch means storing the address as the address. The contents of the means are written as data into the memory.

  At this time, since the instruction code of the transfer instruction between the memory and the register and the operation instruction between the register and the register are already existing for the data processing apparatus, the execution of the instruction code alone operates in the same manner as in the past. Does not impede execution. Therefore, existing software assets that use only existing instructions can be effectively used. The data processing apparatus can achieve functional improvement while maintaining upward compatibility with respect to software assets.

  In addition, it retains the merits of existing general-purpose registers or load / store architecture, and the prefixed instruction code can be used in common regardless of the addressing mode and the contents of the operation. Can do.

  Instructions for reading data from the memory to the latch means, operations, and write operations to the memory based on the contents of the latch means are different from the existing instructions only in the registers used. Can be used without change.

  As a result, it is possible to minimize the increase in the logical scale due to the effective use of the design assets and the operation on the data on the memory.

  By making the data in the memory operable, the amount of data that can be directly processed can be increased, saving / restoring of general purpose registers can be omitted, and the processing speed can be improved.

  When there is a CPU with a wide address space and a CPU with a small address space while maintaining compatibility at the object level, the CPU adds a word and combines existing transfer instructions and arithmetic instructions with a CPU with a wide address space. As a result, it is possible to directly calculate data on the memory even with a CPU having a low compatibility and a small address space. In other words, by using the same method, while maintaining compatibility at the object level, it is possible to directly calculate data on the memory even with a CPU having a wide address space and a CPU having a narrow address space.

  It is possible to enjoy both the advantages of maintaining compatibility at the object level and the advantages of allowing the data on the memory to be directly operated.

  Since a new instruction function is realized by combining existing instructions, a margin for future function expansion and speeding up can be maintained at the same level as an existing CPU.

  In addition, the existing CPU and the emulation interface can be shared, so that the hardware of the same emulator can be shared. By making the emulator hardware common, it is possible to quickly establish a development environment and minimize the resources required for emulator development.

<< Effects of Invention on Examination Problem C >>
The effects of the invention relating to the examination subject C are as follows. That is, by providing a plurality of data processing devices, for example, CPUs including different instruction sets such that one does not include the other in terms of register configuration, combinations of instructions and addressing modes, etc., software requirements in various application fields It is possible to select an instruction set CPU that is relatively close to other CPU assembly language programs in response to various user preferences, and to facilitate the transition to a CPU with improved functions. .

  While preparing an upper CPU having an instruction set that includes any CPU for a plurality of CPUs, one of which does not include the instruction set of the other, enabling effective use of software assets A CPU with improved performance / function can be prepared. Effective utilization of software assets can improve the development efficiency of software development for users.

  The host CPU prepares an operation mode for switching the number of effective address bits, vector and stack unit sizes, or effective address calculation methods, for example, a maximum mode, a quasi-maximum mode, and a minimum mode. It is possible to make it upward compatible, including how to use.

  In the development, a general-purpose register is expanded with respect to an existing CPU (a CPU that becomes a lower CPU), and a higher-level CPU in which a combination of an instruction and an addressing mode is expanded is developed. The lower CPU will have a subset of the upper CPU instruction set. This can improve performance, function, usability and the like while minimizing an increase in the logical scale of the upper CPU, and also facilitates development of the other lower CPU and improves development efficiency. When developing an upper CPU of the upper CPU, compatibility with the plurality of CPUs can be automatically maintained if compatibility with the upper CPU is maintained. It becomes easy to realize a CPU that improves future functions and performance while realizing the effective use of. In other words, it is possible to provide a plurality of CPUs suitable for individual application fields and systems, reduce the overall development cost of the plurality of CPUs, and improve the development efficiency.

  In order to extend the general-purpose register, the register specification field that specifies the general-purpose register is divided into two parts, these two parts are placed in separate words on the basic unit of the instruction code, and one word is omitted. Yes, if an optional word is omitted, an implicit specification is made. An optional word has only a part of the register specification field and does not specify the type of operation. This allows omissible words to be omitted if only general-purpose registers that can be implicitly specified are used. Since a new instruction code specifying the expanded process is not individually added, the instruction code does not increase (the number of bits of the instruction code does not increase), and the instruction execution processing speed does not decrease. By adding the optional instruction code, all of the general-purpose registers can be selected according to the instruction, so that the ease of programming is not impaired. In addition, by securing a part of an arbitrary amount of general-purpose registers for each desired task or desired interrupt processing (not used in other tasks or processing), the general-purpose registers can be set in the task or interrupt processing. There is no need to evacuate and speed up can be achieved. In addition, since the number of general-purpose registers reserved for the task and interrupt processing can be arbitrarily set, it is easy to interchange the general-purpose registers to be used between tasks and processing.

  In general, register access is faster than memory access. By increasing the number of general-purpose registers, the amount of data that can be processed at high speed can be increased, and the processing speed of the CPU can be improved.

  In order to expand the combinations of instructions and addressing modes, one or more of existing transfer instructions between memory and registers, arithmetic instructions between registers and registers, and instructions that combine and combine multiple instruction codes Adopt extension prefix instruction code. When an instruction between memory and register is executed following the pre-instruction code for instruction extension, it is not a general-purpose register, but between a latch means such as a temporary register in the CPU that is not released in the program and the memory. To transfer data. Further, when a calculation instruction between registers and registers is subsequently executed, one or a plurality of pieces of data to be calculated are read from the latch means. When storing the operation result in the memory, the memory address used in the transfer instruction is stored in another latch means, the operation result of the operation instruction is stored in the latch means, and between the memory registers The transfer instruction is generated by itself (that is, generated even if not specified in the program), the contents of the latch means storing the address are used as addresses, and the contents of the latch means storing the operation results are used as data. Write to.

  At this time, since the instruction codes of the transfer instruction between the memory and the register and the operation instruction between the register and the register are already existing, the operation code alone does not hinder the execution of the existing instruction. Therefore, it is possible to effectively use existing software assets that use only existing instructions. The data processing apparatus can achieve functional improvement while maintaining upward compatibility with respect to software assets.

  A bit-length program counter corresponding to the entire address space is provided so that the entire address space, at least most of which can be used linearly for programming, and data transfer addressing to the extent that relatively small data can be handled By reducing the mode or limiting the data size of the transfer data, the logical scale can be reduced without impairing usability in a desired application field.

  By reducing the usable address space or the efficient usable address space during data access and dividing the address space into two, compatibility in the address space with the host CPU is maintained without deteriorating usability. In addition, software compatibility can be maintained by preparing in advance an operation mode for switching the effective address calculation method and the like to the host CPU.

  By expanding the address space for the program, suitability for programming using a high-level language such as C language can be improved. In addition, by making the stack pointer switchable, an undesired increase in the capacity of the stack during task management such as an OS can be suppressed.

  As for the development device, a software development device for the instruction set of the upper CPU is prepared. Further, the development device can be commonly used for a plurality of CPUs, one of which does not include the other instruction set. By enabling the CPU to select the CPU, the development efficiency of the software development apparatus can be improved. For the user, even if a plurality of CPUs are used, since the software development apparatus is common, it is not necessary to generate undesired costs. Migration among the plurality of CPUs is facilitated, and development efficiency can be improved.

  By allowing a plurality of types of descriptions of general-purpose registers having general-purpose functions, such as assembly language, on the software development apparatus, migration from another CPU can be made relatively easy.

  As for the emulator, the upper CPU and the lower CPU can share the emulation interface, and by developing the emulation logic circuit for the upper CPU, it can be used for the lower CPU. The development efficiency including the processor can be improved. In addition, the hardware of the same emulator can be shared, so that the development environment can be quickly established and the resources required for emulator development can be minimized. As the disassembler installed in the emulator is developed for the host CPU and means for selecting the target CPU on the emulator is provided, one disassembler can be practically used. It can be improved.

<< Effects of Invention on Examination D >>
The effects of the invention relating to the examination subject D are as follows. In other words, by combining the existing instruction code or part of the word of the instruction code to realize the bit conditional branch instruction / bit conditional subroutine instruction, the existing software assets can be used without hindering the execution of the existing instruction. Will be available to you. Further, while maintaining compatibility with existing CPUs, an increase in logical and physical scale can be minimized. Further, it is possible to determine the state of the bit of data at an arbitrary address on the memory, and to enable branching and subroutine branching. In addition, it is possible to contribute to improving the usability of the CPU, shortening the instruction code length, and improving the processing performance. In particular, it is possible to realize a reduction in program capacity and an improvement in processing speed of processing for changing the branch destination and the processing content according to the state of a plurality of bits.

<< Effects of Invention on Examination Problem E >>
The effects of the invention relating to the examination subject E are as follows. In other words, by providing a transfer instruction between a plurality of general-purpose registers and memories, or between a plurality of general-purpose registers, even data larger than the bit length of the general-purpose registers can be handled easily, improving usability. With respect to data read / write, it is possible to reduce the frequency of instruction read and increase the speed.

  By transferring data between a plurality of general-purpose registers and memories with a single instruction, it is possible to relatively reduce the number of instruction code reads and speed up data processing. Further, by continuously reading / writing data, a burst operation for an external memory can be used effectively.

  By using a fixed combination that specifies multiple general-purpose registers, the instruction code length can be shortened. Furthermore, by fixing the number of execution states of each instruction, internal conditional branching is eliminated, and internal logic Can be simplified and the logical scale can be reduced.

  Combines the instruction code that instructs the transfer of multiple registers with the instruction code of an existing single general-purpose register transfer instruction to realize a transfer instruction for multiple general-purpose registers, and is shared with a single general-purpose register transfer instruction By performing the optimized operation, an increase in logical scale can be minimized. The addressing mode of the transfer instruction of the existing single general-purpose register can be commonly used. By making available an addressing mode for an existing single general-purpose register transfer instruction, it is possible to facilitate program creation and improve usability.

  The effective address of the transfer instruction is calculated only once by the arithmetic unit, and the instruction operation is simplified by providing an increment (or decrement) function and an increment (or decrement) function in the address buffer. Thus, it can be shared with existing transfer instructions, and an increase in logical scale can be minimized. Speeding up can be achieved by reducing the number of effective address calculations.

  Supporting multiple register transfer instructions with different numbers of registers, and supporting multiple register transfer instructions with different data sizes, such as word size and longword size, make program creation easier, Usability can be improved.

It is a block diagram which illustrates in detail the CPU of the single chip microcomputer based on the invention regarding the examination subjects A, B, and C. It is a block diagram of a single chip microcomputer which is an example of a data processor concerning examination subjects A, B, and C. It is explanatory drawing which shows the structure of the general purpose register | resistor and control register which are incorporated in CPU. It is explanatory drawing which shows the structure of the general purpose register | resistor and control register in 1st downward compatible CPU. It is explanatory drawing which shows the structure of the general purpose register and control register in 2nd downward compatible CPU. It is explanatory drawing regarding the address space of CPU. It is explanatory drawing which shows the effective address calculation method in the maximum mode of the high-order CPU2 with FIG. It is explanatory drawing which shows the effective address calculation method in the maximum mode of the high-order CPU2 with FIG. It is a format figure which shows an example of the instruction format of the machine language of CPU. It is explanatory drawing which illustrates the detailed command format of the transfer command with respect to the memory of CPU. It is explanatory drawing which illustrates the form of the pre-instruction code which does not use an immediate as an instruction format of a direct operation instruction with respect to memory data, EA1, EA2, and an operation. It is explanatory drawing which illustrates the form of the front instruction code | cord | chord and EA1 and EA2 which do not use an immediate as an instruction format of the direct transfer instruction | command with respect to memory data. It is explanatory drawing which illustrates the form of the front instruction code which uses immediate as an instruction format of a direct arithmetic instruction with respect to memory data, EA2, and an operation (immediate). It is explanatory drawing which illustrates the form of the front instruction code which uses immediate as an instruction format of a direct transfer instruction with respect to memory data, EA2, and transfer (immediate). It is a format figure which illustrates the format of a prefix instruction code. It is explanatory drawing which showed the combination of the addressing mode of CPU regarding a data transfer command. It is explanatory drawing which showed the combination of the addressing mode of CPU regarding an addition command. It is a block diagram which shows the detail of a part of register selector and an instruction register. It is explanatory drawing which shows a part of selection logic of a register selector with FIG. 20 by logic description. FIG. 20 is an explanatory diagram showing a part of selection logic of the register selector together with FIG. 19 by a logical description. FIG. 23 is an explanatory diagram showing an example of selection logic of a register selector relating to a register that can also be used as a stack pointer, together with FIG. FIG. 22 is an explanatory diagram showing an example of selection logic of a register selector related to a register that can also be used as a stack pointer, together with FIG. It is explanatory drawing of the logic description which illustrates the decoding logic of the transfer instruction code (mov) contained in an instruction decoder with FIG.24 and FIG.25. It is explanatory drawing of the logic description which illustrates the decoding logic of the transfer instruction code (mov) contained in an instruction decoder together with FIG. 23 and FIG. It is explanatory drawing of the logic description which illustrates the decoding logic of the transfer instruction code (mov) contained in an instruction decoder with FIG.23 and FIG.24. It is explanatory drawing which shows the decoding logic of the operation instruction code (exe) contained in an instruction decoder with FIG. It is explanatory drawing which shows the decoding logic of the operation instruction code (exe) contained in an instruction decoder with FIG. FIG. 31 is an explanatory diagram showing decoding logic of an instruction code (mov.st) included in the instruction decoder and performing the same operation as an internally generated write type transfer instruction. FIG. 31 is an explanatory diagram showing the decoding logic of an instruction code (mov.st) included in the instruction decoder and performing the same operation as an internally generated write-type transfer instruction together with FIGS. 28 and 30. FIG. 30 is an explanatory diagram showing the decoding logic of an instruction code (mov.st) included in the instruction decoder and performing the same operation as an internally generated write type transfer instruction together with FIGS. 28 and 29. It is an operation | movement timing diagram which illustrates the execution timing of the addition instruction | command which does not accompany a prefix instruction code. It is an operation | movement timing diagram which illustrates the execution timing of the addition instruction to which the prefix instruction code for register expansion is added. A prefix instruction code having a register group field, a prefix instruction code of a memory / register type operation, MOV. W @aa: 16, an instruction code corresponding to R0, and ADD. FIG. 10 is a timing diagram illustrating operation timing when an instruction regarded as one instruction is executed by combining instruction codes corresponding to W R0 and R1. It is a timing chart showing an execution timing of a register memory type addition instruction (ADD.WR1, @aa: 16). It is a timing chart showing the execution timing of a memory / memory type addition instruction (ADD.W @ ER1, @aa: 16). It is a timing chart showing the execution timing of a memory-memory type transfer instruction (MOV.W @ ER1, @aa: 16). FIG. 10 is a timing chart showing execution timing of an immediate memory type addition instruction (ADD.W # xx, @aa: 16). FIG. 10 is a timing chart showing the execution timing of an immediate memory type transfer instruction (MOV.W #xx, @aa: 16). FIG. 42 is an explanatory diagram showing another example of the logic description regarding a part of the decoding logic of the operation instruction code (exe) included in the instruction decoder DEC, together with FIGS. 40 and 41. FIG. 42 is an explanatory diagram showing another example of the logic description regarding a part of the decoding logic of the operation instruction code (exe) included in the instruction decoder DEC together with FIGS. 39 and 41. FIG. 41 is an explanatory diagram showing another example of the logic description regarding a part of the decoding logic of the operation instruction code (exe) included in the instruction decoder DEC together with FIGS. 39 and 40. It is explanatory drawing which shows the outline of the development environment of CPU. It is explanatory drawing which illustrates the CPU selection method in the system development apparatus of CPU. It is explanatory drawing which shows an example of the list | wrist which the assembler of CPU outputs. It is a block diagram of the emulator for microcomputers. It is explanatory drawing which illustrates the trace list by the emulator for CPU. It is a block diagram which shows an example of the processor for emulation of a microcomputer. It is explanatory drawing which shows another programming model of a 2nd low-order CPU. It is explanatory drawing which shows another example of the address map of CPU. FIG. 52 is an explanatory diagram illustrating, together with FIG. 51, a method for calculating an effective address in the address map of the second lower CPU shown in FIG. 49. FIG. 50 is an explanatory diagram illustrating, together with FIG. 50, an effective address calculation method in the address map of the second lower CPU shown in FIG. 49. Prefix instruction code for instruction expansion, MOV. FIG. 10 is a timing chart when an instruction regarded as one instruction is executed by combining an instruction code corresponding to W #xx, R0 with an instruction code added with the destination information. It is a block diagram which shows an example of CPU which the microcomputer of the invention regarding the examination subject D has. FIG. 54 is an explanatory diagram illustrating an instruction format of a bit test instruction in the CPU of FIG. 53; FIG. 57 is an explanatory diagram showing an instruction format of a bit conditional branch instruction in the CPU of FIG. 53 together with FIGS. 56 and 57; FIG. 57 is an explanatory diagram showing an instruction format of a bit conditional branch instruction in the CPU of FIG. 53 together with FIGS. 55 and 57; 57 is an explanatory diagram showing an instruction format of a bit conditional branch instruction in the CPU of FIG. 53 together with FIGS. 55 and 56. FIG. FIG. 54 is an explanatory diagram exemplifying combinations of instruction codes in another instruction format when a bit conditional branch instruction in the CPU of FIG. 53 is considered. It is explanatory drawing which illustrates the logic structure of the determination circuit of temporary data register TRD, and a branch control logic by a logic description. FIG. 67 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC with respect to a part of a bit test instruction and a bit conditional branch instruction (first word) in a logical description together with FIGS. 61 and 62; FIG. 65 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a bit test instruction and a part (first word) of a bit conditional branch instruction with a logical description together with FIGS. 60 and 62; FIG. 62 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a bit test instruction and a part (first word) of a bit conditional branch instruction with a logical description together with FIGS. 60 and 61; FIG. 66 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a part of a conditional branch instruction by a logical description together with FIGS. 64 and 65; FIG. 66 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a part of a conditional branch instruction by a logical description together with FIGS. 63 and 65; FIG. 65 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a part of a conditional branch instruction with a logical description together with FIGS. 63 and 64; FIG. 69 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a part of a subroutine branch instruction with a logical description together with FIGS. 67 and 68; FIG. 69 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a part of a subroutine branch instruction with a logical description together with FIGS. 66 and 68; FIG. 68 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for a part of a subroutine branch instruction with a logical description together with FIGS. 66 and 67; FIG. 71 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC with respect to another operation instruction by using a logical description together with FIG. 70. FIG. 70 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC with respect to another operation instruction in conjunction with FIG. 69 by a logical description. FIG. 75 is an explanatory diagram illustrating a logical configuration of an instruction decoder DEC for another operation instruction in conjunction with FIG. 72 by a logical description. FIG. 72 is an explanatory diagram illustrating the logical configuration of the instruction decoder DEC with respect to another operation instruction as well as the logical description together with FIG. 71; It is a timing chart which illustrates the execution timing of the 1st example (BBS # 0, @FFFFFE, $ + 20) of a bit condition branch instruction. It is a timing chart which illustrates the execution timing of the example (BBSR # 5, @ FFFE00, $ + 300) of a bit condition subroutine branch instruction. It is a timing chart which illustrates the execution timing of the 1st example (BTST # 0, @FFFFFE) of a bit test instruction. It is a timing chart which illustrates the execution timing of the 2nd example (BTST # 1, @ ER0 +) of a bit test instruction. It is a timing chart which illustrates the execution timing of the example (BSET # 2, @ ER0 +) of a bit set instruction. It is a timing chart which illustrates the execution timing of the 2nd example (BBC # 0, @ ER0 +, $ + 20) of a bit condition branch instruction. It is a block diagram of the microcomputer which is an example of the data processing apparatus which concerns on this invention of the examination subject E. It is explanatory drawing which shows the address space of CPU. It is explanatory drawing which illustrates the function of the transfer instruction (MOVM) of multiple general purpose registers. It is explanatory drawing which illustrates the data arrangement | positioning of the data transfer by the transfer instruction (MOVM) of a multiple general purpose register. It is explanatory drawing which illustrates the prefix instruction code (prefix instruction code for instruction expansion) which shows instructions, such as a transfer instruction (MOVM) of a multiple general purpose register. It is a block diagram which shows a detailed example of CPU which is an example of the data processor which concerns on invention of examination or the subject E. FIG. It is a block diagram which shows the detail of a part of register selector and an instruction register. It is explanatory drawing which illustrates the function of the control signals s1-s3 input into a register selector. It is a block diagram which illustrates an address buffer. It is explanatory drawing which shows a part of decoder control logic with respect to the transfer instruction (MOV and MOVM instruction) of the word size between a register and a register by a logic description. FIG. 89 is an explanatory diagram of the remaining logical description following FIG. 88. It is explanatory drawing which shows a part of decoder control logic with respect to the transfer instruction (MOV and MOVM instruction) by a 16-bit absolute address by a logic description. FIG. 91 is an explanatory diagram of the remaining logical description following FIG. 90. 92 is an explanatory diagram of the remaining logical description following FIG. 91. FIG. 90 is a flowchart corresponding to a control operation by a register-register transfer instruction (MOV and MOVM instruction) under the control of the logical description shown in FIGS. 88 and 89. FIG. 93 is a flowchart corresponding to a control operation by a transfer instruction (MOV and MOVM instruction) with a 16-bit absolute address by the control of the logical description shown in FIGS. 90 to 92; Register-register type first transfer instruction (MOV.L ER0, ER1), second transfer instruction (MOV.L ER8, ER17), and first example of multiple register transfer instruction (MOVM.W R0- It is a timing chart which illustrates the execution timing of R1, E28-E29). It is a timing chart which illustrates the execution sequence of the 2nd example (MOVM.L @aa: 16, ER0-ER1) of the transfer instruction of a plurality of registers. It is a timing chart which illustrates the execution sequence of the 3rd example (MOVM.W R10-R11, @ ER6) of the transfer instruction of a plurality of registers. It is explanatory drawing which illustrates the outline of the development environment of CPU. It is a block diagram which illustrates the processor for emulation of a microcomputer. 1 is a block diagram illustrating a microcomputer system using a microcomputer for printer control.

Explanation of symbols

1 Single-chip microcomputer 2 CPU
3 interrupt controller 30 internal bus 31 interrupt request signal DEC instruction decoder 200 pf decode logic 201 mov decode logic 202 exe decode logic CHG instruction change unit IR1, IR2 instruction register mskint interrupt mask signal mod (MODS, MODD) modify control signal mkmov Instruction code generation signal EXEC Execution unit INTC Interrupt control unit RSEL Register selector RDB Read data buffer WDB Write data buffer TRA, TRD Temporary register PC Program counter ER0 to ER7 General purpose register AB Address buffer GB, WB, DB bus IDB Internal data bus IAB Internal address bus ALU arithmetic logic unit 2A CPU
bc bit condition field 36 branch control signal 37 branch control logic 38 decision circuit AU arithmetic logic unit 501 microcomputer 502 CPU
510 bus controller r1, r2 register field gr1, gr2 optional instruction code register field LGR1, LGR2 latch circuit for gr1, gr2 in the instruction register LAT1, LAT2 latch circuit for gr2, r2 in the register selector LOG1, LOG2 register selector Control logic of s1 and r2 in s1 to s3 Control signal of register field value

Claims (10)

A data processing device that operates by reading an instruction code included in an instruction set,
The instruction set includes a branch instruction that reads data on an address space and performs a branch in response to a predetermined bit of the data being in a predetermined state,
The branch instruction is configured to include information that is multiple times the basic unit of an instruction code,
The first basic unit information of the branch instruction indicates a process of reading the designated data on the address space and storing it in the latch means not released for programming,
The second basic unit information of the branch instruction is a data processing device for inspecting a predetermined bit of data stored in the latch means and instructing whether to branch according to the inspection result. The first basic unit information can be used from a plurality of types according to a data designation method in the address space,
The second basic unit information can be used from a plurality of types according to a branch destination address designation method.
The data processing device according to claim 1, wherein the branch instruction instructs an operation according to a combination of types of the first basic unit information and the second basic unit information. A flag means for reflecting the calculation result;
The second basic unit information can function as an independent conditional branch instruction, and when functioning as the independent conditional branch instruction, inspects a predetermined bit or bits of the flag means, The data processing apparatus according to claim 1 or 2, wherein an instruction to branch according to the inspection result is given. A data processing device that operates by reading an instruction code included in an instruction set,
The instruction set includes a transfer instruction for performing data transfer between the memory and the register, and a branch instruction for inspecting a predetermined bit of data stored in the register and performing an operation of whether to branch according to the inspection result,
Latch that is not released for programming by reading the prefix instruction code, the instruction code of the transfer instruction, and the instruction code of the branch instruction sequentially, interpreting them as one instruction, reading the specified data in the address space A data processing apparatus for checking whether a predetermined bit of data stored in the means and stored in the latch means is checked and branching according to the check result.   5. The data processing apparatus according to claim 4, further comprising flag means for reflecting an operation result, wherein the transfer instruction interpreted as one instruction together with the prefix instruction code suppresses change of the flag means. Bit inspection means coupled to the latch means;
The bit check means outputs a check result according to a predetermined bit of the branch instruction interpreted as one instruction together with the prefix instruction code,
6. The data processing apparatus according to claim 4, wherein the branch instruction interpreted as one instruction together with the prefix instruction code determines whether or not to branch in response to the output of the inspection result. A decoding means for decoding the instruction code;
5. The decoding means decodes the transfer instruction interpreted as one instruction together with the prefix instruction code, and generates a control signal for instructing an operation change to an instruction code of a subsequent branch instruction. The data processing device according to any one of 1 to 6.   When executing the transfer instruction and the branch instruction interpreted as one instruction together with the prefix instruction code, between the process specified by the instruction code of the transfer instruction and the process specified by the instruction code of the branch instruction 8. The data processing apparatus according to claim 4, wherein insertion of interrupt processing is prohibited. A data processing device that operates by reading an instruction code included in an instruction set,
The instruction set includes a compound instruction that reads data on the address space and performs data processing using the read data,
The compound instruction is configured to include information multiple times the basic unit of an instruction code,
The first basic unit information of the compound instruction instructs a process of reading specified data on the address space and storing it in a latch means that is not released for programming,
The second basic unit information of the compound instruction is a data processing device that instructs predetermined data processing using data stored in the latch means.   10. A data processing apparatus according to claim 9, wherein the latch means is a temporary data register or a temporary address register.

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