JP2001337821A - Data processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve process efficiency for a bit-operation especially keeping bit condition as a parameter even when a program is made by high level language. SOLUTION: This data processing device uses a designated bit of a designated general register for instance bit 0 of a general register R0L as a bit-accumulator, simultaneously supports a process that upper sides 7 bits are cleared in '0'. At this time for instance data processing device stores the bit n1 of a byte data in an address aa1 in bit 0 of the general register R0L, at the same time it can execute an instruction of the processing which clears bit7-1 in '0' ('BLDS #n1,(1)a1'). Under this constitution, 'flag = iop17' is realized by 'BLDS #7, (9)op1' and 'MOV. B R0L, (6)lag' and it is possible to contribute to the simplification of the program and reducing a program capacity and speeding up.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the efficiency of processing involving bit operations such as bit transfer and bit operation in a data processing device such as a microcomputer, for example, a microcomputer integrated into a semiconductor integrated circuit, a microprocessor, The present invention relates to a technology which is effective when applied to a data processor such as a data processor or a CPU, particularly a data processor incorporated in a device.

[0002]

2. Description of the Related Art Increasingly, microcomputer programs composed of semiconductor integrated circuits are described in a high-level language such as the C language.

In device control, processing is often performed using data in bit units for peripheral functions such as an I / O port of a microcomputer. For example, the program is branched by referring to the input state of the I / O port. Also, a desired value is output to the I / O port to realize device control.

[0004] The CPU of the microcomputer has a so-called bit operation instruction so as to easily operate the data in bit units. Bit operation instructions include a bit test (BT) for checking the state of bit data.
ST) instruction, an instruction for changing the value of predetermined bit data, for example, a bit set (BSET) instruction for setting a specified bit value to “1”, and clearing a specified bit value to “0” Bit clear (BCLR) instruction,
And a bit knot (BNOT) instruction for inverting the value of a designated bit. Furthermore, there is a case where a carry (C) flag is used as a bit accumulator and has an instruction to perform bit transfer or bit operation. For example, a bit load (BLD) instruction that transfers a designated bit of a general register or memory operand to a carry flag;
There is a bit store (BST) instruction for transferring the contents of the carry flag to a designated bit of a general-purpose register or a memory operand.

[0005]

For example, as bit manipulation processing, when the state of a first bit is determined and the second bit is set / cleared in accordance with the determination result, the bit test instruction is used. # N1, @ aa1 BEQ L1 BSET # n2, @ aa2 BRA L2 L1: BCLR # n2, @ aa2 L2: This is the address $ a
The value of the n1th bit of the data of a1 is determined.
Clear the n2th bit of the data of a2 to “0”,
If the result of the determination is "1", the n2th bit of the data at the address $ aa2 is set to "1" and the process exits to the label L2.

If bit transfer instructions BLD and BST using the carry (C) flag as a bit accumulator are used in the above processing, the processing can be performed by a simpler program such as BLD # n1, $ aa1 BST # n2, $ aa2. And can contribute to a reduction in program capacity and an increase in speed.

When describing a source program in the C language, bit data is declared as a bit field, that is, as a structure. For example, each bit of the I / O port IOP1 is And so on.

[0008] On the other hand, the parameter is defined as unsendend char flag; Character type parameter flag
Is a byte size and is usually arranged on a RAM.
The contents of bit 7 of the IOP1 are stored in the parameter fl
In a process corresponding to flag = iop17 ;, which is a description to be substituted for ag, the value of the bit of iop17 is unsignedly extended to the byte size (the upper 7 bits are set to 0) and stored in the flag area. This is the process.
This process is described in MOV. B # 00, R0L BLD # 7, {iop1 BST # 0, R0L MOV. BR0L, $ flag, etc. That is, “0” is transferred to the register R0L,
Load bit 7 of Iop1 into carry flag (C) and store carry flag (C) in bit 0 of register R0L.
And transfers the value of the register R0L to the area of the address $ flag. Even microcomputers having bit transfer instructions (BLD, BST) are not necessarily efficient because of the need to perform unsigned extension.
That has been found by the present inventors.

As described above, it is good if the data can be directly transferred to the address $ flag. However, if the storage destination is an array or the like and an address calculation is required, the C flag used as the bit accumulator is Because the result of the calculation is reflected and may change undesirably,
It is necessary to save to a general-purpose register or change the execution order. Given this situation, C
It is easy to avoid compromising the development efficiency of the compiler.

An object of the present invention is to store a bit operation, particularly a bit state, as a parameter or the like in a data processing device such as a microcomputer for controlling devices even when a program is created in a high-level language such as C language. It is to realize the improvement of the processing efficiency in the case.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] The data processing device uses a predetermined bit of a predetermined general-purpose register, for example, bit 0 of the general-purpose register R0L, as a bit accumulator, and simultaneously clears the upper 7 bits to “0”. , Support processing. At this time, the data processing device can execute, for example, an instruction (first predetermined instruction) that can be expressed as “BLDS # n1, @ aa1”. This instruction is an instruction for storing the bit n1 of the byte data at the address aa1 in the bit 0 of the general-purpose register R0L and clearing the bits 7-1 to "0".

When the instruction set has the bit load (BLD) instruction using the carry (C) flag as a bit accumulator, circuit means for extracting a predetermined bit in the execution of the BLDS instruction is used in common with the BLD instruction.
A circuit for storing the extracted bits in bit 0 and generating data in which the upper bit is set to “0” is provided.
A write signal may be generated.

[0015] The data processing apparatus is provided with a "BSTS #
The instruction “BSTS # n2, $ aa2” instructs to store bit 0 of the general-purpose register R0L in bit n2 of the byte data of the address aa2. At this time, the upper bits of the general-purpose register R0L are ignored, and the address aa
The other two bits are retained.

When the instruction set has a bit store (BST) instruction for transferring the contents of the carry flag (C) to the designated one bit of the general-purpose register, bit 0 of the general-purpose register R0L is output in the execution of the BSTS instruction. A new function can be added, and the function of inserting into a predetermined bit can be made common.

If there is room in the instruction code or the like, other general-purpose registers may be used in the BLDS instruction and BSTS instruction without fixing the general-purpose register to R0L. When manipulating multiple bits,
Easy programming.

In the BLDS instruction and BSTS instruction, the bit accumulator is replaced with the general-purpose register R.
It may be made possible to select whether to use a 0 bit or a carry (C) flag. Only one of the microcomputer and the compiler is provided with the selecting means (CPU
CR setting). It can also maintain compatibility with existing programs.

According to the BLDS instruction, the "fla"
g = iop17; "can be BLDS # 7, $ iop1 MOV.BR0L, $ flag, which can be a simpler program, which can contribute to reduction in program capacity and speeding up.

As long as the general-purpose register R0L is not used, there is no problem in performing the address calculation, and the development efficiency of the C compiler is hardly impaired.

[2] In a further preferred example, as a bit transfer instruction, a specific bit of a second desired address, for example, bit 0, from a predetermined bit of a first desired address
And the instruction to clear the upper 7 bits to 0 may be executed at the same time. For example, such an instruction (a second predetermined instruction) can be represented as BLDMOV # n1, $ aa1, $ aa2. This instruction stores bit n1 of the byte data at address aa1 in bit 0 of the byte data at address aa2, and sets bits 7-1 to 0.
To be cleared. By the BLDMOV instruction, the "flag = iop17;" can be changed to BLDMOV # 7, $ iop1, $ flag, which can be a simpler program, which can contribute to reduction in program capacity and speeding up. General-purpose register R
The transfer can be performed without using 0L, and the program efficiency can be improved.

[3] In another example, as a bit transfer instruction, a predetermined bit of a first desired address is transferred to a second predetermined bit of a desired address. Good. This command (third predetermined command)
Can be expressed as, for example, BMOV # n1, # aa1, # n2, # aa2. This instruction stores bit n1 of the byte data at address aa1 in bit n2 of the byte data at address aa2, and holds the other bits. That is, BLDS instruction and BS
The TS instruction is the same instruction. Only the necessary bit data of the byte data of the RAM or the like is used to hold the state of the bit of the I / O port, and the other bits of the byte data can be effectively used for other purposes.
For example, the efficiency of using a memory can be improved. This is particularly effective when programming is performed in an assembly language or the like. In C language, etc., RAM
By declaring a bit field as a structure with parameters and the like to be stored in the memory, a plurality of bits can be arranged in one byte in the RAM, and the amount of RAM used can be reduced. This is effective in a so-called single chip mode in which only the built-in memory operates.

Further, bit 0 of the general-purpose register R0L
In addition, since a bit accumulator such as a carry (C) flag is not used, program efficiency can be improved and usability can be improved.

As an extended instruction of this example, an instruction using one of the memories as a general-purpose register can be supported. That is, as an instruction using the destination side as a general-purpose register, the instruction of BMOV # n1, $ aa1, # n2, Rd is stored in bit n1 of byte data of address aa1.
Is stored in the bit n2 of the byte data of the general-purpose register Rd, and the other bits are held.

As an instruction using the source side as a general-purpose register, the instruction of BMOV # n1, Rs, # n2,.
1 is stored in the bit n2 of the byte data at the address aa2, and the other bits are held.

Further, the instructions of BMOV # n1, Rs, # n2, and Rd are instructions using the source side and the destination side as general purpose registers.
1 is stored in the bit n2 of the byte data of the general-purpose register Rd, and the other bits are held. By supporting these instructions, restrictions between instructions and the designation of data to be used are eliminated or reduced, and programmability can be improved.

[4] In the case of a bit transfer instruction, an instruction execution function (bld-1, bst-1) for transferring data from a source / destination memory to latch means (TRD, DBR) inside the CPU, and a general-purpose register Alternatively, a predetermined bit is extracted from the latch means (bld, bm
ov1), and an instruction execution function of substituting a bit accumulator or the like into a predetermined bit (bst, bmov2) may be combined.

The instruction execution function for transferring data from the memory is shared, and the instruction execution function for performing the bit operation itself is shared with the bit operation instruction for the general-purpose register, thereby reducing the logic scale and the development period. Can be achieved.

At least one of the latch means (TR
D) has a function of extracting and outputting a desired bit and a function of storing only the desired bit, so that load / store with the bit accumulator can be performed without complicating the logical configuration and operation of the ALU. By the same operation as described above, bit transfer between arbitrary bits can be realized.

In the instruction execution function for transferring data from the memory, the effective address of the memory is stored in another latch means (TRA), and the instruction execution function for performing the bit operation itself stores the result in the latch means. (T
RD). Subsequently, a transfer command function to the memory is internally generated, and the content of the latch means storing the address is used as an address, and the content of the latch means storing the operation result is used as data to write to the memory. . Data reading from the memory to the latch means and writing to the memory based on the contents of the latch means can be shared with existing instructions, so that the existing instruction operation is not significantly changed and the increase in logical scale is minimized. can do.

When the bit accumulator is selected, a development device such as a compiler has means for selecting the bit accumulator, and based on this selection, the program to be executed by the CPU is made different. do it.

[0032]

FIG. 2 shows a configuration example (programming model) of general-purpose registers and control registers incorporated in a CPU (for example, a CPU 1 shown in FIG. 4 described later) which is an example of a data processing apparatus according to the present invention. ).

The CPU has eight 32-bit general-purpose registers. The general-purpose registers all have the same function, and can be used as both an address register and a data register.

As a data register, 32 bits,
Can be used as 16-bit and 8-bit registers. The address register and the 32-bit register are collectively used as general-purpose registers ER (ER0 to ER7). As a 16-bit register, a general-purpose register ER
Is divided and used as general-purpose registers E (E0 to E7) and general-purpose registers R (R0 to R7). These have the same function, and up to 16 16-bit registers can be used. As an 8-bit register, the general-purpose register R is divided into general-purpose registers RH (R0H to R7
H), used as general-purpose registers RL (R0L to R7L). These have equivalent functions and can use up to 16 8-bit registers. The method of use can be selected independently for each register.

Bit 0 of general-purpose register R0L has a function as a bit accumulator. In the case of a bit accumulator, upper bits other than bit 0 are set to “0” at the time of writing and ignored at the time of reading.

The general-purpose register ER7 is assigned a function as a stack pointer (SP) in addition to the function as a general-purpose register, and is used implicitly in exception processing and subroutine branching. Exception processing includes interrupt processing.

PC is a 24-bit program counter which indicates the address of an instruction to be executed next by the CPU 1. Although not particularly limited, since the instructions of the CPU 1 are all in units of 2 bytes (words), the least significant bit is invalid, and the least significant bit is regarded as 0 when the instruction is read.

CCR is an 8-bit condition code register which indicates the internal state of the CPU 1. It is composed of 8 bits including an interrupt mask bit (I) and flags of half carry (H), negative (N), zero (Z), overflow (V) and carry (C). The carry flag (C) has a function as a bit accumulator in addition to an operation as a carry for carry / borrow and shift / rotate in an arithmetic operation.

EXR is an 8-bit register that controls exception processing such as interrupts. Interrupt mask bit (I
2 to I0) and trace (T).

For an example of a data configuration on a general-purpose register, a data configuration on a memory space, an addressing mode and a method of calculating an effective address, see “H8S / 2600 Series H8S / 200” issued by Hitachi, Ltd. in March 1995.
0 Series Programming Manual ”.

As the bit accumulator, it is possible to select whether to use the bit 0 of the register R0L or to use the carry (C) flag of the CCR. The selection is specified by a predetermined bit of a control register CPUCR described later.

FIG. 1 illustrates the contents of bit transfer instructions (BLDS, BSTS, BLDMOV, BMOV) included in the instruction set of the CPU 1 as an example of the data processing apparatus according to the present invention.

The BLDS instruction is “BLDS # n1,
<EA1> ”. R0L
Is a bit accumulator, the designated bit of the source data is stored in bit 0 of the general-purpose register R0L, and the upper bit is set to 0. The source data is a general-purpose register or a memory, and is specified by <EA1>.
The designation bit designates the bit number by n1.

The BLDMOV instruction is "BLDMOV #
n1, <EA1>, <EA2>". Similar to the BLDS instruction, but the result is stored not in the general-purpose register R0L but in the destination location. The destination location is <EA2>. It is specified.

The BSTS instruction is “BSTS # n2,
<EA2> ”. R0L
Is a bit accumulator, the general-purpose register R0
The bit 0 of L is stored in the designated bit of the destination data. The upper bits of R0L are ignored, and the other bits of the destination data are retained. The location of the destination is a general-purpose register or a memory, and is specified by <EA2>. The designation bit designates the bit number by n2.

The BMOV instruction is “BMOV # n1, <
EA1>, # n2, <EA2>". The designated bit of the source data is stored in another designated bit of the destination data. The other bits of the source data are ignored and the destination bit is ignored. The source and destination locations are general-purpose registers or memories, and are designated by <EA1> and <EA2>, respectively. The bit numbers are designated by n1 and n2, respectively.

FIG. 3 shows bit transfer instructions (BLDS, BSTS, BLDMO) which are (1) bit 0 fixed transfer instructions.
V) and (2) a bit transfer instruction (BM
OV) instruction format.

The BLDS instruction stores a predetermined bit of data on a general-purpose register or an address space in a bit accumulator (C or R0L [0]).

The BSTS instruction stores a bit accumulator (C or R0L [0]) in predetermined bits of data on a general-purpose register or an address space, and retains other bits.

As for the addressing mode, typically, only the case of direct register and the case of an absolute address of 8 bits are shown.

In the case of a direct register, an operation field (op) indicating the function of each instruction, a bit field (n) for specifying a bit number, and a register field for specifying a general-purpose register are indicated by a one-word instruction code. (R) 4 bits.

When the absolute address is 8 bits, an operation field (op) and an absolute address (EA) which is an EA extension are included in the first word with a 2-word instruction code.
The second word has an operation field (op) and three bits of a bit field (n) for designating a bit number, similarly to the register directly.

When the second word is shared with the register direct instruction code, 4 bits of the register field (r) indicating the location of the data become unnecessary. The bit accumulator is not limited to the general-purpose register R0L, but may be any register specified by the register specification field (r). That is, the BLDS instruction stores a predetermined bit of data on the general-purpose register or the address space in bit 0 of the designated general-purpose register, and sets the upper bit to 0. Flexible use is possible rather than limiting the bit accumulator to the general-purpose register R0L. Specifically, when a plurality of bits are manipulated, a plurality of general-purpose registers can be used correspondingly.

The contents of the operation field are set as appropriate to define each instruction.

The bit transfer instruction BMOV between arbitrary bits is as follows. 2 between registers
In an instruction code of a word, the first word has an operation field (op) and a register field (r) for designating a general-purpose register, 4 bits, and the second word has an operation field (op), a source field, and a destination field. It has a bit field (n) for specifying a bit number, each three bits.

A bit transfer instruction between a memory and a general-purpose register requires two register specification fields and two bit specification fields, and cannot be realized by a one-word instruction code.
In the case of a two-word instruction, it is equivalent to a combination of a BLDS instruction and a BSTS instruction. Therefore, the bit transfer instruction between the general-purpose registers does not need to be defined, but the defined one holds the bit accumulator. Since the combination of the instruction function and the addressing mode can be arbitrarily set, it is easy to use and the program efficiency can be improved.

FIG. 4 shows a configuration example of the CPU 1 which is an example of the data processing apparatus according to the present invention.

CPU 1 has an instruction control section (instruction control means) 2 for performing instruction fetch and instruction decoding to generate a control signal.
And an execution unit (instruction execution means) 3 for executing an instruction by performing an operation based on the control signal.

The instruction control section 2 includes an instruction register IR, an instruction change section CHG, an instruction decoder DEC, a register selector RSEL, and an interrupt control section INT.

The internal data bus ID is stored in the instruction register IR.
Instructions are loaded from B. The loaded instruction is decoded by the instruction decoder DEC. Instruction decoder DEC
Is, for example, a micro ROM or a PLA (Program).
(M. Logic Array) or wired logic. A part of the output of the instruction decoder DEC is fed back to the instruction decoder DEC. This is the stage code (TMG) used for the transition in each instruction code
And control signals (MODS, MOD
D).

FIG. 4 conceptually illustrates some functions of the instruction decoder DEC. The transfer instruction code (bld-1, bst-1, mov-st) is composed of a state code signal (nxttmg) and an interrupt mask signal (i
ntmsk), memory read signal (read), memory write signal (write), temporary register read / write signal (TRDr / w, TRAr / w: t described later)
rdgb, wbtrd, bittrd, etc.) and a control signal (mod: including MODS, MODED described later).

The operation instruction code (exe: bld-
0, bst-0, bldst-0, bmov-0a, b
mov-0b) is an interrupt mask signal (intms
k), source general register read signal (Rsrd), destination general register read / write signal (R
dr / w), general-purpose register R0L read / write signal (R0Lr / w: includes r0lgb, wbrol described later), carry flag set signal (Cset), read data buffer read signal (DBRrd: dbrg described below)
b), a temporary register read / write signal (TRDr / w: including trdgb and wbtrd described later), an ALU control signal, and a control signal (mkmov) for internally generating a data transfer operation.

The instruction decoder DEC receives a bit accumulator selection signal, and switches between a general-purpose register R0L read / write signal and a carry flag set signal. Further, the input source / output destination of the data to be used is switched by the control signals MODS and MODED. In the case of the destination-side memory (MODD = 1), a signal (mkmov) for generating an instruction code for performing an operation equivalent to a write-type transfer instruction internally is output. Further, predetermined bit fields (n1, n2 in FIGS. 1 and 3) are provided to the arithmetic and logic unit ALU and the temporary register TRD.
The details of the instruction decoder DEC and the instruction execution will be described later.

The instruction register IR temporarily stores the read instruction. The instruction to be executed is output to the instruction decoder DEC.

The instruction change unit CHG operates when an instruction code other than the read instruction is given to the instruction decoder DEC, and otherwise gives the contents of the instruction register IR to the instruction decoder DEC. Instruction codes other than the read instruction are used when an exception process such as an interrupt is executed according to an instruction from the interrupt control unit INT, and when the instruction decoder D
The instruction code (mov-m-v) that performs the same operation as the write-type transfer instruction internally in accordance with the instruction (mkmov) of the EC
It is used when generating (st).

The interrupt controller INT accepts an interrupt request signal output from an interrupt controller 32 shown in FIG. 14 described later. Also, referring to the interrupt mask signal output from the instruction decoder DEC, if the interrupt is not masked, the interrupt is instructed to the instruction changing unit CHG.

A plurality of instruction codes (words having an operation field) as shown in FIGS.
Are executed as a series of instructions, each instruction code indicates an interrupt mask so that execution of a predetermined combination of instruction codes is not interrupted by interruption.

The register selector RSEL selects a general-purpose register based on the instruction of the instruction decoder DEC and the information of the register field included in the instruction code.
When the general-purpose register R0L is used as a bit accumulator, it can be directly specified from the instruction decoder DEC.

The execution unit 3 includes general-purpose registers ER0 to ER
7, a program counter PC, a condition code register CCR, temporary registers TRA and TRD, an arithmetic and logic unit ALU, a branch address operation unit AU, an incrementer INC, a read data buffer DBR, a write data buffer DBW, and an address buffer MA.
These blocks are interconnected by a GB bus, a DB bus, and a WB bus. The temporary data register TRD has a bit input / output function.

General-purpose registers ER0 to ER shown in FIG.
7, except for the program counter PC and the condition code register CCR, they cannot be referenced on programming.
Used only for operation inside the microcomputer. That is, the read data buffer DBR, the write data buffer DBW, the address buffer MA, and the like temporarily latch data in order to interface with the internal address bus IAB and the internal data bus IDB. The temporary registers TRA and TRD are appropriately used for the operation inside the microcomputer.

The read data buffer DBR is a ROM,
Instruction codes and data read from a RAM, an internal I / O register, or an external memory (not shown) are temporarily stored.

The write data buffer DBW has ROM, R
Write data to the AM, internal I / O register, or external memory is temporarily stored.

Address buffer MA temporarily stores an address to be read / written by the CPU.

The arithmetic and logic unit ALU is used for various operations specified by instructions, calculation of effective addresses, and the like. The incrementer INC is a program counter PC
Used for the increment of.

Each unit of the execution unit 3 is divided corresponding to division E (16 bits), H (8 bits) and L (8 bits) of the general-purpose register. When performing bit transfer to the memory, the registers TRA, TRD,
DBR or the like is used.

The temporary register TRA stores a read address when reading the destination address in the case of a BSTS or BMOV instruction in which the destination data becomes a memory, and stores the read address when writing data to the destination memory. (The same address as the read address) is output.

The temporary register TRD temporarily stores the source data in the case of a BLDS or BSTS instruction in which the source data becomes a memory, and outputs the source data when the operation instruction code is executed. When the destination data is a BSTS or BMOV instruction that becomes a memory, the operation result is temporarily stored, and write data is output when the data is written to the destination memory.

Further, the read data buffer DBR temporarily stores the destination data when the destination data is an operation instruction that becomes a memory, and outputs the source data when the operation code is executed. These registers TRA, TRD, and DBR also operate as appropriate in other cases, but detailed description is omitted.

FIG. 5 is a block diagram showing a portion related to a bit transfer instruction of the arithmetic and logic unit ALU. Illustration of other ALU functions is omitted.

The arithmetic and logic unit ALU includes a decoder 10,
Selector 11, input selector 12, input selector 13,
Logical operation circuit 14, zero detection circuit 15, output selector 1
6 inclusive. These are controlled by control signals (not shown). The decoder 10 inputs information (bn) indicating a bit number included in the instruction code, and generates a pattern in which only designated bits are set to 1 and other bits are set to 0.

The selector 11 has a carry flag (C).
And bit 0 (DB [0]) of the internal bus DB, and any input is selected by a bit accumulator selection signal. When the general-purpose register R0L is used as a bit accumulator, the contents of the general-purpose register R0L are output to the internal bus DB at a predetermined timing.

The input selector 12 inputs the internal bus GB and the output (decout) of the decoder 10. The input selector 13 includes a bit accumulator (bacc) output from the selector 11, a designated bit (trdbit) of the register TRD, and an output (d
ecoout).

The logic operation circuit 14 includes the input selector 1
A predetermined logical operation is performed on outputs 2 and 13. The zero detection circuit 15 generates a logical sum of all bits of the output of the logical operation circuit 14. The output selector 16 outputs the output of the logical operation circuit 14 and the output of the zero detection circuit 15 (zoo
t) is input to output to the internal bus WB.

In the case of the BLDS instruction, the logical operation circuit performs an AND operation. Data input values are extracted only for the designated bits, and the other bits are set to 0. That is, aluin1 [7: 0] = data [7: 0] & dec
out [7: 0]; aluin2 [7: 0] = decout [7: 0];

The output of the logic operation circuit 14 is input to a zero detection circuit (logical sum circuit) 15. The output of the zero detection circuit 15 is the logical sum of all the bits with respect to the input, that is, zout = | (data [7: 0] & decout
[7: 0]); In the case of a BLD instruction, the output selector 16 outputs the output of the zero detection circuit 15 to bit 0 and makes a selection so that the other bits are set to “0”. That is, aboutout [7: 0] = {7′b00000000, z
out｝;

Further, an instruction to write the output of the output selector 16 to the general-purpose register R0L is issued. As described above, when an arbitrary general-purpose register can be used, a write to the general-purpose register specified by the instruction code is instructed.

When the result of the BLD instruction is stored in the general-purpose register R0L without sign-extending the upper bits instead of 0, the following equation is used: alouout [7: 0] = {zout, zou
t,. . . , Zout}; This is equivalent to writing the byte data H'00 or H'FF.

When a bit logical operation instruction is provided, data and a bit accumulator of only the selected bit are input to the arithmetic and logic unit ALU.
4 may be instructed to perform a predetermined calculation. The input selectors 12 and 13 of the logical operation circuit 14 are set as follows. That is, aluin1 [7: 0] = data [7: 0] & dec
out [7: 0]; aruin2 [7: 0] = bacc & decout
[7: 0];

In the case of the input selector 13, 1-bit ba
The cc is ANDed with each bit of 8-bit decount [7: 0] to obtain 8-bit aruin2 [7: 0]. Data in which the selected bit is set to the value of the bit accumulator and the other bits are set to 0 is input.

The result is detected by the zero detection circuit 15, that is, zout = | ((data [7: 0] <op> 8 ｛ba
cc｝) & decout [7: 0]); Here, <op> is a designated logical operation, which is a logical product, a logical sum, or an exclusive logical sum. Writing this to the general-purpose register R0L can be realized in the same manner as described above.

For the BSTS instruction, the logical operation circuit 1
The input selector 12 of No. 5 is set as follows. That is, aluin1 [7: 0] = data [7: 0] & ￣de
cout [7: 0]; The input selector 13 of the logical operation circuit 15 performs the same operation as the bit logical operation. That is, aluin2 [7: 0] = bacc & decount
[7: 0]; By instructing the logical operation circuit 15 to perform a logical product, the designated bit is used as a bit accumulator, and the other bits are used as input data, and bits are inserted. The output selector 16 outputs the operation result of the logical operation circuit 14. That is, each bit is: aloud = decout? 8 {back}:
data; In addition, symbol? Means that the signal before and after the signal delimited by the following symbol: is selected by decount.

The output of the arithmetic and logic unit ALU can be stored in a general-purpose register or written to a predetermined memory via a temporary register and a data write buffer.

The selector 11 of the bit accumulator is
Whether the carry flag (C) or bit 0 (R0L [0]) of the general-purpose register R0L is used as the bit accumulator is selected by a mode signal.

A bit transfer instruction between arbitrary bits (BMO
About V), it is as follows. In the case of the first mode,
The specified bit of the source data input to the arithmetic and logic unit ALU is detected by the zero detection circuit 15 and stored in another specified bit of the destination data stored in the temporary register TRD. That is, the outputs of the input selectors 12 and 13 are: alin1 [7: 0] = data [7: 0] & dec
out [7: 0]; aruin2 [7: 0] = decout [7: 0]; and the output of the zero detection circuit 15 is: zout = | (data [7: 0] & decout
[7: 0]); In place of the bit accumulator, the BL is stored in the designated bit of the temporary register.
Same as the DS instruction. Here, "decout" is obtained by decoding the bit number on the source side.

In the case of the second mode, the temporary register T
The designated bit (tr) of the source data stored in the RD
dbit) is stored in another designated bit of the destination data input to the arithmetic and logic unit ALU. The outputs of the input selectors 12 and 13 are: aluin1 [7: 0] = data [7: 0] & ￣de
cout [7: 0]; aruin2 [7: 0] = 8 {trdbit} & dec
out [7: 0]; and the output of the arithmetic and logic unit ALU is as follows: aluout = decout? 8 {trdbit}: d
ata; is the same as the BSTS instruction except that trdbit is used instead of bacc. Where deco
ut is obtained by decoding the bit number on the destination side.

In the first mode and the second mode, the bit numbers on the source side and the destination side in the instruction code are exchanged.
The bit position of the instruction code to be input to the.

FIG. 6 is a block diagram of the temporary register TRD. The temporary register TRD includes a decoder 20, an input selector 2
1, the output selector 23 is included. The output trdbit of the output selector 23 is supplied to the input selector 13 of FIG.

The decoder 20 inputs predetermined information (bm) indicating a bit number included in the instruction code, sets only designated bits to “1”, and sets other bits to “0”.
(Tdecout [7:
0]).

The designated bit of the register section 22 selected by the output selector 23 is represented by the following logical expression: trdbit = | (trd [7: 0] & tdecout
[7: 0]); That is, the logical product of the output of the decoder 20 and each bit of the register unit 22 is calculated, and the logical sum of all the bits is calculated. A selector is configured to extract a desired bit. This is used in the second mode of the bit transfer instruction (BMOV) between arbitrary bits. At this time, td
"ecout" is obtained by decoding the bit number on the source side. trd [7: 0] is an output of the register unit 22.

The input selector 21 converts the input value to the register unit 22 into casex (wbtrd, dbtrrd, bittrd) 100: trdin [7: 0] = wb [7: 0]; 010: trdin [7: 0] = 011: trdin [7: 0] = (8 {zout} & tdecout [7: 0]); | (db [7: 0] & @ tdecout [7: 0]); 001: trdin [7: 0] = (8 {zout} & tdecout [7: 0]); | (trd [7: 0] & @ tdecout [7: 0]); 000: trdin [7: 0] = trd [ 7: 0]; That is, the content of the internal bus WB is selected by the control signal wbtrd, and the control signal dbtr
By d, the contents of the internal bus DB are selected. Also,
The bit selected by the control signal bittrd is:
For the output of the zero detection circuit 15 and the other bits, the original value of the register unit 22 is selected. At the same time, the control signals (wbtrd, dbtrrd, bittrd)
Writing is performed in synchronization with a predetermined clock (￣φ).
This can be described as follows.

[0101] This is used in the first mode of the bit transfer instruction (BMOV) between arbitrary bits. At this time, tdecount is
This is a decoded bit number on the destination side.

The following is an example of the execution timing of the instruction of the present invention. Although there is no particular limitation, the internal data bus is 16 bits, and the built-in ROM and RAM can be read / written in one state. Built-in R
The OM and RAM use IAB as an address bus and IDB as a data bus. Although the later-described PAB and PDB are not connected, the same timing is internally generated. The operation timing described below is synchronized with the rising edge C1 of the clock signal φ and the falling edge C2 of the clock signal φ in each operation cycle Ti. Although not particularly shown, C2 is actually a timing synchronized with the rising edge of the inverted clock signal (or non-overlap signal) φ # of the clock signal φ.

The control signal output from the decoder DEC includes control A and control according to the phase.
olB and controlC, depending on the control target,
The phases are different.

Control A mainly performs bus control. It controls bus commands and address output.

The execution sequence is controlled by control
B, output of control signals TMG, MODS, and MODD, prohibition of interruption by control signal intmsk, and instruction code (m
ov-st), and the like. Also, it controls the reading of data input to the arithmetic and logic unit ALU.

The control signal controlC controls the arithmetic and logic unit ALU and instructs the operation result to be written in a general-purpose register or a temporary register. For example,
When the instruction is read, the control signal controlA
Is activated, and the next C2
, The following series of operations are performed. (1) The contents of the PC are read to the internal bus GB, transferred to the address buffer AB, and output to the address bus IAB. (2) A bus command indicating an instruction read (if) is output. (3)
The value of the program counter PC on the internal bus GB is taken into the incrementer INC, and +2 is specified. (4)
At the next C1 (φ synchronization), the incremented program counter PC value on the internal bus WB is written to the program counter PC.

FIG. 7 shows a first example of the bit transfer instruction (BL
DS # 7, @FFFFFE).

At C2 (φ # synchronization) of T0, an address signal is sent from address buffer MA of CPU 1 to address bus I.
Output to AB. At C1 (φ synchronization) of T1, the contents of the address bus IAB are output to the address bus PAB, and a read cycle is started. The read data is obtained on the internal data bus in C2, and this is latched in the instruction register IR in C1 of T2. This is the first word of the instruction code (bld-1), and stores the data at the specified address in the temporary register TRD.

Subsequently, the next address (+
Is output to the address bus IAB, and the read data is latched in the instruction register IR at C1 of T3. This is the second word of the instruction code (bl
d-0), the designated bit is stored in the accumulator. The above operation is performed by controlling the execution of the previous instruction, and the relative relationship may be different.

When the execution of the immediately preceding instruction is completed, if the execution of the instruction is started earliest after the instruction is read, T
2 and the instruction code (bld-1) is the instruction decoder D
It is input to the EC and the contents of the command are decoded. According to the decoding result, a control signal is output to control each unit. That is, since the addressing mode is an 8-bit absolute address, the source data is read based on the absolute address, and the read result is stored in a temporary register (TR).
D). In addition, the control signal MODS is set to 1 and the interrupt disable intmsk is set to 1.

At C2 of T2, the contents (absolute address) of bits 7 to 0 (IR [7: 0] = 8'hFE) of the first word of the instruction code are read out to the internal bus GB and input to the address buffer MA. I do. At this time, the upper bit is extended by one. An address signal is output from address buffer MA to bus IAB.

Data is read from T3. Also,
At C2 of T3, the contents of the program counter PC are read out to the internal bus GB and input to the address buffer MA and the incrementer INC. An address signal is output from address buffer MA to bus IAB.

At C1 of T4, the read data is stored in the read data buffer DBR. Further, the data is output from the read data buffer DBR to the internal bus DB and input to the arithmetic and logic unit ALU. The operation of the arithmetic and logic unit ALU is not operated. At C2 of T4, the read data is output from the arithmetic and logic unit ALU to the internal bus WB and stored in the temporary register TRD.

In C1 of T4, the instruction code (bld-0)
Is input to the instruction decoder DEC, and the control signal MODS
At the same time, the contents of the instruction are decrypted. According to the decoding result, a control signal is output to control each unit. MODS
Since the signal is set to 1, the designated bit of the temporary register TRD is transferred to the bit accumulator.

As described above, the control signal con for the C1 of T4.
In accordance with the instruction read by control A and the instruction of PC increment, the content of the program counter PC is read out to the internal bus GB at C2 of T4, and the address buffer MA
To the incrementer INC. An address signal is output from address buffer MA to address bus IAB. At C1 of T5, the result incremented (+2) by the incrementer INC is written to the program counter PC via the internal bus WB.

On the other hand, in control B of C2 of T4,
Indication of input data of arithmetic logic unit ALU (trd_g
b) is performed, and the ALU is
It outputs a control and register storage instruction (wb_r01). In accordance therewith, the contents of the temporary register TRD are read out to the internal bus GB and input to the arithmetic and logic unit ALU. The arithmetic and logic unit ALU performs the following operation (bld) to execute the BLDS instruction. The decoder 10 of the arithmetic and logic unit ALU includes bits 6 to 4 of the instruction code.
(Opcode [6: 4] = 7), and the input selector 12 of the arithmetic and logic unit ALU calculates the logical product of the output (decount = H'80) of the decoder 10 and the internal bus GB by the arithmetic and logic unit ALU. The input selector 13 outputs a decode output decount of the decoder 10 and performs an AND operation on these outputs. The result is obtained in the zero detection circuit 15 (zout = gb [7] = trd [7]).

When general-purpose register R0L is used as a bit accumulator, an instruction (wb_r01) for storing the contents of internal bus WB in R0L is issued. When the carry flag (C) is a bit accumulator, an instruction to store the result (zout) of the zero detection circuit 15 in the carry flag is performed instead of the control signal wb_r01.

Output selector 16 of arithmetic and logic unit ALU
As a result, output data (# 7'b00000000, {7'b00000000,
zout｝) is generated, and the internal bus WB is generated at C2 of T5.
Is output to The contents of the internal bus WB or the zero detection circuit 15 are stored in the general-purpose register R0L or the carry flag (C) according to the instruction.

At C1 of T5, the contents of the bus IDB (next instruction) are latched in the instruction register IR, and the decoder DEC
And the contents of the command are decoded. The operation is performed according to the decoding result. The instruction is read from C2 of T5.

As described above, since the first word and the second word are not divided, a continuous command signal (intmsk) is output from C2 of T2 to C2 of T4. With this signal, execution of an instruction can be continued even if an interrupt request or the like has occurred.

When a general-purpose register other than R0L is used, bits 3 to 0 (op [3: 0]) of the instruction code are decoded by the instruction decoder DEC, and the control signal wb_r01 is replaced with the control signal wb_r01 at C1 of T5. Thus, an instruction for inputting from the internal bus WB to the designated general-purpose register may be issued.

FIG. 8 shows a second example of the bit transfer instruction (BL
DMOV # 6, $ FFFFFD, $ FFFF00).

At C1 of T2, the instruction code (bld-1) is input to the instruction decoder DEC, and the contents of the instruction are decoded. This is similar to the first word of the BLDS instruction. At C1 of T4, the second word (bst-
1) is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the decoding result, output the control signal,
Control each part. That is, since the addressing mode is an 8-bit absolute address, the destination data is read based on the absolute address, and the read result is stored in the read data buffer DBR. The effective address (EA2 = FFFF00) used for reading is
The data is stored in the temporary register TRA at C1 of T5. It is also assumed that the control signal MODED = 1. The control signal MODS = 1 output from the first word is continued.

The instruction code (bldmov-
0) is input to the instruction decoder DEC, and the control signal MO
The contents of the instruction are decoded together with DS and MODD. According to the decoding result, a control signal is output to control each unit. Since the control signals MODS and MODD are set to 1, the control is performed so that the designated bit of the read data buffer DBR is set to bit 0, and the data whose upper bit is set to 0 is stored in the temporary register TRD. In the same manner as described above, the instruction is read by the control A of C1 at T5 and the program counter PC is incremented.

The control data of the arithmetic and logic unit ALU is designated (dbr_gb) by the control B of C2 of T5, and the control of the arithmetic and logic unit ALU and the instruction of the register storage (wb_gb) are performed by the control C of C1 of T5.
trd) is output. In accordance therewith, the contents of the read data buffer RDB are read out to the internal bus GB and input to the arithmetic and logic unit ALU. Arithmetic logic unit ALU is B
To execute the same operation as the LDS instruction, the following operation (b
ld). Decoder 10 of arithmetic logic unit ALU
Are bits 6 to 4 of the instruction code (IR [6: 4] =
6) is given, the input selector 12 of the arithmetic and logic unit ALU calculates the logical product of the decoder output (decout = H'40) and the internal bus GB, and the input selector 13 of the arithmetic and logic unit ALU outputs the decode output of the decoder 10. And output
These logical product operations are performed. The result is obtained in the zero detection circuit 15 (zout = gb [6] = dbr)
[6]).

Output selector 16 of arithmetic logic unit ALU
As a result, the output of the zero detection circuit 15 is set to bit 0, and the output data (data0 = $ 7'b0000
000, zout｝) is generated and output to the internal bus WB at C2 of T6. According to the instruction (wb_trd), the contents of the internal bus WB are stored in the temporary register TR.
D.

At C2 of T5, the instruction code (mov-s
generating a control signal that generates t), and the instruction code is:
Input from C1 of T6 to the instruction decoder DEC. This instruction code (mov-st) is stored in the temporary register TR
A is an address register and a temporary register TRD
Performs the same operation as the transfer instruction using. That is, at C2 of T6, the destination effective address (EA2) stored in the temporary register TRA is read to GB, output to the address bus IAB via the address buffer MA, and a bus command for byte data write is issued. I do. At C2 of T7, the operation result (data) stored in the temporary register TRD
o) is read out to the data bus DB, output to the data bus IDB via the write data buffer DBW, and the operation result is written to the memory address of the destination. The instruction is fetched from C2 of T7, and the program counter PC is incremented. As a result, in the second word (bst-1) of the instruction code, the portion that has not been subjected to the instruction fetch and the PC increment is recovered.

When writing to the destination side memory, the instruction code (mov-st) is generated inside the CPU 1 so that the instruction code can be shortened and the processing time can be shortened. By referring to the contents of the temporary register TRA, it is not necessary to calculate the effective address again, and the processing time can be further reduced. Existing transfer instructions (MOV.B R0L, @ER
By adopting an operation similar to 0), design can be facilitated. The first word (bl) of the instruction code
d-1) However, for the sake of commonality, the temporary register TR
A is being stored.

In the same manner as described above, a continuous instruction signal (intmsk) is output from C2 of T2 to C2 of T6 so that the first word and the second and subsequent words are not divided. With this signal, execution of an instruction can be continued even if an interrupt request or the like has occurred.

FIG. 9 shows a third example of the bit transfer instruction (BS
TS # 5, $ FFFF10).
At C1 of T2, the first word (bst-1) of the instruction code is input to the instruction decoder DEC, and the contents of the instruction are decoded. According to the decoding result, a control signal is output to control each unit. This is the same as the second word (bst-1) of the instruction code in FIG.

At C1 of T4, the second word (bst-0) of the instruction code is input to the instruction decoder DEC, and the contents of the instruction are decoded together with the control signal MODED. According to the decoding result, a control signal is output to control each unit. Since the control signal MODED is set to 1, control is performed such that bit 0 of the general-purpose register R0L is stored in the designated bit of the read data buffer DBR, and the other bits are stored and stored in the temporary register TRD. Perform

Similarly to the above, the control of C1 of T3
The instruction is read by A and the PC is incremented.

At the control B of C2 in T3, the instruction of the input data of the arithmetic and logic unit ALU (dbr_gb, r
0l_db) and controlC of C1 of T4
Then, the control for the arithmetic and logic unit ALU and the instruction for register storage (wb_trd) are output. According to this,
The contents of the read data buffer DBR are read out to the internal bus GB and input to the arithmetic and logic unit ALU. Further, the contents of the general-purpose register R0L are read out to the internal bus DB. The arithmetic and logic unit ALU performs the following operation (bst) to execute the BSTS instruction. The decoder 10 of the arithmetic and logic unit ALU has bits 6 to 4 of the instruction code (IR
[6: 4] = 5) and bit 0 of the internal bus DB (bit 0 of the general-purpose register R0L as a bit accumulator)
And the input selector 12 of the arithmetic and logic unit ALU
Calculates the logical product of the inversion of the output (decount = H'20) of the decoder 10 and the internal bus GB by the arithmetic and logic unit ALU.
Output selector 13 outputs a logical product (H'20 & 8 {DB [0]}) of the output of decoder 10 and the bit accumulator, and performs a logical product operation on these.

Output selector 16 of arithmetic and logic unit ALU
The result ($ 2'b00, DB [0], 5'b0000
0｝) is generated and output to the internal bus WB at C2 of T6. The content of the internal bus WB is the instruction (wb_tr)
According to d), it is stored in the temporary register TRD. At C2 of T4, a control signal for generating an instruction code (mov-st) is generated.
To the decoder DEC. This is the same as FIG.

FIG. 10 shows a fourth example of the bit transfer instruction (B
MOV # 6, $ FFFFFC, # 5, $ FFFF2
The execution timing of 1) is shown. Operations other than the third word of the instruction code are the same as those in FIG.

The instruction code (bmov-0) at C1 of T5
b) is input to the instruction decoder DEC and the control signal MO
The contents of the instruction are decoded together with DS and MODD. According to the decoding result, a control signal is output to control each unit. Since the control signals MODS and MODD are set to 1, the designated bit (bit 6) of the temporary register TRD is substituted for the designated bit (bit 5) of the read data buffer DBR, and the other bits are held. Control is performed so that the data thus obtained is stored in temporary register TRD. The arithmetic and logic unit ALU is a BMO
It operates in the second mode (bmov2) of the V instruction.

As described above, the control of C1 of T5
The instruction is read by A and the program counter PC is incremented.

The control data of the arithmetic and logic unit ALU is instructed (dbr_gb) by the control B of C2 in T3, and the control for the arithmetic and logic unit ALU and the instruction of register storage (wb_g) are performed by the control C of C1 in T4.
trd) is output. In accordance with this, the contents of the read data buffer DBR are read out to the internal bus GB and input to the arithmetic and logic unit ALU.

The arithmetic and logic unit ALU performs the following operation to execute the second mode of the BMOV instruction. The instruction code bits 6 to 4 (IR [6: 4] = 5) are given to the decoder 10 of the arithmetic and logic unit ALU, and the input selector 12 outputs the output of the decoder 10 (decout = H′2).
0) and the logical product of the internal bus GB and the input selector 13 outputs the output of the decoder 10 and the temporary register TRD.
And outputs the logical product (H'20 & 8 {trdbit}) of the designated bit (bit 6) trdbit, and performs the logical product operation on them.

The result (data0 =
｛DBR [7: 6], trdbit, DBR [4:
0]｝) is generated and output to the internal bus WB at C2 of T6. The contents of the internal bus WB correspond to the instruction (wb_t).
rd), it is stored in the temporary register TRD. At C2 of T4, a control signal for generating an instruction code (mov-st) is generated.
To the decoder DEC. This is the same as FIG.

FIG. 11 shows a fifth example of the bit transfer instruction (B
MOV # 4, #FFFFFB, # 3, R2L). The overall operation is substantially the same as in FIG. 7, and the operation of the first word (bld-1) of the instruction code is the same as in FIG.

The operation of the second word of the instruction code is roughly as follows.
10 is the same as FIG. 10 except that the designated general-purpose register (destination general-purpose register Rd = R2L) is read onto the internal bus GB, and the result (data0 = ｛R2L [7:
4], trdbit, R2L [2: 0]}) are stored in the designated general-purpose register (R2L), and the processing ends.

FIG. 12 shows a sixth example of the bit transfer instruction (B
MOV # 2, R3H, # 1, $ FFFF32). Operations other than the second word of the instruction code are the same as those in FIG.

At C1 of T4, the instruction code (bmov-0
a) is input to the instruction decoder DEC, and the control signal MO
The contents of the instruction are decoded together with the DD. Control signal MO
Since DD is set to 1, the designated bit (bit 2) of the designated general-purpose register (R3H) is replaced with the designated bit (bit 1) of the temporary register TRD.
Transfer to The arithmetic and logic unit ALU operates in the first mode of the BMOV instruction.

As described above, the control of C1 of T4
The instruction is read by A and the program counter PC is incremented.

At the control B of C2 of T3, the instruction of the input data of the arithmetic and logic unit ALU (rs_gb: R3
H3 is specified by r3h_gb), and the control C of C1 at T4 outputs an instruction (bittrrd) for controlling the arithmetic and logic unit ALU and storing the output of the zero detection circuit 15 in a register. In accordance therewith, the contents of the general-purpose register R3H are read out to the internal bus GB and input to the arithmetic and logic unit ALU.

The arithmetic and logic unit ALU performs the following operation (bmov1) to execute the first mode of the BMOV instruction. The decoder 10 of the arithmetic and logic unit ALU is provided with bits 6 to 4 (IR [6: 4] = 2) of the instruction code, and the input selector 12 outputs the output (deco
ut = H'02) and the logical product of the inversion of the internal bus GB and
The input selector 13 outputs the output of the decoder 10 and performs an AND operation on these outputs.

The result (zout = |
(R3H [7: 0] &H'02) = R3H [2]) is generated and stored in bit 1 of the temporary register TRD according to the instruction (bittrd) at C2 of T6. Other bits are retained and the result (data0
= {TRD [7: 2], zout, TRD [0]}).

At C2 of T4, the instruction code (mov-s
generating a control signal that generates t), and the instruction code is:
Input from C1 of T5 to the decoder DEC. This is the same as FIG.

FIG. 13 shows a seventh example of the bit transfer instruction (B
MOV # 7, R4H, # 6, R5L). The first word (mov-1) of the instruction code is
The designated general-purpose register (R4H) is transferred to the temporary register TRD. This is because the existing instruction (MOV.B
R4H, R0L) can facilitate design. The operation of the second word is the same as in FIG.

FIG. 14 shows a microcomputer incorporating the CPU as an example of the data processing apparatus according to the present invention.

The microcomputer 30 has the CPU
1, a system controller (SYSC) 31, an interrupt controller (INT) 32, a ROM 33 that stores a processing program of the CPU 1, a work area of the CPU 1, and a RAM 3 that is a memory for temporarily storing data.
4. It is composed of functional blocks or modules such as a timer 35, a serial communication interface (SCI) 36, an A / D converter 37, first to ninth input / output ports IOP1 to IOP9, and a clock oscillator (CPG) 38. Is formed on one semiconductor substrate by the semiconductor manufacturing technology.

The microcomputer 30 has, as power supply terminals, input terminals for ground level (Vss), power supply voltage level (Vcc), analog ground level (AVss), analog power supply voltage level (AVcc), and analog reference voltage (Vref). And dedicated control terminals such as reset (RES) and standby (STB).
Y), mode control (MD0, MD1), and clock input (EXTAL, XTAL) terminals. CPG3
The microcomputer 30 operates in synchronization with a reference oscillator (system clock) φ generated based on a crystal oscillator connected to the terminals EXTAL and XTAL or an external clock input to the EXTAL terminal. One cycle of the reference clock signal φ is called a state.

The functional blocks of the microcomputer 30 are interconnected by an internal bus 39. The internal bus 39 includes an address bus, a data bus, and a control bus to which a bus command, a read signal, a write signal, a bus size signal, and the like are transmitted. Although not specifically shown,
As described above, the internal address bus depends on its phase.
There are two types, AB and PAB, and the internal data bus also has IDB and PDB depending on the phase. IAB and PA
B, IDB and PDB are interfaced with each other. The data bus width of the internal bus is 16 bits. The CPU 1 makes the built-in ROM 33 and RAM 34 readable / writable in one state. Through such an internal bus 39, the CPU
1 reads / writes the functional blocks and modules.

The ROM 33 stores a processing program for the CPU 1. In the case of a flash memory or a mask ROM, in the case of a flash memory, a user can write data using a predetermined PROM writer. The mask ROM is written in a manufacturing process based on a predetermined object file provided by a user. The RAM 34 holds the parameters and the like.

System controller (SYSC) 31
Has a control register CPUCR that controls the entire state of the microcomputer 30 (operation mode and low power consumption state) and controls the CPU 1, and instructs whether to use a CCR or a general-purpose register as the bit accumulator. Is set.

Timer 35, SCI 36, A / D converter 3
7, input / output ports IOP1 to IOP9, SYSC31,
The control registers of the INT 32 and the CPG 38 are collectively called internal I / O registers. These include bits and flags that have meaning in bit units. For example, there are an output port and an interrupt factor flag. They are,
In a C language program, a bit field is declared as a structure and handled.

Each of the input / output ports IOP1 to IOP9 is also used as an address bus, a data bus, a bus control signal, or an input / output terminal of the timer 35, the SCI 36, and the A / D converter 37. That is, the timer 35, the SCI 36, A
The / D converter 37 has an input / output signal, and inputs / outputs to / from the outside via a terminal also used as an input / output port. For example, IOP5, IOP6, and IOP7 are also used as input / output terminals of the timer 35, and IOP8 is also used as input / output terminals of the SCI 36. An analog data input / output terminal is also used as an input / output port IOP9.

When a reset signal RES is given to the microcomputer 30, the microcomputer 30 including the CPU 1 is reset. When the reset is released, the CPU 1 reads a start address from a predetermined address and performs a reset exception process for starting reading an instruction from the start address. Thereafter, the CPU 1 sequentially reads and decodes the instructions from the ROM 33 or the like, and performs data processing or data transfer with the RAM 34, the timer 35, the SCI 36, or the like based on the decoded contents. That is, the CPU 1 sets the input / output port IOP1
Processing is performed based on instructions stored in the ROM 33 or the like with reference to data input from the IOP 9, the A / D converter 37 or the like, or instructions input from the SCI 36 or the like, and based on the result, , I / O port IOP1
A signal is output to the outside using the IOP9, the timer 35 and the like to control various devices.

The state of the timer 35, SCI 36, external signals, and the like can be transmitted to the CPU 1 as an interrupt signal. The interrupt signal includes an A / D converter 37, a timer 35,
CI36, input / output ports IOP1 to IOP9 output,
The interrupt controller (INT) 32 receives this and supplies an interrupt request signal to the CPU 1 based on the designation of a predetermined register or the like. When an interrupt factor occurs, an interrupt request signal is generated in the CPU 1, and the CPU 1 interrupts the process being executed at the break of the instruction, executes an exception processing state, branches to a predetermined processing routine, and executes a desired processing. And clear the interrupt factor. At the end of the predetermined processing routine, a normal return instruction is placed, and the interrupted processing is resumed by executing this instruction.

FIG. 15 shows an outline of a development environment of the CPU 1. The user can use various editors and the like to
Create a program in language or assembly language. This is usually created by dividing into a plurality of modules.

The C compiler 40 inputs each C language source program created by the user and outputs an assembly language source program or an object module. The assembler 41 inputs an assembly language source program and outputs an object module. The linkage editor 42 is a C compiler 40
And a plurality of object modules generated by the assembler 41, resolve external references and relative addresses of each module, combine them into one program,
Output the load module. The load module can be input to the simulator / debugger 43 to simulate the operation of the CPU 1 on a system development device such as a personal computer, display the execution result, and analyze and evaluate the program. Also, by inputting to the emulator 44, so-called in-circuit emulation that operates on an actual application system or the like is performed, analysis and evaluation of the actual operation of the entire microcomputer can be performed. Further, by inputting the load module to the PROM writer 45, the created program can be loaded into the case where the built-in ROM 33 of the microcomputer 30 is a flash memory or the like, or into an external flash memory or the like. If necessary, the data is converted into a desired format by an object converter or the like. In addition, a general-purpose subroutine can be provided as a librarian.

FIG. 16 exemplifies a method of specifying a bit accumulator in the system development device of the CPU 1. Here, a case where the instruction of the CPU 1 is selected is shown.

As illustrated in (a), while a prompt is displayed on a display on a system development apparatus such as a personal computer, for example, “SET C
PU = BITACC-R0L ".

Alternatively, as shown in (b), while a prompt is displayed, a command “SET CPU” is input, and in response to this, a menu of CPU type and operation mode is displayed, for example. “BITACC (1.B
ITACC-R0L, 2. BITACC-C) "and prompts the user to enter a menu number so that the user may enter any of menu numbers 1-2. If there are other options, continue to enter It should be possible.

In addition, selection may be made from a drop-down menu of a window, or a workstation or the like may be input as a C shell command. Such information is stored as a CPU information file (CPU definition information) and is referred to at the time of compiling as shown in FIG. Furthermore, selection of a bit accumulator or the like can be input as a control instruction of a source program such as an assembler or a C compiler.

Also, as an example when the C compiler is executed as illustrated in (c), it may be set as an option. For example, "ccomp-bitacc = r0ls
source. c ". Option" -bita
cc = r01 ”, the bit accumulator is set to R0L,
Compile "source.c".

The C compiler, for example, outputs “flag = i
op17; ", when the carry flag (C) is used as a bit accumulator, a program such as MOV.B # 00, R0L BLD # 7, $ iop1 BST # 0, R0L MOV.B R0L, $ flag is generated. And set the bit accumulator to R
0L, BLD # 7, {iop1 MOV. A program such as BR0L, $ flag is generated.

The steps for analyzing the lexical and semantics of the C source program and performing the optimization can be common, and then differ only in the step of generating a program corresponding to the CPU.

According to the selected instruction type and operation mode, the C compiler can use available operations,
An instruction indicated by a combination of a data size and an addressing mode is determined, and a program written in C language is
It is converted into PU1 instructions and output as an assembly language program or object module.

The C compiler itself has a function of converting a program in C language into an instruction of the CPU 1 and a function of C ++.
Improvements in functions that are not directly related to the instruction set of the CPU 1, such as compiling a program in a language and optimizing between modules, have been attempted. Must be applied to the compiler. If a common C compiler is used as in the present invention, it is easy to improve functions that are not directly related to the instruction set of the CPU 1, and it is possible to improve development efficiency and the like.

The setting of the register CPUCR is the same as the selection of the bit accumulator. If this is written in assembly language, register CPU
The value to be set in CR is xy, and MOV. B #xy, R0L MOV. BR0L, $ CPUCR. It can also be embedded in a C language source program. In C language, CPUCR = xy;

According to the CPU and the like described above, the following functions and effects can be obtained.

[1] An arbitrary bit of the data on the memory is stored in a predetermined bit (for example, bit 0) of the data on the predetermined general-purpose register or the memory, and the other bits are set to a fixed value (0). , Sign extension), etc., for example, making it possible to easily execute, for example, the assignment of a bit field declared value on a structure described in C language to a character type parameter, It is possible to reduce the execution time of an instruction and the length of an instruction code. For example, by combining the BLDS instruction and the MOV instruction, the instruction code of 6 words and the execution state number of 8 states in the related art can be reduced to 3 words and 5 states. Such operations frequently occur in the microcomputer for controlling equipment, and the effect is further enhanced. As a result, the processing performance of the microcomputer can be improved, thereby contributing to higher speed and higher functionality of device control. By having instructions conforming to the C language, it is possible to improve the development efficiency of a development device such as compiling and optimization.

[2] By using a general-purpose register for the bit accumulator instead of the carry flag (C),
While the bits to be operated are held in the bit accumulator, other operations such as address calculation can be executed, thereby facilitating programming. Also,
The BSTS instruction and other bit logical operation instructions can also easily perform a logical operation on a bit basis using the same bit accumulator.

[3] A variety of usages can be supported by allowing the bit accumulator to be designated as a carry flag (C) or a general-purpose register. Existing C with carry flag (C) as bit accumulator
If a PU exists, this software asset can be used effectively. When the carry flag (C) is a bit accumulator, limited resources can be effectively used even when the number of general-purpose registers is not sufficiently large.

Since the development device has a means for selecting the bit accumulator, a C compiler and the like can be used in common, and the development efficiency can be improved. Common use can also reduce the man-hours for transplantation and maintenance.
The user, regardless of how to use the bit accumulator,
Commonly available and convenient. Since the method of using the bit accumulator can be changed or a comparison can be made between both programs immediately, it is possible to contribute to shortening the development period and to suppress undesired costs.

[4] By making a general-purpose register used as a bit accumulator selectable, programming flexibility can be improved when a plurality of bits are manipulated. For example, in the case of flag1 = iop17; flag2 = iop27; and if flag1 and flag2 are arranged at consecutive addresses, BLD # 7, $ iop1, R0L BLD # 7, $ iop2, R0H MOV. Writes to the memory can be shared as WR0, $ flag, etc., to achieve higher speed.

[5] Transfer from an arbitrary bit to another arbitrary bit is enabled, thereby facilitating programming and shortening execution time. Declaring a bit field of a structure, etc. on the built-in RAM, holding multiple bits,
The use efficiency of the built-in RAM can be improved. The source and destination can be independently selected from general-purpose registers / memory, thereby facilitating programming.

[6] The instruction code of the existing bit transfer instruction, its machine language and control are shared, and the
Conventional design resources can be effectively used, and addition and change of a logical scale can be minimized, and an increase in a logical and physical scale can be minimized. In addition, the time required for development can be shortened, and resources can be saved.

The instruction code is composed of a plurality of words, and the instruction execution function for transferring data from the memory, the instruction execution function for performing bit manipulation itself, and the instruction function for transferring data to the memory are controlled by different instruction code words. Each of them performs the same operation as an existing similar instruction, thereby shortening the development period. Since the instruction execution function for transferring data from the memory and the transfer instruction function for transferring data to the memory can be used in common for the types of bit transfer instructions, the instruction execution function for performing the bit operation itself is commonly used for general-purpose registers. Since it can be used, an increase in the logical scale can be suppressed. By making the instruction execution function for transferring data from the memory common, it is possible to easily increase the types of addressing modes.

[7] The latch means such as the temporary register TRD is provided with means for determining the state of a designated bit, and the state of a predetermined bit is determined without reading it out to the arithmetic logic unit ALU or the like. By doing so, it can be realized without changing the overall operation of the bit transfer instruction.
Also, an increase in logical scale can be minimized. Similarly, by providing a means for inputting only predetermined bits, the portion to be changed can be reduced and the increase in logical scale can be minimized.

A bit transfer instruction between arbitrary bits (BMO
In the first mode and the second mode V), the operations of the BLDS instruction and BSTS instruction and the ALU can be made common, respectively, thereby suppressing an increase in logical scale and shortening the development period.

A bit transfer instruction between arbitrary bits (BMO
In the first mode and the second mode of V), the bit number fields on the source side / destination side in the instruction code are exchanged, and the bit position of the instruction code input to the decoder is made common, thereby simplifying the logic. Can be planned.

The invention made by the present inventors is not limited to the embodiment, but can be variously modified without departing from the gist of the invention. For example, it is not necessary to have both the bit 0 fixed transfer and the transfer between arbitrary bits, and only one of them or only some of the instructions and the addressing modes may be used.

The bit accumulator is a general-purpose register R
The present invention is not limited to the selection between the bit 0 of 0L and the carry (C) flag. Both may be used, and the type of instruction may be different, or may be specified in an addressing mode or the like. As described above, an arbitrary general-purpose register can be specified in addition to the general-purpose register R0L.
Instead of using bit 0, it may be the most significant bit such as bit 7. As described above, the upper bit can be set to 0 and can have the same content as that of bit 0 (for example, storing H'00 and FF). These may be selectable, or may be specified by the type of command or addressing mode.

The size of source or destination data for transferring bits is not limited to bytes, but may be words or the like, and can be appropriately selected according to the data size of the CPU. Multiple sizes may be available.

The source or destination addressing mode for transferring bits can be set directly to the register or to the 8
It is not limited to a bit absolute address, but 16 bits to 32 bits
It can be used as appropriate according to the addressing mode of the CPU, such as a bit absolute address or register indirect. The source and destination addressing modes need not match each other.

In the above example, the instruction code for reading the source or destination data, the instruction code for executing the bit transfer operation, and the instruction code for writing the execution result are executed separately. For the configuration of the instruction code, the method of decoding the instruction code, and the method of executing the instruction, various methods can be adopted. For example, the BLDMOV instruction is sequenced in common with the BMOV instruction of the memory-memory, but the order of the second word and the third word is reversed, the destination memory does not read, and the operation result ( TRD)
May be performed only. This can shorten one state. In this case, generation of an instruction code (mov-st) that performs the same operation as the write-type transfer instruction is not performed.

Although the control signal uses MODS and MODED, it can be divided into other control signals. Further, the basic unit of the instruction code does not need to be limited to 16 bits, and may be an arbitrary bit width such as 8 bits or 32 bits.

The internal configuration of the CPU, for example, an internal bus or A
It goes without saying that the LU configuration and operation timing can be changed at any time. The other functional blocks of the microcomputer are not restricted at all.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is the application field of the background has been described. However, the present invention is not limited to this. A processing device is also applicable, and the present invention can be applied to at least a data processing device that decodes and processes instructions and performs arithmetic processing.

[0193]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the data in the address space is read, the state of the desired bit is detected and stored in a predetermined bit (for example, bit 0) of the general-purpose register. The instruction (BLDS instruction) for setting the state (e.g., 0) of the
For example, when a program is created in a high-level language such as a language, the instruction code length of bit manipulation (particularly, when the bit state is stored as a parameter or the like) can be reduced, and the execution time can be reduced. In the above, by having an instruction (BLDMOV instruction) for storing in a desired address space instead of the general-purpose register, the instruction code length and the execution time can be further reduced. By having a bit transfer instruction (BMOV instruction) between arbitrary bits, the instruction code length and the execution time can be reduced, and the use efficiency of a memory such as a RAM can be improved.

[Brief description of the drawings]

FIG. 1 shows a CP as an example of a data processing device according to the present invention.
The bit transfer instruction (BLDS,
FIG. 3 is an overall explanatory diagram of BSTS, BLDMOV, BMOV).

FIG. 2 is an example of a data processing device according to the present invention;
FIG. 3 is an explanatory diagram showing a configuration example of a general-purpose register and a control register incorporated in U.

FIG. 3 is an instruction format diagram of a bit transfer instruction (BLDS, BSTS, BLDMOV) as a bit 0 fixed transfer instruction and a bit transfer instruction (BMOV) between arbitrary bits.

FIG. 4 shows a CP as an example of a data processing device according to the present invention.
It is a block diagram showing an example of U.

FIG. 5 is a block diagram illustrating a portion related to a bit transfer instruction of the arithmetic and logic unit;

FIG. 6 is a block diagram illustrating an example of a temporary data register.

FIG. 7 shows a first example of a bit transfer instruction (BLD # 7, {
5 is a timing chart illustrating the execution timing of (FFFFFE).

FIG. 8 shows a second example of a bit transfer instruction (BLDMOV #
6 is a timing chart illustrating the execution timing of (#FFFFFD, # FFFF00).

FIG. 9 shows a third example of a bit transfer instruction (BST # 5, {
6 is a timing chart illustrating the execution timing of FFFF10).

FIG. 10 shows a fourth example of a bit transfer instruction (BMOV #
6 is a timing chart illustrating the execution timing of (#FFFFFC, # 5, # FFFF21).

FIG. 11 shows a fifth example of a bit transfer instruction (BMOV #
4, {FFFFFB, # 3, R2L) is a timing chart illustrating the execution timing.

FIG. 12 shows a sixth example of the bit transfer instruction (BMOV #
2, R3H, # 1, $ FFFF32).

FIG. 13 shows a seventh example of the bit transfer instruction (BMOV #
7, R4H, # 6, R5L).

FIG. 14 is a block diagram showing a microcomputer as an example of a data processing device according to the present invention.

FIG. 15 is an example of a data processing device according to the present invention;
FIG. 2 is an explanatory diagram illustrating an outline of a PU development environment.

FIG. 16 is an example of a data processing device according to the present invention;
FIG. 4 is an explanatory diagram illustrating a method of specifying a bit accumulator in a PU system development device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Instruction control part 3 Execution part DEC Instruction decoder ER0-ER7 General-purpose register MA Address buffer ALU Arithmetic and logical operation unit 10 Decoder 11 Selector 12 Input selector 13 Input selector 14 Logical operation circuit 15 Zero detection circuit 16 Output selector TRD Temporary data register Reference Signs List 20 decoder 21 input selector 22 register section 23 output selector CCR condition code register PC program counter 30 microcomputer

Claims (5)

[Claims] 1. A data processing device which decodes a read instruction code by an instruction control means and executes the instruction by an instruction execution means, wherein the instruction execution means is a register means and an arithmetic means used for executing an instruction. The instruction control means, when decoding the first predetermined instruction, causes the instruction execution means to read data in the address space,
The state of a desired bit of the data is detected, and the register means is controlled to a predetermined state. The predetermined state of the register means is such that a predetermined bit of the data is stored in a predetermined bit of the register means. The data processing device is characterized in that the state is reflected and the other bits of the register means are set to constant values. 2. When the instruction control means decodes a second predetermined instruction, the instruction control means causes the instruction execution means to read data on an address space, detect a state of a desired bit of the data, and Controlling another data to a predetermined state, the predetermined state of the other data in the address space reflects a state of a desired bit of the data in a predetermined bit of the another data. 2. The data processing apparatus according to claim 1, wherein the other bits of the other data are set to a constant value. 3. The register means includes a status register means for storing a flag and a general-purpose register means, and the register means for reflecting a state of a desired bit of the data includes the status register means or the general-purpose register means. 3. The data processing apparatus according to claim 1, further comprising means for instructing which one is to be targeted. 4. When the instruction control means decodes a third predetermined instruction, the instruction control means causes the instruction execution means to read data in a register means or an address space, and detects a state of a desired bit of the data. 4. The data processing as claimed in claim 1, wherein the control is performed to reflect the state of the bit to a desired bit state of another data in another register means or address space. apparatus. 5. The instruction execution unit has a temporary data latch unit, and the temporary data latch unit has at least one of a function of outputting a state of a desired bit and a function of inputting only a desired bit. 5. The data processing apparatus according to claim 4, wherein an output of said temporary data latch means is connectable to an input of said arithmetic means.