JP3432532B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and, for example, to a technique effectively used for a central processing unit of a single chip microcomputer.

[0002]

2. Description of the Related Art A single-chip microcomputer has a central processing unit (hereinafter also simply referred to as a CPU).
4 bits, 8 bits,
There are 16-bit microcomputers and the like. At present, the 8-bit single-chip microcomputer is most often used among these, and is used for device embedded control. An example of such an 8-bit single-chip microcomputer is "H8 / 330 HD6473308 HD643" issued by Hitachi, Ltd. in June 1989.
3308 hardware manual ”. A central processing unit of an 8-bit single-chip microcomputer (hereinafter referred to as an 8-bit CPU) mainly handles a data length of 8
Bits, and therefore an 8-bit CPU has a register or accumulator that is 8-bit long, and a 16-bit register that is twice as long as the 8-bit register. Although not particularly limited, these 8-bit CPUs mainly use 8-bit registers or 16-bit registers for data processing, and use only 16-bit registers as address registers for referring to a memory.
The 16-bit register as such an address register may be called an index register, a stack pointer, a program counter, or the like.

In the 8-bit CPU, the minimum instruction unit is 16 bits (2 bytes). Further, when arranging an instruction or 16-bit data in the memory, it is limited to allocating it in a continuous 2-byte area starting from an even number. Further, the operation instruction of the 8-bit CPU is allowed only between the registers inside the CPU, and the operation of the data arranged in the memory must be performed by the operation instruction after the data is once transferred to the register inside the CPU. I have to. Instead of having such restrictions,
The internal configuration of the CPU, particularly the configuration of the control unit that controls the execution state of the CPU, is simplified, and the logical and physical scales are reduced. Manufacturing costs can be reduced as a result of the reduction of the logical and physical scales. Further, as a secondary effect, it is possible to improve the operation speed. That is,
A relatively large processing performance can be realized with a relatively small manufacturing cost.

[0004]

However, the above-mentioned C
In PU, the address register is 16 bits long and C
The memory that the PU can refer to is 65,536 bytes (= 2 ¹⁶ ,
The following is 64 kbytes). On the other hand, in the application of device built-in control in which an 8-bit single-chip microcomputer is used, it is required to handle a large-capacity program or data in order to improve the performance of the device.
At this time, it is desirable that the function is upward compatible with the conventional CPU. That is, the user can directly use all or part of the source program or the object program already developed by the conventional CPU. As a result, only the peripheral functions of the microcomputer or the parts that depend on the application system are changed,
Immediately develop software or application system,
The development period can be shortened.

In response to such a demand, the inventor of the present invention realizes a relatively large processing performance while reducing the logical / physical scale of the CPU or a relatively small manufacturing cost, while achieving 64 k. CPU that can refer to more than one byte of memory
Was examined.

On the other hand, a memory which can be referred to by generating an address by adding an 8-bit page register to the 8-bit CPU and combining it with a 16-bit register is 16777216 bytes (= 2 ²⁴ , hereinafter 16 Mbytes).
As an example of the single-chip microcomputer, "H8 / 532" issued by Hitachi, Ltd. in December 1988
HD6475328 HD6435328 Hardware Manual ”and the like. In such a memory reference method, since the page register and the address register are completely independent, the hardware implementation method is simplified, but carry or borrow is not propagated between the page register and the address register. When writing a program or compiler, one must always be careful that a group of programs or data does not cross page boundaries. That is, in the above example, when the instruction is executed from the address 0, the program counter is initially H'0000.
(H 'indicates a hexadecimal number), and the corresponding page register (hereinafter referred to as code page register) is H'00.
Continue to execute operation instructions without using branch instructions,
When the next instruction is executed after reaching the address 535 (H'FFF), the program counter is H'FFF.
F → H'0000 and overflow. Because the carry at this time is not propagated to the code page register,
The next instruction will return to address 0. For this reason, a program is created by dividing it so that it does not exceed 64 kbytes, the divided programs are assigned to different pages, and when the execution is transferred from a program existing in one page to a program existing in another page You must use inter-branch instructions. That is, when using a branch instruction in the program, whether the branch destination is in the same page,
It is necessary to properly use the intra-page branch instruction and the inter-page branch instruction in consideration of whether they exist on another page. Similarly, it is necessary to divide the data so that it does not exceed 64 kbytes and manage it. That is, when updating the contents of the address register each time the memory is accessed, such as in the so-called post-increment register indirect mode, even if the address register overflows, the corresponding page register (hereinafter referred to as the data page register) Carry does not propagate. When using a 16-bit displacement indirectly with a register with displacement, a 16-bit displacement is added to a 16-bit address register, and even if a carry or borrow occurs, it is not propagated to the page register. An address is generated by combining the 16-bit addition result and the page register. That is, when the page register is H'00, the address register is H'FFFF, and the displacement is H'4000, the resulting address is H'003FFF. Therefore, in the address extension technique using the page register, the addressing modes that can be practically used are also limited.

To manage the page register by always paying attention to such a program or data so as not to cross a page boundary, it is necessary to manage the contents of a page register by using a program (object) in a so-called machine language of a CPU. It becomes a big constraint on the creation of a compiler that automatically converts to a program), which lowers the design efficiency of the compiler and significantly increases the size of the created object program. As a result, the execution time of the program also decreases. Resulting in.

In addition, for a sufficient application with a memory space of 64 kbytes or less, the page register cannot be used as a data register, which is logically and physically wasted, resulting in the relatively small manufacturing cost. This goes against the purpose of achieving relatively large processing performance.

An object of the present invention is to minimize the increase in the logical / physical scale and , depending on the operation mode, to the lower CPs.
Lower CPU capable of utilizing some or all of the programs already developed for another data processing device such as U
It is an object of the present invention to provide a data processing device capable of relatively widening the address space that can be continuously used while achieving upward compatibility with . Another object of the present invention is to provide a data processing device which can facilitate compilation of a program created in a high-level language in addition to the above objects.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, for general-purpose registers of the CPU,
To store data information, divide it all, or divide it into two, or divide it into two.
One of the equal divisions is further divided into two and used, and the address information can be held with a bit number larger than the address bit number of the lower CPU. For example, a 16-bit extension register is added to a 16-bit general-purpose register of an 8-bit CPU, and the entire 32-bit register is used collectively or a part thereof as an address register, and the entire 32-bit data register is used. 1
As a unit, it is divided into two to form two 16-bit data registers, and one of the 16-bit data registers is divided into two.
It can be divided and used as two 8-bit registers. Designation of the usage pattern of such a register is performed as follows.
Whether it is used as an 8-bit register or a 16-bit register is determined by the size bit of the data information included in the operation code. When the size of the data information is 8 bits (bytes), the upper and lower bits of the 8-bit register are designated by a predetermined 1 bit of the register designation field included in the instruction. When the size of the data information is 16 bits (word), the predetermined 1 bit specifies the upper or lower part of the 16-bit register. And 32 bits (longword)
Usage as a register is specified by a prefix code of an instruction including an operation code. Alternatively, a new operation code having the same number of bits as the operation code of the lower CPU is added and designated. Based on such a register configuration, the instruction execution function of the lower CPU having a 16-bit register is included. As a result, the program developed for the lower CPU can be used for the upper CPU according to the present invention at least at the level of the source program (the description level in the high-level language). That is, at least at the source program level, upward compatibility is realized. Here, the lower CPU refers to a CPU whose register configuration and its instruction set are included in the register configuration and instruction set of a data processing device such as the CPU according to the present invention.

Furthermore, in order to realize upward compatibility at the object program level, an operation mode for switching the number of bits of an effective address and the unit size of a vector and a stack according to the usage form of the register, for example, the first mode
It suffices to prepare a maximum mode as one mode or a higher mode and a minimum mode as a second mode or a lower mode . CP in minimum mode
U operates exactly like a lower CPU. In the maximum mode, the CPU operates as the upper CPU with the maximum functions provided therein. That is, the first mode
And a data processing device having a second mode,
Have a predetermined bit length, and each has a first portion (E0-E0).
E7) and the second part (R0L, R0H to R7L, R7H)
And a plurality of general-purpose registers having
A first arithmetic and logic unit coupled to the first portion of the star.
The unit of the unit and the plurality of general-purpose registers
The second arithmetic connected to the second part (ALUL, ALUH)
And a logical operation unit. The first mode is
First arithmetic logic operation unit and the above second arithmetic logic operation
The unit performing address and data operations
To enable. The second mode is the second arithmetic logic.
Arithmetic unit performs address arithmetic and data arithmetic
In addition to making it possible,
Allows the knit to perform data operations.

Since it is necessary that the preceding code does not overlap with the instruction code of the lower CPU, it is optimal to use it as the code corresponding to the undefined instruction code.

The unit of instruction can be twice as long as the unit of data information. For example, if the CPU register is 32
When expanded to bits, when considering the future use of an address space of 4 Gbytes, the instruction length is set to 2 bytes, and the 24-bit absolute address displacement is set to 4 bytes including the reserved area. Further, in order to simplify the configuration of the execution means and the control means and contribute to the reduction of the logical and physical scale, the least significant bit of the effective address designation part in the instruction code is set to the least significant bit of the word in the instruction code. Is desirable.

[0016]

According to the above-mentioned means, it is possible to use the register structure which can be divided into two parts for holding the data information and can also be used as an address register with a bit number equal to or more than the address bit number of the lower CPU. The byte / word size of the data information is specified by the size bit of the operation code, and the use of the data information of the long word size is specified by the prefix code or the newly added operation code with the same number of bits as the lower CPU. The upper / lower part of the byte size register used for byte size data information is designated by a predetermined 1 bit of the register designation field, and the word size register is designated by a predetermined 1 bit for word size data information. The upper / lower order of each is specified, so that at least the To achieve upward compatibility of the nest program level.

Preparing the maximum mode and the minimum mode realizes upward compatibility at the object program level.

A register configuration in which a 16-bit extension register is added to a 16-bit general-purpose register of an 8-bit CPU to constitute a total of 32 bits makes the data holding means easy to use on software and hardware. Good and thus achieves a logical as well as a physical reduction in the size of data processing devices such as CPUs. Also,
With respect to holding address data using all or part of the data holding means, it is easy to expand the linearly usable address space, and it is possible to create and compile a program as compared with the address space expansion technology using page registers. Make it easier.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a single chip microcomputer which is a first embodiment of a data processing device according to the present invention. A single-chip microcomputer 100 shown in the figure has a CPU (central processing unit) 1 that controls the entire control, an RO that holds an operation program of the CPU 1, and the like.
M (read only memory) 2, RAM used as a work area of the CPU 1 and a temporary storage area for data
(Random access memory) 3, timer 4, serial communication interface (SCI) 5, clock pulse generator 68, and input / output port (IO
P) 61 to 67 and other functional blocks, which are interconnected by an internal bus 69. The internal bus 69 includes an address bus, a data bus, and a control bus, although not particularly limited. Such a single chip microcomputer 100 is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

Single-chip microcomputer 10
0 is the terminal XTA of the clock pulse generator CPG
It operates in synchronization with a crystal oscillator connected to L and EXTAL or a reference clock generated based on an external clock input from the outside. The minimum unit of this reference clock is called a state. In the figure, Vss and Vcc are power supply terminals. MODE1 to MODE3 are CPU1
Is a mode signal for.

When a reset signal RES is applied to the CPU 1, the single chip microcomputer 100
Is reset. When the reset state is released, the CPU 1 reads the start address and performs the reset exception handling to start reading the instruction from this start address. It is assumed that the start address is stored at address 0, although it is not particularly limited.
Thereafter, although not particularly limited, the CPU 1 sequentially reads out the instruction from the ROM 2 and decodes it, and processes the data or the RAM 3, the timer 4, and the S based on the decoded result.
Data is transferred to and from the CI5 and the input / output ports 61 to 67. That is, the CPU 1 refers to data input from the input / output ports 61 to 67 or the like or instructions input from the SCI 5 or the like, performs processing based on an instruction stored in the ROM 2, and inputs / outputs according to the result. The ports 61 to 7 and the timer 4 are used to output signals to the outside to control various devices.
Although not particularly limited, the ROM2, RAM3,
It is assumed that the read / write of the timer 4 and the like is executed in two states for each of byte (eg, 8 bits) / word (eg, 16 bits).

The minimum unit of the instruction of the CPU 1 is 2 bytes, and when the instruction or 16-bit data is arranged in the memory, it is arranged in a continuous 2-byte area starting from an even number.

FIG. 2 shows an example of a register configuration of a CPU corresponding to the lower CPU of the CPU 1. In this embodiment, the lower CPU is a CPU provided before the development of the CPU 1 according to this embodiment. In other words, the CPU 1 according to this embodiment can be positioned as an upgraded version of the lower CPU.

The lower CPUs shown in FIG.
Eight general-purpose registers R0L, R0H to R7 of 6-bit length
L, R7H and 16-bit program counter PC
And 8-bit condition code register CCR
And have. General-purpose registers R0L, R0H to R7
L and R7H are not particularly limited, but can store 8-bit length data with the upper 8 bits and the lower 8 bits independent, or can store 16-bit length data by connecting the upper and lower bits. it can. The condition code register CCR includes an interrupt mask bit (I), a carry flag (C), a zero flag (Z), a negative flag (N), and an overflow flag (V).
When the interrupt mask bit I is 1, the CPU 1 is in an interrupt disabled state, and when it is 0, it is in an interrupt enabled state. The other flags reflect the result of calculation.

FIG. 3 shows data used in the register configuration of FIG.

The byte data handled by the lower CPU is stored in the upper RiH or the lower RiL of the general-purpose register (i = 0 to 7) as described above. The word data is stored in the general register Ri. Bit 15 corresponds to the most significant bit of data and bit 0 corresponds to the least significant bit. Address information (also referred to as address data) is stored in the general-purpose register Ri as word data. Bit 15 corresponds to the most significant bit of data and bit 0 corresponds to the least significant bit. Eight 16-bit registers and 16 8-bit registers can be used. Whether the data size is byte or word is determined by the size bit of 1 bit included in the operation code of the instruction.

FIG. 4 shows an upper CP according to an embodiment of the present invention.
An example of the register configuration of the CPU 1 as U is shown.

The CPU 1 includes eight general-purpose registers R0L, R0H to R7L and R7H each having a 16-bit length, and eight extension registers E0 to E7 each having a 16-bit length.
It has a 24-bit program counter PC and an 8-bit condition code register CCR. General-purpose registers R0L, R0H to R7L, R7H are
Although not particularly limited, the upper 8 bits and the lower 8 bits can be stored independently to store 8-bit length data.
Data of 16-bit length can be stored by connecting the upper and lower bits. The extension register Ei cannot be divided into 8 bits and used independently.

When the general purpose registers RiL, RiH are used as address registers, the general purpose registers RiH, R
The 16 bits held by the iL are used as the lower 16 bits of the address, and the contents of the corresponding extension register Ei are used as the upper 16 bits of the address, for a total of 32 bits, or the upper 8 bits of the extension register Ei are ignored and a 24-bit address is generated. To do. CPU1 is 24 bits or 32
A continuous address space defined by bit addresses can be used. This 32-bit or 2
The 4-bit address can be modified in various ways. When this modification is performed, when a carry or borrow occurs in the calculation of the lower 16 bits, the carry is carried up or carried down to the extension register Ei on the upper side. In the following description, the address data is 24 bits. Accordingly, the bit length of the program counter PC in FIG. 4 is set to 24 bits. Program counter P
The bit length of C may be 32 bits.

The extension registers E0 to E7 can be used as data registers in the same manner as general purpose registers as 16-bit registers. That is, it is possible to perform data operation between extension registers and between extension registers and general-purpose registers. Since the condition code register CCR is the same as the above, detailed description thereof will be omitted. The program counter PC is the same as the above except for the bit length.

FIG. 5 shows general-purpose registers R0L, R0H to R.
7L and R7H and data configuration examples of the extension registers E0 to E7 are shown. The byte data handled by the CPU 1 is the high-order RiH (i = 0, 1, ..., 7) or the low-order R of the general-purpose register.
It is stored in iL. Word data is general register Ri
(RiH, RiL) or stored in the extension register Ei. At this time, bit 15 corresponds to the most significant bit of data and bit 0 corresponds to the least significant bit. The 32-bit longword data is stored in the general register Ri and the extension register Ei. The 24-bit address data is stored in the extension register Ei and the general register Ri as longword data. At this time, the upper 8 bits of the extension register Ei are set as a reserved area. The reserved 8-bit address data and 24-bit address data are also simply referred to as longword address data.

With this register configuration, 16 8-bit registers, 16 16-bit registers, and 8 24-bit registers can be used. This means that the software, which is upward compatible with the lower CPU and is created by using the register of the lower CPU, can be used in the CPU 1 at least at the source program level. In order for the CPU 1 to realize the upward compatibility with the lower CPU, it is necessary to have commonality in the way of specifying the registers. Although this will be described in detail later, it is sufficient to consider only the register number as the address register, and for both 8-bit operation and 16-bit operation, the register specification in the register specification field of the instruction is 4 bits. The instruction format can be shared with the lower CPU. In addition, since 4 bits are used to specify 16 registers, no waste occurs. In this respect, such a register configuration simplifies the internal configuration of the CPU 1, reduces the logical / physical scale, and reduces the manufacturing cost. It does not impair the purpose of reducing the cost and improving the operation speed.

6 to 8 show an example of an addressing mode of the CPU 1 and a method of calculating an effective address.

In the register indirect shown in FIG. 6A, the instruction code includes a portion for designating a register, and a total of 24 bits of the contents of the register designated by this instruction code and the extension register corresponding thereto are addressed. Specify the address on the memory as. Since the address may be 24 bits, the upper 8 bits are ignored.

The register indirect with displacement shown in (2) and (3) of FIG. 6 is the result of adding the displacement included in the instruction code to the 24-bit address obtained in the same manner as the above register indirect. The address on the memory is specified with the address. The addition result is used only for specifying the address and is not reflected in the contents of the extension register Ei and the general register Ri. Although not particularly limited, the displacement is 24 bits or 16 bits, and when adding the 16-bit displacement, the upper 16 bits are sign-extended.
That is, the upper 16 bits of the displacement are 1
The addition is performed assuming that the value is the same as that of bit 15 of the 6-bit displacement. In this case, the upper 8 bits of the 24-bit displacement include a 32-bit displacement designating part in the instruction code together with the reserved area in consideration of the instruction being a 2-byte unit and future expansion. .

The post-increment register indirect shown in (4) of FIG. 7 specifies an address on the memory with a 24-bit address obtained in the same manner as the register indirect. Thereafter, 1 or 2 or 4 is added to this address, and the addition result is stored in the extension register / general-purpose register. When specifying byte data in memory, 1 is
When word data is specified, 2 is added, and when address data is specified, 4 is added. The upper 8 bits of the addition result are also stored in the extension register.

The pre-decrement register indirect shown in (5) of FIG. 7 is obtained in the same manner as the register indirect.
An address on the memory is designated by a 24-bit address obtained by subtracting 1 or 2 or 4 from the 4-bit address. After that, the subtraction result is stored in the extension register / general-purpose register. 1 is specified when byte data on the memory is specified, 2 is specified when word data is specified, and 4 is specified when address data is specified. Similarly to the above, when the address may be 24 bits, although not particularly limited, the upper 8 bits of the subtraction result are also stored in the extension register.

In the program counter relative shown in (6) of FIG. 7, the address on the memory is designated with the result obtained by adding the displacement contained in the instruction code to the 24-bit address of the contents of the program counter. The addition result is stored in the program counter. Although not particularly limited, the displacement is 16 bits or 8 bits, and when these displacements are added, the upper 8 bits or 1
6 bits are sign-extended. That is, the upper 8 bits of the displacement are added as bit 15 of the 16-bit displacement, or the upper 16 bits are assumed to have the same value as the bit 7 of the 8-bit displacement and the addition is performed. Program counter relative is used only for branch instructions.

The absolute address shown in FIG. 8 designates the address on the memory with the 8-bit, 16-bit or 24-bit absolute address included in the instruction code as the address. In the 8-bit absolute address, the upper 16 bits are extended by 1. That is, all bits 23 to 8 of the address are set to 1. Therefore, the usable address is H'F
It is 256 bytes of FFF00 to H'FFFFFF.
The 16-bit absolute address is sign-extended with the upper 8 bits. That is, if the bit 15 of the 16-bit absolute address is 0, all the bits 23 to 16 of the address are 0, and if the bit 15 is 1, all the bits 23 to 16 of the address are 1. Therefore, usable addresses are 64 kbytes of H'000000 to H'007FFF and H'FF8000 to H'FFFFFF.

In addition to the above, the CPU 1 is an immediate
An addressing mode such as register direct is executed, but since these are not directly related to the present invention, detailed description thereof will be omitted.

Since the lower CPU has an address space of 64 kbytes, there is no register indirect with 24-bit displacement and absolute address of 24-bit. Also, there is no long word size such as indirect decrement register. The other addressing modes shown in FIGS. 6 to 8 can be equated with the addressing mode and effective address calculation supported by the lower CPU if the upper 8 bits of the address information are ignored. Therefore, the CPU 1 is functionally compatible with the lower CPU and the conventional CPU in terms of addressing mode and address calculation.

9 to 16 show the instruction formats of the main addressing mode instructions.

The format of each instruction has an operation code section op for indicating the function and addressing mode of each instruction, and a register for designating a register to be used according to the operation code of the operation code section op. Designation part (rs, rd, e
rs, erd), absolute address (aa), displacement (d), or immediate (xx). The instruction format is in units of 2 bytes, and the register designating section uses bit 7 to bit 4, bit 3 to bit 0 of the first word of the instruction code, or bit 1 as a special form.
1 to 8 are included. The register designating unit rs designates a byte or word size source register, and the register designating unit rd designates a byte or word size destination register. Whether the register to be designated has a byte size or a word size is determined by the operation code of the operation code section. That is, when the operation code is accompanied by a 16-bit operation, the register designating parts rs and rd
The lower 3 bits of 8 specify which of the eight registers R0 to R7 is to be used, and whether the extended register or the general-purpose register is used among the specified registers is determined by the remaining register designation section. Designated by the upper 1 bit. When accompanied by an operation code involving an 8-bit operation, the lower 3 bits of the register designating unit rs, rd designate which of the eight registers R0 to R7, and the general register among the designated registers. Whether to use the upper side or the lower side of is determined by the remaining upper 1 bit of the register designating unit. The register designation unit ers designates a longword size source register, and the register designation unit erd designates a longword size destination register. Register designating part ers, e in which 4 bits are secured
The most significant 1 bit of rd is effectively ignored during instruction decoding. In this case, the fact that the register designated by 3 bits which is substantially significant is 32 bits is clarified by the operation code when a new operation code dedicated to the longword data can be newly added. . When it is not possible to add such a new operation code, or when it is determined that it is not a good idea to add such an operation code, the prefix code described below is used. Here, the number of bits of the operation code dedicated to the longword data is the same as the number of bits of the operation code of the lower CPU.

Absolute address aa, displacement d, immediate xx in the instruction format
Is included in the instruction code such that the least significant bit is the even-numbered bit 0. That is, the absolute address aa of 16 bits or more, the displacement d, and the immediate xx are included in units of 2 bytes. Therefore, 2
4-bit absolute address aa, displacement d
Is a 4-byte area including a reserved portion of a predetermined number of bits in the 1-byte area at the beginning (higher-order bit side). The 8-bit absolute address aa, the displacement d, and the immediate xx are contained in bits 7 to 0 of the first word.

According to the above-mentioned instruction format, the portion designating the register in the instruction format is fixed to a part of the first word of the instruction, so that the decoding logic configuration of the instruction becomes simple. Furthermore, the lower 3 bits of the register designation area determine which of the 8 registers is designated, and the upper 1 bit determines which area of the designated 1 register is to be used. At the same time, the size of the area determined by the 1 bit is determined by the data size specified in the instruction, in other words, by the operation code of the operation code section, so that the data stored in the register and the address data are stored. However, the number of bits in the register designating section can be minimized even when there are several types of bytes, words, and long words.

Similarly to the above, the lower CPU does not have a register indirect with 24-bit displacement, two addressing modes of a 24-bit absolute address, and a longword size instruction. Other commands are lower CP
U is common to the CPU 1, and the CPU 1 shares the instruction format with the lower CPU.

FIG. 17 shows an example of correspondence between the data of the register designating section and the register designated by the data in the instruction format.

The register designating section designates a register number (0 to 7) by bits 0 to 2, and bit 3 indicates whether it is the upper side or the lower side of the general register Ri (RiH /
RiL) is a general-purpose register Ri for word size
Or extension register Ei. In the use as long word size data and address register, bit 3 is ignored as described above and practically does not exist.

FIG. 18 shows an internal block diagram of the CPU 1. The CPU 1 is mainly a micro ROM or PLA (Programmable Logic A).
control unit CONT configured by rray), general-purpose register
Of the general-purpose registers R0L, R0H as the second part of
R7L, R7H, extension registers E0 to E7 as the first part of general-purpose registers , program counter PC (PC
L, PCH, PCE), an execution unit EXE including a condition code register CCR, and a register selection unit R
It is composed of EGSEL. The control unit CONT fetches an instruction, decodes it, generates various control signals necessary for executing the instruction, and controls the instruction execution procedure. The register selection unit REGSEL generates a register selection signal according to the result of decoding the instruction.

The execution unit EXE further includes temporary registers TRL, TRH, TRE and an arithmetic logic unit ALU.
L, ALUH, ALUE, read data buffer RDB
L, RDBH, RDBE, write data buffer WDB
L, WDBH, WDBE, and address buffer AB
L, ABH, ABE, these are three internal buses A
(L, H, E), B (L, H, E), C (L, H, E
E) and the selector circuit unit SEL. The arithmetic logic unit ALUE is a first arithmetic logic operation.
The arithmetic logic unit ALUL, ALU
H is a second arithmetic logic unit. The read data buffers RDBL, RDBH, RDBE are connected to external data buses D7 to D0 and D15 to D8. The write data buffers WDBL, WDBH, WDBE are connected to the data buses D7 to D0, D15 to D8 via the write data output buffers WDBOL, WDBOH. The arithmetic logic units ALUL, ALUH, ALUE are
It is used for various calculations designated by instructions, addition of the program counter PC, calculation of effective address, and the like. The read data buffers RDBL, RDBH, RDBE are
Instructions and data read from ROM2, RAM3 or an external memory (not shown) are temporarily stored, and write data buffers WDBL, WDBH, WDBE
Temporarily stores the data to be written in the ROM 2, RAM 3 or an external memory. This gives C
The timing of the internal operation of PU1 and the read / write operation outside of CPU1 are adjusted. Address buffer AB
L, ABH, and ABE temporarily store the address read / written by the CPU 1.

Although not particularly limited, each circuit block in the execution unit EXE is basically composed of two blocks of 8 bits and one block of 16 bits. General-purpose register consists of 2 blocks of 8 bits, R0H
~ R7H corresponds to bits 15 to 8, and R0L to R7L corresponds to bits 7 to 0. The higher-order bits of the general-purpose register, that is, bits 31 to 16 correspond to one block of 16-bit extension registers E0 to E7. The internal bus is provided with A, B, and C in parallel corresponding to these bits 31 to 16, bits 15 to 8, and bits 7 to 0, respectively. The same applies to the temporary registers TR, ALU, read data buffer, write data buffer, and the like. The physical arrangement of these is not particularly limited.

By providing such a general-purpose register Ri and an extension register Ei, while maintaining compatibility with the lower CPU,
When the 6 MB address space can be used, it is a good idea to use an instruction system in which the main operation is performed between registers and the operation of memory and register is not performed directly (that is, not performed by one instruction) in both lower CPUs. is there.

First, if the lower CPU supports the direct operation between the memory and the register and the instruction system is optimized, a new instruction can be added for the upper CPU. Have difficulty. That is, regarding the operation of the memory and the register, the number of operation codes determined by the combination of the addressing mode of the memory and the type of operation is dramatically increased, and it is difficult to add a new operation code. Alternatively, the new operation code cannot necessarily be optimized, the instruction length becomes long, the program size becomes large, and the execution efficiency of the program also deteriorates.

Second, in order to effectively use the 16 Mbyte address space, the complicated addressing mode as described above is required. When such a complicated addressing mode can be executed for many arithmetic instructions, the control unit C
This is because the structure of the ONT becomes complicated and it is against the purpose of minimizing the logical and physical scale. To access the memory, data may be transferred to and from the register by a transfer instruction having the various addressing modes described above, and data processing such as calculation may be performed on the register. The general-purpose register Ri can be used as a maximum of 16 bits with an 8-bit length, and the general-purpose register Ri and the extension register Ei can be used as a maximum of 16 bits with a 16-bit length, and data necessary for a certain process must be placed on the register. You can Alternatively, at least most of the frequently used data can be placed in registers. Therefore, it is considered that there are few cases where inconveniences such as an increase in processing programs and a decrease in execution speed occur.

A bit manipulation instruction is an instruction that needs to be operated on a memory. Although these are designated as the nth bit of the address assigned in byte units, they are not data handled in byte units, and each bit has an independent function. For example, in the case of a register for controlling the operation of the timer, the timer clock is selected by the 0th bit and the 1st bit, and the timer counter is cleared when the contents of the timer counter and the comparison register match with the 2nd bit. Whether or not to do so is specified, and the third bit specifies whether or not to generate an interrupt when the above-mentioned coincidence occurs. These must be set to 1 or cleared to 0 in 1-bit units. Alternatively, when the processing program of the CPU 1 is different depending on whether a predetermined 1 bit of the input port is 0 or 1, it is necessary to judge the 1-bit data.
Such 1-bit data must be directly operated on the memory. This is because if a bit operation is performed after the data is once transferred to the register on a byte-by-byte basis, an interrupt occurs between the transfer and the bit operation, which causes a problem that the value of the input port changes, for example. However, the target address of such a bit manipulation instruction is fixed, and a complicated addressing mode is not necessary. It is only necessary to execute absolute address and minimum register indirect. Moreover, even in the case of an absolute address, it is not necessary to be able to use the entire address space, and it is considered sufficient if it can be used only in the address range in which the timer / input / output port exists. Eight bits are sufficient as an absolute address that can be used to specify such an address range. If 16 bits are used, the usable address range is widened, but the instruction length becomes long and control becomes complicated. It is considered very rare if the entire space of 16 Mbytes must be available for at least 24 bits. Therefore, the CPU 1 in the present embodiment supports a bit operation instruction for a direct operation between an internal register such as a general-purpose register and an external register such as a control register of a peripheral circuit, As a result, even if a 1-bit or several-bit bit manipulation instruction is directly performed with the external peripheral circuit, there is no fear that the scale of the control unit or the type of instruction is significantly increased.

FIG. 19 shows an example of the relationship between the function of the instruction and the combination of the addressing modes.

In the figure, # is immediate, R is register direct, @R is register indirect, @ (d16, R) and @ (d24, R) are register indirect with displacement, @ -R is pre-decrement register indirect, @R
+ Indicates indirect post increment register, @ a8, @a
16, @ a24 is an absolute address, @ (d8, PC), @
(D16, PC) means program counter relative addressing modes. In the figure, B means byte, W means word, and L means long word. The program counter relative is dedicated to branch instructions. Other addressing modes can be used in transfer instructions. Arithmetic instructions can use immediate and register direct. However, the unary operation is only direct to the register.

In FIG. 19, those supported by the lower CPU are marked with a circle. The long word of increment / decrement is a word-size operation because the address register has a word size in the lower CPU.

As described above, the arithmetic operation instruction can use bytes, words, and longwords, but addition and subtraction with carry can use only the byte size. Increment and decrement can use bytes, words, and longwords when the register is used as a counter, but ± 2 and ± 4 are used for address calculation, so only longwords can be used. There is. Logical operation instruction,
The shift instruction and rotate instruction can use bytes, words, and longwords, although not particularly limited. This is because, as one of the applications using the 16-Mbyte address space, when handling character data of a printer, it is considered that these instructions are frequently used for black-and-white inversion of character data and processing of italics and the like. On the contrary, in the lower CPU which supports the address space of 64 kbytes, the logical operation instruction, the shift instruction and the rotate instruction are not particularly limited, but only the byte can be used.

As described above, even if it is difficult to add a new operation code even if the instruction system is such that the main operation is performed between the registers and the direct operation between the memory and the register is not performed, for example, a long operation is performed. If a word-sized transfer instruction and operation instruction are equivalent to a word-sized instruction with a 1-word prefix code added,
The logical and physical scale of the control unit can be minimized.

20 and 21 show an example instruction format using a prefix code.

As described above, 1 is added before the indirect word size instruction format of the register with displacement.
A word prefix code is provided to represent the long word size. Since it is necessary that the prefix code does not overlap with the instruction code of the lower CPU, it is optimal to use it as the code corresponding to the undefined instruction code. In addition, it is possible to use, as a prefix code, if the operand specification field of an instruction such as a non-operation (NOP) instruction that does not substantially require the information of the operand specification field is filled with a predetermined code. it can.

FIG. 22 shows an address map of such a microcomputer.

The built-in ROM is arranged from the address H'00000, and the built-in peripheral functions and the built-in RAM are H'FF800.
It is arranged after that, and the space between them is an external space. Built-in peripheral functions and built-in RAM in the middle of the address space,
For example, it can be arranged from H'0F800 to H'0FFFF, etc. In this case, the external space is divided into two parts, and the program written in the internal ROM and the program existing in the external space are consecutively arranged. Can't use
Contrary to the object of the invention. Therefore, the built-in ROM, which should mainly be the program area, and the built-in peripheral function / built-in RAM, which should be mainly the data area, should be arranged opposite to each other in the address space, and a continuous space should be provided between them. In particular, the built-in ROM must include a start address or an address storing the start address.

The 16-bit absolute address sign-extends the upper 8 bits to generate an effective address. Therefore, the designated range is H'000000 to H'007FFF and H'FF8000 to H'FFFFFF, and the built-in R
OM 32 kbytes and built-in RAM and built-in peripheral functions can be specified. Like the lower CPU, the built-in functional block can be specified by a 16-bit absolute address except for the built-in ROM portion larger than 32 kbytes. Therefore, the software can be easily ported from the lower CPU. In the case of indirect 16-bit displacement register, the displacement matches the reference address and the specified range of the reference address when the contents of the register are interpreted as relative values.

In the above embodiment, the address space is set to 16 Mbytes. Further, although the function expanded in the present invention is required, the address space is 64 as in the conventional case.
A sufficient application of k bytes is also possible.

For example, when all the terminals of the single-chip microcomputer are used as input / output ports and the mounting area of the application system is to be reduced without using the external space, the total internal area should be 64 kbytes or less. For example, the address space is 64 kbytes, which is the same as in the conventional case.

In such an application, vector reading or program counter stacking may be performed in units of 16 bits, that is, 2 bytes. Accessing 4 bytes is wasteful, which reduces execution time and memory utilization efficiency. It will decrease.

Although not particularly limited, the mode operating in the address space of 64 kbytes is the minimum mode, and the mode operating in the address space of 64 kbytes or more is the maximum mode as described above. The minimum mode and the maximum mode are shown in FIG.
It is designated appropriately by the DE3 terminal.

FIG. 23 shows the difference in the operation of the CPU in the minimum mode and the maximum mode.

As described above, the first mode or higher order
In the maximum mode as the mode, the maximum number of addresses is 24 bits, and the vector, the stack at the time of exception processing, and the stack at the time of subroutine call all include addresses of 24 bits and are in units of 4 bytes.

In the minimum mode as the second mode or lower mode , the maximum number of addresses is 16 bits, and the stack at the time of vector subroutine call is reduced to 2 bytes corresponding to 16 bits of the address. .
Although not particularly limited, the CPU 1 has so-called post-increment register indirect / pre-decrement register indirect as an addressing mode, and the address register is updated in the lower 16 bits. That is, the extension address is not updated. The minimum mode can achieve higher speed and higher memory utilization efficiency than the maximum mode.

FIG. 24 shows the data format on the memory in the minimum mode and the maximum mode.

In the maximum mode, the vector is arranged in units of 4 bytes with a multiple of 4 at the head. The first 1 byte is a reserved area, and the remaining 3 bytes are used as a start address. The stack is arranged in 4-byte units with even addresses starting at the time of exception handling and subroutine call.

In the minimum mode, the vector is arranged in 2-byte units with an even address at the beginning. These are used as a start address (lower 16 bits; upper 8 bits are regarded as 0). In the exception processing, the CCR / reserved area and the lower 16 bits of the PC are stored in units of 4 bytes at the beginning of an even address in the exception processing. At the time of subroutine call, PC with an even address at the beginning in units of 2 bytes
The lower 16 bits are stored.

If the minimum mode and the maximum mode are prepared, the CPU 1 operating in the minimum mode
Can achieve upward compatibility at the object program level.

Considering testing such a single-chip microcomputer, it is desirable that the vector area can be used as an external memory in both the minimum mode and the maximum mode. Since the maximum mode effectively uses a wide address, RO
It is considered that the M invalid extended mode is set, and the ROM
In the invalid extended mode, there is no problem because the vector area becomes external memory. However, when the minimum mode is only the single chip mode, it is necessary to use the vector area as an external memory for testing at least. At the time of testing, the contents of the built-in ROM store the user's program and cannot be used by the manufacturer. For this reason, the switching function of the minimum mode / maximum mode vector structure cannot be tested.

To address this, for example, a register capable of reading / writing only in the test mode may be provided so that the minimum mode and the ROM invalid extension mode can be set by setting the bit. Minimum RO
Data may be externally input when the vector area on M is read.

According to the above embodiment, the following effects are obtained. (1) 16-bit general-purpose register of 8-bit CPU
With the form of adding a bit extension register,
A 32-bit register (Ri + Ei) is used as a whole or a part of it is used as an address register, and as a data register, the entire 32 bits are divided into two units and divided into two 16-bit data registers (Ei). , Ri), one of the 16-bit data registers is further divided into two, and two 8-bit registers (Ri
H, RiL). Whether to use it as an 8-bit register or a 16-bit register is determined by the size bit of the data information included in the operation code. When the size of the data information is 8 bits (bytes), the upper (RiH) / lower (RiL) of the 8-bit register is designated by a predetermined 1 bit of the register designation field included in the instruction. When the size of the data information is 16 bits (word), the predetermined 1 bit specifies the upper (Ei) / lower (Ri) of the 16-bit register. The use as a 32-bit register (Ri + Ei) is specified by the prefix code (prefix code) of the instruction including the operation code. Alternatively, a new operation code having the same number of bits as the operation code of the lower CPU is added and designated. As described above, the register configuration of the CPU 1 including the register designation system includes the register configuration of the lower CPU. Based on this, the CPU 1 includes the instruction execution function supported by the lower CPU having the 16-bit general-purpose register. As a result, the program developed for the lower CPU becomes available to at least the level higher CPU 1 of the source program. That is, upward compatibility can be realized at least at the source program level. (2) The number of effective address bits and the unit size of the vector and the stack are stored in the registers Ei, Ri, Ri.
By preparing a maximum mode and a minimum mode as operation modes to be switched according to the usage patterns of H and RiL, the CPI 1 operating in the minimum mode is
Upward compatibility at the object program level can be realized. (3) By using a prefix code for instructions that use longword data, a new operation code is used even if the instruction system does not perform direct operations between memory and registers, but performs major operations between registers. It is possible to deal with the case where it is difficult to add the control unit, and it is possible to remarkably suppress the increase in the logical and physical scale of the control unit. (4) By adopting a code corresponding to the code of the undefined instruction as the prefix code, duplication with other operation codes can be completely prevented. (5) The 32-bit registers Ri and Ei are used collectively or partially as address registers, and divided into two 16-bit data registers, and one of the 16-bit data registers is used as an 8-bit register. By making it available, a wide address space of 16 Mbytes can be used while efficiently performing data processing. (6) By setting the instruction length to 2 bytes and the 24-bit absolute address displacement to 4 bytes including the reserved area, an address space of 4 Gbytes can be used in the future. (7) By making the number of registers that can be used as 8-bit registers equal to the number of registers that can be used as 16-bit registers, the instruction length can be shortened and the program efficiency can be improved. (8) By configuring the register designating part in the instruction code with 3 bits designating the entire register and 1 bit designating the register part, the logical selection of the register selection circuit
The physical scale can be reduced. (9) By setting the least significant bit of the effective address designation section in the instruction code to be the least significant bit of the word in the instruction code, the configuration of the execution section and the control section can be simplified and the logical and physical scale can be reduced. . (10) The address space of 64 kbytes or more can be used by minimizing the logical and physical scale of the single-chip microcomputer 100.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, the block configuration of the CPU 1, the register configuration, a specific example of a logic circuit, etc. are not limited at all. The number of bits of the register or the number of registers can be arbitrarily selected. The addressing mode and the calculation method of the effective address can be changed variously.

In the above description, the case where the invention made by the present inventor is applied to a single-chip microcomputer in the field of application which is the background of the invention has been mainly described, but the invention is not limited thereto and other data processing devices can be used. It is applicable and can be applied when the scale of data is more important than the data processing performance.

[0083]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Lower C including the register designation method
By including the register configuration of another data processing device such as PU and the instruction execution function of the lower CPU, the program developed for the lower CPU is at least at the level of the source program, and the data processing according to the present invention is performed. The device can be used, and at least upward compatibility at the source program level can be realized. (2) By preparing in advance an operation mode (first mode, second mode) for switching the number of bits of an effective address and the unit size of a vector and a stack according to the usage pattern of the register, Upward compatibility at the program level will be easily realized. (3) 16 bits in the 16-bit general-purpose register of the 8-bit CPU
A data holding means having a total of 32 bits by adding a bit extension register is used to hold the data, either all or divided into two, or one divided into two and used. It is possible, which makes the data holding means easy to use on software as well as on hardware, and thus it is possible to reduce the logical and physical scale of the data processing device. Further, regarding the point of holding the address data using the whole or a part of the data holding means, the linearly usable address space can be easily expanded, and the program can be created as compared with the address space expansion technique by the page register. Also, compilation can be facilitated. Therefore, a program created in a high-level language can be efficiently executed. (4) Considering an operation instruction of n-bit data and an operation instruction of 2n-bit data, a part used by dividing the whole into two equal parts and one part divided into two equal parts are further divided into two equal parts and used. And each individual data holding means is configured so that the total number of parts used in the equal division is equal to the total number of parts used in the equal division. By providing a plurality of units of data holding means, the instruction length can be shortened and the program efficiency can be improved . ( 5) Therefore, it is possible to use part or all of the program already developed for another data processing device such as a lower CPU according to the operation mode while minimizing the increase in logical and physical scale. In addition, it is possible to relatively widen the address space that can be continuously used while realizing the upper compatibility with the lower CPU.

[Brief description of drawings]

FIG. 1 is a block diagram of a single-chip microcomputer according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a register configuration example of a lower CPU.

FIG. 3 is an explanatory diagram showing a data configuration of a general-purpose register of the CPU of FIG.

FIG. 4 is an explanatory diagram of a register configuration of a CPU which is an embodiment of a data processing device according to the present invention.

FIG. 5 is a data configuration diagram on a register of the CPU according to the present embodiment.

FIG. 6 is an explanatory diagram showing an example of an addressing mode and an effective address calculation method by the CPU according to the present embodiment.

FIG. 7 is an explanatory diagram of another example of the addressing mode and the effective address calculation method by the CPU according to the present embodiment.

FIG. 8 is an explanatory diagram of another example of the addressing mode and the effective address calculation method by the CPU according to the present embodiment.

FIG. 9 is an explanatory diagram showing an example of an instruction format of the CPU according to the present embodiment.

FIG. 10 is an explanatory diagram of another instruction format of the CPU according to the present embodiment.

FIG. 11 is an explanatory diagram of another instruction format of the CPU according to the present embodiment.

FIG. 12 is an explanatory diagram of another instruction format of the CPU according to the present embodiment.

FIG. 13 is an explanatory diagram of still another instruction format of the CPU according to the present embodiment.

FIG. 14 is an explanatory diagram of still another instruction format of the CPU according to the present embodiment.

FIG. 15 is an explanatory diagram of still another instruction format of the CPU according to the present embodiment.

FIG. 16 is an explanatory diagram of a part of the remaining instruction formats of the CPU according to the embodiment.

17 is an explanatory diagram related to a designation mode of the registers shown in FIG. 4. FIG.

FIG. 18 is an example block diagram of a CPU according to the present embodiment.

FIG. 19 is an explanatory diagram showing a combination of a CPU instruction and an addressing mode according to the present embodiment.

FIG. 20 is an explanatory diagram of an instruction format using a prefix code.

FIG. 21 is an explanatory diagram of another instruction format using a prefix code.

FIG. 22 is an address map of a microcomputer according to an embodiment of the present invention.

FIG. 23 CP in minimum mode and maximum mode
It is explanatory drawing which shows the difference of operation | movement of U.

FIG. 24 is an explanatory diagram showing a difference in data format on a memory between the minimum mode and the maximum mode.

[Explanation of symbols]

1 CPU 2 ROM 3 RAM 4 timer 5 SCI 100 single-chip microcomputer Ri (R0L, R0H to R7L, R7H) general-purpose register E (E0 to E7) extension register PC program counter SEL selector circuit unit EXE execution unit CONT control unit REGSEL register Select circuit units ABL, ABH, ABE Address buffers ALUL, ALUH, ALUE Arithmetic logic operation units RDBL, RDBH, RDBE Read data buffers RDB1, RDB3 First read data buffer parts RDB2, RDB4 Second read data buffer parts WDBL, WDBH , WDBE write data buffer WDBOL, WDBOH write data output buffer

Continuation of the front page (56) Reference JP-A-2-146628 (JP, A) JP-A-63-113635 (JP, A) JP-A-64-93847 (JP, A) JP-A-64-91236 (JP , A) Yukio Kaneda, Microprocessor and RISC, Ohmsha Co., Ltd., May 25, 1991, first edition, p. 27-132 Nobuyuki Nakajima, 80386 Protected Mode Utilization Research, Interface, CQ Publishing Co., Ltd., September 1, 1990, Volume 16, No. 9, p. 147-174 Kenji Kani and 6 others, V Series Microcomputer I, Maruzen Co., Ltd., January 20, 1986, 1st edition, p. 32-37 Kenji Kani and 6 others, V Series Microcomputer II, Maruzen Co., Ltd., April 30, 1987, 1st edition, p. 104- 109 (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/30-9/36

Claims (7)

(57) [Claims] 1. A data processing device having a first mode and a second mode, each of which has a predetermined bit length, and a plurality of general-purpose registers each having a first part and a second part, A first arithmetic logic operation unit coupled to the first portion of the plurality of general purpose registers and a second arithmetic logic operation unit coupled to the second portion of the plurality of general purpose registers; One mode enables the first arithmetic logic operation unit and the second arithmetic logic operation unit to perform an address operation and a data operation, and the second mode is the second arithmetic logic operation unit. Is capable of performing an address operation and a data operation, and the first arithmetic logic operation unit is capable of performing a data operation. Data processing equipment. 2. Whether to operate in the first mode or the second mode
2. The data processing device according to claim 1, further comprising an external terminal for receiving a mode signal that determines whether to operate in a mode. 3. A central processing unit having the plurality of general-purpose registers, the first and second arithmetic and logic operation units, and a central processing unit coupled to the central processing unit, wherein one of the plurality of general-purpose registers is connected to the central processing unit. An internal bus supplied with an address signal, a first memory coupled to the internal bus for holding program data of the data processing device, and coupled to the internal bus to provide a working area for the central processing unit. The central processing unit has an address space including a first region including a region in which the address of the first memory is arranged and a region including a region in which the address of the second memory is arranged. Between the second area and the first area and the second area, and And a third region for less, the address space of the third area when the first mode,
2. The data processing device according to claim 1, wherein the data processing device is wider than the address space of the third area in the second mode. 4. The first part is an upper register,
The second portion is a lower register, and the upper register and the lower register are:
Work in concert to define combinational registers,
4. The data processing apparatus according to claim 3, wherein address data is held in the combination register, and address data is held in the lower register in the second mode. 5. A plurality of general-purpose registers, each of which includes a first portion having a first predetermined bit length and a second portion having a second predetermined bit length, and coupled to the first portion of the plurality of general-purpose registers. and a first arithmetic logic unit, a second arithmetic logic unit coupled to the second portion of the plurality of general purpose registers, coupled to said first and second arithmetic logic unit, the dynamic
Depending on the work mode and a mode control means for controlling an operating state of said first and second arithmetic logic unit, said mode control means, in the case of higher order modes, said first and second arithmetic logic Both of the units cooperate to extract the first address part from the first part, the second address part from the second part, and execute the address operation for accessing the first address space. And controlling the first and second arithmetic logic operation units, and in the case of the lower mode, the second arithmetic logic operation unit takes out the second address part and stores the first address space smaller than the first address space. A data processing device, which executes an address operation for accessing two address spaces and controls the first and second arithmetic logic operation units. 6. The first part is an upper register,
The second part is a lower register, and the upper register and the lower register are:
Work in concert to define combinational registers,
6. The data processing apparatus according to claim 5, wherein address data is held in the combination register, and address data is held in the lower register in the lower mode. 7. A plurality of general purpose registers, each including a first portion having a first bit length and a second portion having a second bit length, and a first portion coupled to the first portion of the plurality of general purpose registers. And a second arithmetic logic operation unit coupled to the second portion of the plurality of general purpose registers to prepare a data processing device having two modes, a first mode and a second mode. In the first mode, in order to process an address larger than the second bit length, the first and second arithmetic logic operation units are cooperatively used to perform an address operation, or Performing a data operation using the first and second arithmetic logic operation units in cooperation to process data larger than a first bit length; and in the second mode. , In order to process the address of the second bit length, using said second arithmetic logic unit, and executes the address calculation, the first
Performing a data operation using the first arithmetic and logic unit for processing bit-length data.