JP3154542B2 - Data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and a microcomputer, for example, a single-chip microcomputer and its central processing unit (CPU).
It is related to technology that is effective to use.

[0002]

2. Description of the Related Art Single-chip microcomputers include 4-bit, 8-bit, and 16-bit microcomputers depending on the data length mainly handled by these central processing units. At present, among these, an 8-bit single-chip microcomputer is most frequently used, and is used for controlling embedded devices. As such an 8-bit single-chip microcomputer,
Issued in June 1989 by Hitachi, Ltd. “H8 / 330 H
D6473308 HD64333308 Hardware Manual. Central processing unit of 8-bit single-chip microcomputer (hereinafter referred to as 8-bit CP)
U) mainly deals with a data length of 8 bits, so that an 8-bit CPU has an 8-bit register or accumulator, and 1 which is twice as long as an 8-bit register.
It has a 6-bit register. These 8-bit CPUs
Although there is no particular limitation, an 8-bit register or a 16-bit register is mainly used for data processing, and only a 16-bit register is used as an address register for referring to a memory. Such a 16-bit register as an address register may be called an index register, a stack pointer, a program counter, or the like.

In the 8-bit CPU, the minimum instruction unit is 16 bits (2 bytes). Further, when arranging an instruction or 16-bit data in a memory, it is limited to arranging it in a continuous 2-byte area starting from an even number. Further, the operation instruction of the 8-bit CPU can be performed only between the registers in the CPU, and the operation of the data arranged in the memory must be performed after the data is once transferred to the register in the CPU. Must. Instead of having these limitations,
The internal configuration of the CPU, particularly the configuration of a control unit that controls the execution state of the CPU, is simplified, and the logical and physical scales are reduced. As a result of reducing the logical and physical scale, manufacturing costs can be reduced. Further, as a secondary effect, the operation speed can be improved. That is,
A relatively large processing performance can be realized with a relatively small manufacturing cost.

[0004] However, in the 8-bit CPU,
Since the address register is 16 bits long, the memory that can be referred to by the CPU is 65536 bytes (= 2 ¹⁶ , 6
4 kbytes). On the other hand, in the application of built-in device control using an 8-bit single-chip microcomputer, it is required to handle a large amount of programs or data due to the high performance of the device. In response to such a demand, the present inventor has reduced the logical and physical scales of the CPU, or at a relatively low manufacturing cost, while maintaining the feature of realizing a relatively large processing performance. A CPU that can refer to a memory of 64 kbytes or more was studied.

On the other hand, an 8-bit CPU is provided with an 8-bit page register and combined with a 16-bit register to generate 16777216 bytes (= 2 ²⁴ , hereinafter 16 Mbytes) of memory that can be referred to by generating an address.
"H8 / 532" issued by Hitachi, Ltd. in December 1988 as an example of a single-chip microcomputer
HD64753328 HD6435328 Hardware Manual. In such a memory reference method, since the page register and the address register are completely independent, the hardware implementation method is simplified, but no carry or borrow is propagated between the page register and the address register. When creating a program or compiler, care must always be taken to ensure that a group of programs or data does not cross page boundaries. That is, in the above example, when the instruction is executed from address 0, the program counter initially reads H'0000.
(H 'indicates a hexadecimal number), and the corresponding page register (hereinafter, code page register) is H'00.
Continue to execute operation instructions without using branch instructions,
After the address reaches 535 (H'FFFF), when the next instruction is executed, the program counter becomes H'FFFF.
F → H′0000 and overflow. Since the carry at this time is not propagated to the code page register,
The next instruction returns to address 0. For this reason, the program is divided and created so as not to exceed 64 Kbytes, and the divided programs are allocated to different pages, respectively, and when the execution is transferred from the program existing on one page to the program existing on another page, the program is called a page. It is necessary to use an inter-branch instruction. That is, when using a branch instruction in a program, whether the branch destination exists in the same page,
It is necessary to use an intra-page branch instruction and an inter-page branch instruction in consideration of whether the instruction exists on another page. Similarly, data must be divided and managed so as not to exceed 64 Kbytes. That is, when the contents of the address register are updated each time the memory is accessed as in the so-called post-increment register indirect mode, the corresponding page register (hereinafter referred to as the data page register) is stored even if the address register overflows as described above. Carry is not propagated. When a 16-bit displacement is used indirectly with a register with a displacement, a 16-bit displacement is added to a 16-bit address register, and the carry or borrow is not propagated to the page register. An address is generated by combining the 16-bit addition result and the page register. That is, if the page register is H'00, the address register is H'FFFF, and the displacement is H'4000, the resulting address will be H'003FFF. Therefore, in the address extension technique using the page register, the usable addressing mode is also substantially limited.

[0006] Managing the page register while always paying attention so that the program or data does not cross a page boundary is to convert the contents programmed using a so-called high-level language into a program (object) in a so-called machine language of a CPU. Program), which greatly reduces the design efficiency of the compiler, significantly increases the size of the object program created, and, as a result, reduces the execution time of the program. Resulting in.

In addition, for applications where a memory space of 64 Kbytes or less is sufficient, the page register cannot be used as a data register, so that it is logically and physically wasted, and the relatively small manufacturing cost. This defeats the purpose of realizing relatively large processing performance.

[0008]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data processing apparatus capable of relatively expanding a continuously usable address space while minimizing an increase in logical and physical scales. 64k using 8-bit CPU
An object of the present invention is to provide a data processing device capable of continuously using an address space of bytes or more. Another object of the invention is
Another object of the present invention is to provide a data processing device capable of efficiently executing a program created in a high-level language. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, as a register of the CPU,
All or part of the data is used to hold the data, or one of the two parts is used by further dividing it into two parts, and the whole or a part is used to hold the address data. Data holding means to be used. For example,
A 16-bit extension register is added to a 16-bit general-purpose register of an 8-bit CPU, and a 32-bit register is used collectively or a part of the 32-bit register as an address register. Make one of the 16-bit data registers available as an 8-bit register.

In consideration of an operation instruction of n-bit data and an operation instruction of 2n-bit data, in order to shorten the instruction length and improve the program efficiency, a part used by dividing the whole into two equal parts, Each data holding means is configured so as to have a portion that is used by equally dividing one of the equally divided portions, and the total number of portions used in the equally divided portion is further divided into two equal portions. It is preferable to provide a plurality of units of the data holding means so as to be equal to the total number of used parts. For example, a plurality of 32-bit registers are provided so that the number of parts usable as an 8-bit register is equal to the number of parts usable as a 16-bit register.

The instruction unit can be twice as long as the data unit. For example, when the CPU register is expanded to 32 bits, when considering the use of the 4 Gbyte address space in the future, the instruction length is set to 2 bytes, and the 24-bit absolute address displacement is set to 4 bytes including the reserved area. And Further, in order to simplify the configuration of the execution means and the control means and to contribute to the reduction of the logical and physical scale, the least significant bit of the effective address designating part in the instruction code is replaced with the least significant bit of the word in the instruction code. Is desirable.

In order to reduce the logical and physical scale of a selection circuit for the data holding means such as a register, an instruction format in which a portion designating the data holding means is fixed to a part of an instruction unit It is advisable to adopt Further, in that case, the specified portion is an area for specifying a required data holding unit from a plurality of units,
It is preferable that the data storage unit be configured with an area for designating any part in one data holding unit. At this time, the control means determines, based on the data size specified in the instruction, which part of the data holding means specifies which part is divided into two equal parts, It is possible to determine which of the equally divided parts is to be designated.

In order to simplify the configuration of the write buffer means including the data holding means and to reduce the logical and physical scale of the data processing device, the write buffer means needs to have the number of bits of the data holding means. And a second portion having a number of bits matching the number of bits in the equally divided area of the data holding means, and storing the data based on a data write instruction. It is preferable that the contents of the means be stored in the first part in a lump, and the data stored in the first part be transferred to the second part in two divided steps and output. For example, when the data holding unit has 32 bits, the write buffer unit sets the first portion to 32 bits and the second portion to 16 bits.

In order to simplify the structure of the read buffer means for the data holding means and to reduce the logical and physical scale of the data processing device, the read buffer means must match the number of bits of the data holding means. The total number of bits to be read is divided into two equal parts, the upper side and the lower side. Based on the data read instruction, the lower side always stores read data at the time of reading, and the upper side determines whether or not to store the read data. It is better to be specified. For example, the read buffer means is composed of a 32-bit master stage and a 32-bit slave stage, and the lower 16 bits are always input when reading, and the upper side is prohibited from inputting when reading the lower word of long word data. To As a result, the 24-bit effective address designation part and the long word data in the instruction code can be handled in the same manner.

In order to reduce the logical and physical scale of the entire microcomputer in terms of the configuration for bus access, the address space has areas for accessing in different states such as the bus width in the address space, and When there is a data transfer device that performs read / write besides CPU,
The read / write control is performed by a common bus controller, and the bus controller controls the read buffer means and the write buffer means of the CPU or another data transfer device, and further, if necessary, the CPU or another data transfer device. In a standby state.

[0017]

According to the above-described means, 16 bits of the 8-bit CPU are used.
The data holding means, which is constructed by adding a 16-bit extension register to the bit general-purpose register and having a total of 32 bits, can be used to hold the data in whole or in two or in one of two parts. It can be used in two parts, which improves the usability of the data holding means on software and hardware, and achieves a reduction in the logical and physical size of the data processing device.
In addition, in terms of holding address data using the whole or a part of the data holding means, it is easy to expand the address space that can be used linearly. Make compilation easier.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be sequentially described according to the following items. [1] Entire single-chip microcomputer [2] Configuration example of 8-bit extension register + 16-bit general-purpose register [3] Problem of configuration example of 8-bit extension register + 16-bit general-purpose register [4] Configuration example of 16-bit extension register + 16-bit general-purpose register [5] Advantages of 16-bit extension register + 16-bit general-purpose register configuration example [6] Addressing mode and effective address calculation example [7] Instruction format of main addressing mode [8] CPU internal block

[9] Example of instruction execution and exception processing by CPU [10] List of arithmetic operation instructions of CPU [11] List of combinations of instruction functions and addressing modes [12] Example of circuit configuration of registers [13] General-purpose registers and extensions Example of register operation [14] Configuration example of register selector [15] Selector circuit [16] Read data buffer [17] Write data buffer [18] Address buffer [19] Address map of microcomputer [20] Minimum mode Maximum mode [21] Single chip microcomputer operation mode [22] DMA built-in single chip microcomputer [23] Modification of CPU [24] Effects of the embodiment

[1] Overall Single-Chip Microcomputer FIG. 1 shows a single-chip microcomputer as a first embodiment of the data processing apparatus according to the present invention. Single-chip microcomputer 10 shown in FIG.
0 is a CPU (central processing unit) 1 for controlling the entire system, C
A ROM (read only memory) 2 holding an operation program of the PU 1, a RAM (random access memory) 3 used as a work area of the CPU 1 and a temporary storage area of data, a timer 4, a serial communication interface (SCI) 5, It comprises functional blocks such as a clock pulse generator 68 and input / output ports (IOPs) 61 to 67, which are interconnected by an internal bus 69. The internal bus 69 includes, but is not limited to, an address bus, a data bus, and a control bus. The single-chip microcomputer 100 is formed on one semiconductor substrate such as a silicon substrate by a known semiconductor integrated circuit manufacturing technique.

Single-chip microcomputer 10
0 is the terminal XTA of the clock pulse generator CPG
The operation is performed in synchronization with a crystal oscillator connected to L, EXTAL or a reference clock generated based on an external clock input from the outside. The minimum unit of the reference clock is called a state. In the figure, Vss and Vcc are power supply terminals. MODE1 to MODE3 are CPU1
Is a mode signal corresponding to.

When a reset signal RES is applied to the CPU 1, the single-chip microcomputer 100
Is reset. When the reset state is released, the CPU 1 reads a start address and performs a reset exception process for starting reading an instruction from the start address. The start address is stored at address 0, although there is no particular limitation.
Thereafter, although not particularly limited, the CPU 1 sequentially reads and decodes the instructions from the ROM 2 and processes the data or processes the data or the RAM 3, the timer 4, and the S based on the decoded result.
Data is transferred to the CI5, the input / output ports 61 to 67, and the like. That is, the CPU 1 performs processing based on the instructions stored in the ROM 2 while referring to data input from the input / output ports 61 to 67 or instructions input from the SCI 5 or the like. Signals are output to the outside using the ports 61 to 7 and the timer 4 to control various devices.
Although not particularly limited, the ROM 2, RAM 3,
The reading / writing of the timer 4 and the like is executed in two states of both byte (for example, 8 bits) / word (for example, 16 bits).

The minimum unit of the instruction of the CPU 1 is 2 bytes. When the instruction or 16-bit data is arranged in the memory, it is arranged in a continuous 2-byte area starting from an even number.

[2] Configuration Example of 8-bit Extension Register + 16-bit General-purpose Register FIG. 2 shows a first configuration example of a register incorporated in the CPU 1. The CPU 1 has eight general-purpose registers R0L, R0H to R7L, R7H each having a 16-bit length, eight extension registers E0 to E7 each having an 8-bit length,
It has a 24-bit program counter PC and an 8-bit condition code register CCR. The general-purpose registers R0L, R0H to R7L, R7H are
Although there is no particular limitation, it is also possible to store 8-bit data by making upper 8 bits and lower 8 bits independent.
The 16-bit data can also be stored by connecting the upper and lower bits.

General purpose registers R0L, R0H to R7L, R
When 7H is used as an address register, a 16-bit address held by the general-purpose register is used as the lower 16 bits of the address, and the 8 bits held by the corresponding extension register are used as the upper 8 bits of the address, thereby generating a 24-bit address in total. Things. In other words, the CPU 1 can use a continuous address space defined by a maximum of 24-bit addresses. Further, the 24-bit address can be modified in various modes. For example, displacement can be added to the 24-bit address, multiplied by a constant, or the contents of another register can be added. When performing this modification, if a carry or borrow occurs in the calculation of the lower 16 bits, the upper 8 bits
Carry or carry bits. When this result is held in the address register, the result of the upper 8 bits is also held in the corresponding extension register at the same time.

The extension registers E0 to E7 can be used as data registers as well as general-purpose registers. That is, data operations can be performed between extension registers and between the extension register and the general-purpose register.

The program counter PC is a 24-bit counter and indicates the address of an instruction to be executed next by the CPU 1. The condition code register CCR includes an interrupt mask bit (I), a carry flag (C), a zero flag (Z), a negative flag (N), and an overflow flag (V). Interrupt mask bit I
When 1 is set, the CPU 1 is set to the interrupt disabled state, and when 0, the CPU 1 is set to the interrupt enabled state. Other flags reflect the result of the operation and the like.

FIG. 3 shows general-purpose registers R0L, R0H to R0R.
7L, R7H and data configuration examples of extension registers E0 to E7 are shown. The byte data handled by the CPU 1 is the upper RiH (i = 0, 1,..., 7) or lower R
iL or the extension register Ei. When using the upper RiH of the general-purpose register, bit 15 corresponds to the most significant bit (MSB) of the data, and bit 8 corresponds to the least significant bit (LSB). Similarly, when using the lower RiL of the general-purpose register, bit 7 corresponds to the most significant bit, and bit 0 corresponds to the least significant bit. When the extension register Ei is used for byte data, bit 23 corresponds to the most significant bit, and bit 16 corresponds to the least significant bit. Word data is stored in general-purpose registers Ri (RiL and RiL).
H). At this time, bit 15 corresponds to the most significant bit of the data, and bit 0 corresponds to the least significant bit. The address data is stored in the extension register Ei and the general-purpose registers RiL and RiH. Bit 7 of the extension register Ei corresponds to the most significant bit of the address data, and bit 0 of the general-purpose register RiL corresponds to the least significant bit. It should be noted that the CPU 1 also outputs 1-bit data,
Alternatively, binary-coded decimal data and the like are handled, but they are not directly related to the present invention, and therefore detailed description is omitted.

FIG. 4 shows an example of a data configuration of a memory such as the RAM 3 and the ROM 2. Although not particularly limited, the memory is addressed in byte units.
The byte data handled by the CPU 1 is stored at each address of the memory. Word data is stored by connecting even addresses and odd addresses of the memory. Bit 7 of the even address corresponds to the most significant bit of the data, and bit 0 of the odd address corresponds to the least significant bit. Address data is stored in a 4-byte address starting from an even address. One byte of the leading even address is reserved on the system for future expansion. Bit 7 of the next odd address corresponds to the most significant bit of the address data, and bit 0 of the fourth byte of the odd address corresponds to the least significant bit.

[3] Problems of 8-bit extension register + 16-bit general-purpose register configuration example An extension register Ei is added to the 16-bit general-purpose register Ri of the 8-bit CPU 1, and the entirety including the added extension register is collectively used as address data. It makes it possible to access the memory etc. by grasping it, and in this case the address operation grasps as a unit address in both the extension register and the corresponding general-purpose register and processes the carry and borrow generated in the address operation, The address space that can be used linearly can be expanded from 64 kbytes to a maximum of 16 Mbytes as compared with the case where a 16-bit address register is used. However, in this case, the present inventors have clarified that there are the following problems.

First, in the above register configuration, 24 registers can be used as an 8-bit register, 8 registers can be used as a 16-bit register, or 8 registers can be used as a 24-bit register. For example, 8-bit addition is performed. In this case, each of the addition number (source register) and the augend (destination register) requires 5 bits. Since the instruction length is in units of 2 bytes, the minimum instruction length does not become the minimum instruction length for the 8-bit operation unless the operation specification is 6 bits. For a 16-bit operation, the register specification may be 3 bits,
In this regard, it is not difficult or advisable to share the instruction format with the 8-bit operation. Also, 24
It is wasteful to use 5 bits to specify a book register. That is, if there are five bits, a desired register can be specified from the originally 32 registers.

Second, in the case where 24-bit data is arranged in a memory, a reserved area as described with reference to FIG. 4 is required, and the utilization efficiency of the memory is not good. If the reserved area is deleted, it becomes difficult to mix 16-bit data and 24-bit data on the memory. At least, when arranging 16-bit data in a memory, it is limited to arranging it in a continuous 2-byte area starting from an even number, simplifying the internal configuration of the CPU, reducing the logical and physical scale,
The purpose of reducing the manufacturing cost and improving the operation speed is impaired.

Third, except for using 24-bit data as an address, it is difficult to handle as data because it has an odd-byte length. As described above, in the conventional microcomputer, data to be handled is 8 bits or 1 bit.
If it is 6 bits and is used with these conventional microcomputers and can store word data, when transferring data from them, two word data cannot be stored in one register of the CPU 1, and ,
This is because, when word data is transferred to them, the contents of one register of the CPU 1 must be divided into 16 bits and 8 bits. Also, when the above-mentioned compiler is created, it is difficult for a so-called host computer to handle 24-bit data in the same manner as described above, which may reduce the design efficiency and performance of the compiler.

[4] Example of 16-bit extension register + 16-bit general-purpose register configuration An example of a register configuration that can cope with the problem described in the above item [3] will be further described.

FIG. 5 shows a second example of the configuration of the register incorporated in the CPU 1. The CPU 1 has eight general-purpose registers R0L, R0H to R7L each having a 16-bit length.
R7H, eight extension registers E0 to E7 each having a length of 16 bits, and a program counter PC having a length of 24 bits.
And an 8-bit condition code register CCR
And General registers R0L, R0H to R7
Although not particularly limited, L and R7H can store 8-bit data by making upper 8 bits and lower 8 bits independent, or store 16-bit data by connecting upper and lower bits. it can. The extension register Ei is 8
It cannot be divided into bits and used independently.

When the general-purpose registers RiL and RiH are used as address registers, the general-purpose registers RiH and R
The 16 bits held by the iL are set to the lower 16 bits of the address, and the contents of the corresponding extension register Ei are set to the upper 16 bits of the address. Is what you do. CPU1 is 24 bits or 32
A continuous address space defined by bit addresses can be used. Furthermore, this 32 bits or 2
As described above, the 4-bit address can be variously modified.
When a carry or a borrow occurs in the calculation of 6 bits, carry-up or carry-down is performed on the upper-side extension register Ei. In the following description, the address data is 24 bits. Accordingly, the bit length of the program counter PC in FIG. 5 is set to 24 bits. The bit length of the program counter PC may be 32 bits.

The extension registers E0 to E7 can be used as data registers as 16-bit registers like general-purpose registers. That is, data operations can be performed between extension registers and between extension registers and general-purpose registers. Note that the condition code register CCR is the same as described above, and a detailed description thereof will be omitted.

FIG. 6 shows general-purpose registers R0L, R0H to R0R.
7L, R7H and data configuration examples of extension registers E0 to E7 are shown. The byte data handled by the CPU 1 is the upper RiH (i = 0, 1,..., 7) or lower R
stored in iL. Word data is stored in general-purpose register Ri.
(RiH, RiL) or the extension register Ei. At this time, bit 15 corresponds to the most significant bit of the data, and bit 0 corresponds to the least significant bit. The 32-bit long word data is stored in the general-purpose register Ri and the extension register Ei. The 24-bit address data is stored as longword data in the extension register Ei and the general-purpose register Ri. At this time, the upper 8 bits of the extension register Ei are reserved. The reserved 8-bit and 24-bit address data are also simply referred to as long word address data.

FIG. 7 shows an example of a data configuration of a memory such as the RAM 3 and the ROM 2. As described above, the memory is assigned an address in byte units. The byte data handled by the CPU 1 is stored at each address of the memory. Word data is stored by connecting even addresses and odd addresses of the memory. Bit 7 of the even address corresponds to the most significant bit of the data, and bit 0 of the odd address corresponds to the least significant bit. The long word data is stored at a 4-byte address starting from an even address. Bit 7 of the first even address corresponds to the most significant bit of the data, and bit 0 of the fourth byte of the odd address corresponds to the least significant bit.

[5] Advantages of 16-bit extension register + 16-bit general-purpose register configuration example First, in the above-described register configuration, 16 registers are used as an 8-bit register, 16 registers are used as a 16-bit register, and 8 registers are used as a 24-bit register. Can be used.
For both 8-bit and 16-bit operations,
The register specification is 4 bits, and the instruction format can be shared. Also, since 4 bits are used to specify a desired register from 16 registers, there is no waste in the number of information bits for the specification.

Secondly, when long word data is arranged in a memory, a reserved area is not required. When the address has a 24-bit length, waste is generated as described above. When storing long word data, no waste occurs.

Third, in addition to using long word data as addresses, it is easy to handle as data. It is easy to transfer data to and from a conventional microcomputer, and no waste occurs. The same applies to the host computer of the compiler, and the design efficiency and performance of the compiler are not reduced.

Fourth, the register configuration of FIG. 5 has a register bit number of about 4 /
It may be considered that the size of the CPU 1 is tripled and the logical and physical scales of the CPU 1 are increased. On the other hand, as described above, the use efficiency of the memory is improved, and the scale of the program can be reduced for the same processing by improving the performance of the compiler. As a result, the capacity and physical scale of a memory such as a ROM can be reduced, and reduction in the physical scale of the entire single-chip microcomputer is not hindered.
Therefore, the internal configuration of the CPU is simplified, the logical and physical scales are reduced, and the manufacturing cost is reduced and the operation speed is improved. The following description is for the case where the register configuration of FIG. 5 is adopted.

[6] Example of Addressing Mode and Effective Address Calculation FIGS. 8 to 10 show an example of the addressing mode of the CPU 1 and a method of calculating the effective address.

In the register indirect shown in (1) of FIG. 8, an instruction code includes a portion for specifying a register, and a total of 24 bits of the register specified by the instruction code and the contents of the extension register corresponding to the register are addressed. Specifies the address on the memory. Since the address may be 24 bits, the upper 8 bits are ignored.

The register indirect with displacement shown in (2) and (3) of FIG. 8 is the result of adding the displacement included in the instruction code to the 24-bit address obtained in the same manner as the register indirect. Is used to specify an address on the memory. The addition result is used only for specifying the address, and is not reflected in the contents of the extension register Ei and the general-purpose register Ri. Although not particularly limited, the displacement is 24 bits or 16 bits, and when adding the 16-bit displacement, the upper 16 bits are sign-extended.
That is, the upper 16 bits of the displacement are 1
The addition is performed assuming that the value is the same as the bit 15 of the 6-bit displacement. In this case, in the upper 8 bits of the 24-bit displacement, a 32-bit displacement designating section is included in the instruction code together with the reserved area, in consideration of the fact that the instruction is in units of 2 bytes and future expansion. .

The post-increment register indirect shown in (4) of FIG. 9 specifies an address on the memory by a 24-bit address obtained in the same manner as the register indirect. Thereafter, 1 or 2 or 4 is added to this address, and the addition result is stored in the extension register / general-purpose register. When specifying byte data in memory, 1
When word data is specified, 2 is added, and when address data is specified, 4 is added. The upper 8 bits of the addition result are also stored in the extension register.

The absolute address shown in FIG. 10 specifies an address on the memory using an 8-bit, 16-bit or 24-bit absolute address included in the instruction code as an address. The upper 16 bits of the 8-bit absolute address are extended by one. That is, bits 23 to 8 of the address are all 1s. Therefore, the usable address is H '
FFFF00 to H'FFFFFF are 256 bytes. The upper 8 bits of the 16-bit absolute address are sign-extended. That is, if bit 15 of the 16-bit absolute address is 0, bits 23 to 16 of the address are all 0s, and if bit 15 is 1, all bits 23 to 16 of the address are 1s. Therefore, usable addresses are 64 kbytes of H'000000 to H'007FFF and H'FF8000 to H'FFFFFF.

The pre-decrement register indirect shown in (5) of FIG. 9 is obtained in the same manner as the register indirect.
An address on the memory is specified by a 24-bit address obtained by subtracting 1 or 2 or 4 from the 4-bit address. Thereafter, the result of the subtraction is stored in the extension register / general-purpose register. When specifying byte data on the memory, 1 is subtracted, when word data is specified, 2 is specified, and when address data is specified, 4 is subtracted. As described above, when the address may be 24 bits, the upper 8 bits of the subtraction result are stored in the extension register, although there is no particular limitation.

The program counter relative shown in (6) of FIG. 9 designates an address on the memory as a result of adding a displacement included in the instruction code to a 24-bit address of the contents of the program counter. The addition result is stored in the program counter. Although not particularly limited, the displacement is 16 bits or 8 bits, and when these displacements are added, the upper 8 bits or 1 bit is added.
Six bits are sign-extended. That is, the addition is performed assuming that the upper 8 bits of the displacement have the same value as bit 15 of the 16-bit displacement, or the upper 16 bits have the same value as bit 7 of the 8-bit displacement. Program counter relative is used only for branch instructions.

In addition to the above, the CPU 1
Addressing modes such as register direct are executed, but since these are not directly related to the present invention, detailed description is omitted.

[7] Instruction Format in Main Addressing Mode FIGS. 11 to 18 show instruction formats of instructions in the main addressing mode. The format of each instruction has an operation code part op for indicating the function and addressing mode of each instruction, and a register specification part (rs, rs,) for specifying a register to be used according to the operation code of the operation code part op. rd, e
rs, erd), absolute address (aa), displacement (d), or immediate (xx). The instruction format is in units of 2 bytes, and the register designating section stores bits 7 to 4 and bits 3 to 0 of the first word of the instruction code or bit 1 as a special form.
1 to bit 8 are included. The register specifying unit rs specifies a byte or word size source register, and the register specifying unit rd specifies a byte or word size destination register. Whether the register to be specified is of byte size or word size is determined by the operation code of the operation code section. That is, in the case of accompanying an operation code involving a 16-bit operation, the lower 3 bits of the register specification sections rs and rd
The bit designates one of the eight registers R0 to R7, and whether to use the extension register or the general-purpose register among the designated registers is determined by the remaining upper one bit of the register designation unit. Specified by 8
In the case of accompanying an operation code involving a bit operation, the lower three bits of the register specification parts rs and rd are 8 bits.
This register R0 to R7 is specified, and whether the upper side or the lower side of the general-purpose register is used among the specified registers is determined by the remaining upper one bit of the register specification section. It is determined. The register specifying unit ers specifies a longword-sized source register, and the register specifying unit erd specifies a longword-sized destination register. The most significant one bit of the register designation parts ers, erd, which are reserved for four bits, is substantially ignored during instruction decoding.

Absolute address aa, displacement d, immediate xx in the instruction format
Are included in the instruction code such that the least significant bit is an even-numbered bit 0. That is, the absolute address aa, displacement d, and immediate xx of 16 bits or more are included in units of 2 bytes. Therefore, 2
4-bit absolute address aa, displacement d
Is 4 bytes including a reserved portion of a predetermined number of bits in an area of 1 byte at the head (upper bit side). The 8-bit absolute address aa, displacement d, and immediate xx are included in bits 7 to 0 of the first word.

According to the above instruction format, the following effects can be obtained. (1) Since the part specifying the register in the instruction format is fixed to one part of the first word of the instruction, the decoding logic configuration of the instruction is simplified. (2) Determine which of the eight registers is to be specified by the lower three bits of the register specification area,
The upper one is used to determine which area of the register is to be used.
The size of the area determined by the bits and the size of the area determined by the one bit is determined by the data size specified in the instruction, in other words, by the operation code of the operation code section. Also, when address data covers several types of bytes, words, and long words, the number of bits in the register designation section can be minimized.

[8] Internal Block of CPU FIG. 19 shows an internal block diagram of the CPU 1. CP
U1 is mainly composed of a micro ROM or PLA (Pl
The control unit CONT is composed of a programmable logic array, and the general-purpose registers R0L, R
0H to R7L, R7H, an execution unit EX including extension registers E0 to E7, a program counter PC (PCL, PCH, PCE), a condition code register CCR, and the like.
E and a register selection unit REGSEL.
The control unit CONT fetches an instruction, decodes the instruction,
It generates various control signals necessary for the execution of the instruction and controls the execution procedure of the instruction. The register selection unit REGSEL is
A register selection signal is generated according to the result of decoding the instruction.

The execution unit EXE further includes temporary registers TRL, TRH, TRE, arithmetic logic units ALUL,
ALUH, ALUE, read data buffer RDBL,
RDBH, RDBE, write data buffer WDBL,
WDBH, WDBE, and address buffers ABL, A
BH, ABE, and these three internal buses A (L,
H, E), B (L, H, E), C (L, H, E), and the selector circuit SEL. The read data buffers RDBL, RDBH, and RDBE are connected to external data buses D7 to D0 and D15 to D8.
Write data buffers WDBL, WDBH, WDBE
Are write data output buffers WDBOL, WDBOH
Are connected to the data buses D7 to D0 and D15 to D8. Arithmetic logic units ALUL, ALUH, ALU
E is used for various operations specified by the instruction, addition of the program counter PC, calculation of the effective address, and the like. Read data buffers RDBL, RDBH, RDB
E temporarily stores an instruction or data read from the ROM 2, the RAM 3, or an external memory (not shown), and stores write data buffers WDBL, WDBH, and WDBH.
The DBE temporarily stores data to be written in the ROM 2, RAM 3, external memory, or the like. Thus, the timing of the internal operation of the CPU 1 and the timing of the read / write operation outside the CPU 1 are adjusted. The address buffers ABL, ABH, and ABE temporarily store addresses to be read / written by the CPU 1.

Although not particularly limited, each circuit block in the execution unit EXE is basically composed of two blocks of 8 bits and one block of 16 bits. The general-purpose register is composed of two 8-bit blocks.
R7H correspond to bits 15 to 8, and R0L to R7L correspond to bits 7 to 0. The higher-order bits of the general-purpose register, that is, bits 31 to 16 correspond to one block of 16-bit extension registers E0 to E7. In the internal bus, A, B, and C buses are provided in parallel corresponding to the bits 31 to 16, the bits 15 to 8, and the bits 7 to 0, respectively. The same applies to the temporary registers TR, ALU, read data buffer, write data buffer, and the like. These physical arrangements are not particularly limited.

[0057]

[9] Example of Instruction Execution and Exception Processing by CPU Representative instruction execution processing and exception processing of the CPU 1 will be described based on the flowcharts shown in FIGS.

In the reset exception handling shown in FIG.
The CPU 1 reads a start address stored in a 4-byte address starting from address 0. Note that, of the four bytes, one byte at address 0 is reserved for future expansion as described above and is ignored. CPU1 is the first
In a step, the interrupt mask bit I is set to "1".
At the same time, data 0 is generated on the bus A inside the CPU 1 and transferred to the address buffers ABL, ABH, and ABE (hereinafter, also simply referred to as AB).
UH, ALUE (hereinafter, also simply referred to as ALU) adds 2 to it. Addition result is temporary register TR via C bus
L, TRH, and TRE (hereinafter simply referred to as TR). In a second step Sa2, reading of word data is started with the contents of the address buffer AB as an address. In the third step Sa3, the read operation is completed, and the read word data is stored in the read data buffer RDBE,
Stored in RDBL, RDBH. At the same time, the contents of the temporary register TR are output to the bus A, and the address buffer A
Transfer to B. In a fourth step Sa4, reading of word data is started using the contents of the address buffer AB as an address. In the fifth step Sa5, the read operation is completed, and the read word data is stored in the data buffer RDB.
L and RDBH. At this time, the read data buffer holds data in a so-called first-in first-out format, although there is no particular limitation. In the sixth step Sa6, the third step Sa3
And the read data buffer RDB in the fifth step Sa5.
The 32-bit data stored in E, RDBH, and RDBL are output to the bus A as a start address, transferred to the address buffer AB, and incremented by 2 in the ALU.
The addition result is sent to the program counter PC (P
CL, PCH, PCE). Note that the upper 8 bits of the data stored in the data buffer RDBE in the third step Sa3 are ignored as described above. In a seventh step Sa7, the reading of the head instruction of the program is started in word units using the contents of the address buffer AB as an address. In an eighth step Sa8, the read operation is completed, and the read word data is stored in the data buffer RDB.
L and RDBH. Actually, the data is further transferred to the instruction read data buffer RDBI shown in FIG. At the same time, the contents of the program counter PC are output to the bus A and transferred to the address buffer AB.
Add 2 in LU. The addition result is the program counter P
Store in C. In the ninth step Sa9, the reading of the third and fourth byte instructions of the program is started by using the contents of the address buffer AB as an address.
Further, in the eighth step Sa8, the data buffer RDB
The instructions stored in the L and RDBHs (actually the instructions held in the instruction read data buffer RDBI) are sent to the control unit CON.
Transfer to T and start decoding. From the next step, an operation is started based on the instruction that has started decoding in the ninth step Sa9, which is the first instruction of the program. The word data whose reading has been started in the ninth step Sa9 is stored in a predetermined read data buffer during execution of this instruction.

FIG. 21 shows a processing flow of an instruction for transferring immediate data to a register. For example, the instruction (MOV.B # 34, R0L) for transferring the data 34 to the general-purpose register R0L is not particularly limited, but as described above, includes the immediate data 34 in the instruction code and has an instruction length of 2 bytes. And In the first step Sb1, this instruction terminates the instruction executed immediately before or the read operation started in the last step of the exception processing, and stores the read word data in the read data buffers RDBH and RDBL (RDBI). At the same time, the contents of the program counter PC are output to the bus A, transferred to the address buffer AB, and 2 is added by the ALU. The addition result is stored in the program counter PC.
In the second step Sb2, based on the contents stored in the address buffer AB, the reading of the third and fourth bytes of the instruction from this instruction is started with a word. At the same time, the immediate data 34 included in this instruction code already stored in the data buffers RDBH, RDBH is transferred to the bus A.
, Passes through the ALU, is output from the ALU to the bus C, and is transferred to the register R0L. When the data passes through the ALU, the data is inspected and reflected in the Z and N flags of the condition code register CCR. Further, the first step Sb1
Transfers the instruction stored in the read data buffer RDBI to the control unit CONT, and starts decoding. From the next step, the operation based on the next instruction, the instruction that started decoding in the second step Sb2, is started. Second step S
The word data whose reading has been started in b2 is stored in a predetermined read data buffer during execution of this instruction.

FIG. 22 shows an instruction for transferring the contents of the memory to the register in the register indirect addressing mode with displacement. For example, register R
0 and the relative value 12 in the address indicated by the extension register E0.
34 to transfer the byte data to the general-purpose register R1H from the address obtained by adding the address {MOV. B ＠ (1234, E
R0), R1H} are not particularly limited, but as described above, the displacement 1234 is included in the instruction code.
And an instruction length of 4 bytes. This instruction is
At step Sc1, the read operation started in the last step of the instruction executed immediately before or of the exception processing is terminated, and the read word data (the third and fourth bytes of this instruction) are stored in the read data buffers RDBE, RDBH, and RDBL. Store. At the same time, the contents of the program
To the address buffer AB, and further to AL
Add 2 with U. The addition result is the program counter PC
To be stored. In the second step Sc2, based on the contents stored in the address buffer AB, the reading of the next instruction, which is the third and fourth byte instructions from this instruction, is started with a word. At the same time, the data buffers RDBH, R
The displacement 1234 included in the instruction code stored in the DBL is transferred to the bus B by the general-purpose register R0.
And the contents of the extension register E0 are output to the bus A, these are added by the ALU, output from the ALU to the bus C, and transferred to the temporary register. Upon addition, the displacement is expanded to 00001234. In the third step Sc3, the read operation is completed, and the read word data is stored in the read data buffers RDBH and RDBL and the read data buffer for instruction RDBI. At the same time, the contents of the temporary register TR are output to the bus A and transferred to the address buffer AB. In a fourth step Sc4, data reading is started in bytes using the contents of the address buffer AB as an address. In a fifth step Sc5, the read operation is completed, and the read byte data is stored in the read data buffer. As described above, the contents of the program counter PC are transferred to the address buffer AB, and 2 is added. In a sixth step Sc6, data reading is started in bytes using the contents of the address buffer AB as an address. The data stored in the data buffer in the fifth step Sc5 is output to the bus A, passes through the ALU,
To the bus C and transfer it to the register R1H. AL
When passing through U, the data is inspected and reflected in the Z and N flags of the condition code register CCR. The command stored in the read data buffer RDBI in the third step Sc3 is transferred to the control unit CONT, and decoding is started. From the next step, the operation of the next instruction is started as described above.

FIG. 23 shows an example processing flow of an instruction for register-transferring the contents of a memory in the post-increment register indirect addressing mode. For example, from the address indicated by the general-purpose register R7 and the extension register E7, the extension data is transferred to the general-purpose register R2 and the extension register E2.
(MOV.L @ ER7 +, ER2)
Is an instruction length of 2 bytes, although there is no particular limitation. In the first instruction Sd1, in the first step Sd1, the immediately preceding instruction or the read operation started in the last step of the exception processing is completed, and the read word data is stored in the data buffers RDBH and RDBL and the instruction read data buffer RDBI. Store. Second step Sd2
Then, the contents of the register R7 and the extension register E7 are output to the bus A and transferred to the address buffer AB, and at the same time, the ALU
Is added, and the result is stored in the general-purpose register R7 and the extension register E7. In a third step Sd3, data reading is started in words using the contents of the address buffer AB as an address. In the fourth step Sd4, the read operation is completed, and the read word data is stored in the read data buffers RDBH, RDBL. At the same time, general-purpose register R
7 and the contents of the extension register E7 are output to the bus A and transferred to the address buffer AB, and at the same time, 2 is added by the ALU. The addition result is stored in the general-purpose register R7 and the extension register E7. In a fifth step Sd5, data reading is started in words using the contents of the address buffer AB as an address. The read operation is completed in a sixth step Sd6,
Reads the read word data into a read data buffer RDB
H, RDBL. As described above, the contents of the program counter PC are transferred to the address buffer AB, and 2 is added. In the seventh step Sd7, the address buffer A
Data reading is started with a word using the contents of B as an address. The data stored in the read data buffers RDBH and RDBL are output to the bus A, passed through the ALU,
The signal is output from U to the bus C and transferred to the general-purpose register R2 and the extension register E2. When the data passes through the ALU, the data is inspected and reflected in the Z and N flags of the condition code register CCR. In the first step Sd1, the data buffer R
The command stored in the DBI is transferred to the control unit CONT, and decoding is started. From the next step, the operation of the next instruction is started as described above.

FIG. 24 shows an example processing flow of an instruction for transferring the contents of a register to a memory in the pre-decrement register indirect addressing mode. For example, the instruction (MOV.LER2,... -ER7) for transferring the extension data from the address indicated by the general-purpose register R7 and the extension register E7 to the general-purpose register R2 and the extension register E2 is not particularly limited, but is a 2-byte instruction. Let it be long. In the first step Se1, the instruction executed immediately before or the read operation started in the last step of the exception processing is completed, and the read word data is stored in the read data buffers RDBH and RDBL and the instruction read data buffer RDBI. Store. In the second step Se2, the contents of the register R7 and the extension register E7 are output to the bus A, 4 is subtracted by the ALU, and the result is stored in the general register R7.
Is stored in the extension register E7. Third step Se3
Then, the contents of the register R7 and the extension register E7 are output to the bus A again, and are transferred to the address buffer AB.
LU is added with 2 and the result is stored in temporary register TR. In a fourth step Se4, the contents of the general-purpose register R2 and the extension register E2 are output to the bus B and stored in the write data buffers WDBE, WDBL and WDBL.
Start writing data in words. The upper 16 bits simultaneously write data output buffers WDBOH and WDOH.
The data is transferred to the BOL and output to the data buses D15 to D0. In a fifth step Se5, the write operation is completed, and the contents of the temporary register TR are output to the bus A and transferred to the address buffer AB. In the sixth step, data writing is started with a word. Write data buffer WDB
H and the lower 16 bits of WDBL are transferred to the write data output buffers WDBOH and WDBOL, and the data bus D
15 to D0. At the sixth step Se6, the write operation is completed, and the read word data is stored in the read data buffers RDBH, RDBL. As described above, the contents of the program counter PC are transferred to the address buffer AB, and 2 is added. In a seventh step Se7, data reading is started in words using the contents of the address buffer AB as an address. The contents of the general-purpose register R2 and the extension register E2 are output to the bus A and passed through the ALU.
When the data passes through the ALU, the data is inspected and reflected in the Z and N flags of the condition code register CCR. First
At step Se1, the instruction stored in the data buffer RDBI is transferred to the control unit CONT, and decoding is started. From the next step, the operation of the next instruction is started as described above.

[10] List of Arithmetic Operation Instructions of CPU FIG. 25 shows a list of arithmetic operation instructions of CPU 1. The arithmetic operation specifically includes addition, subtraction, and comparison.

As the addition instruction, ADD, A
There is a DDC instruction, and the ADD instruction has a byte size, a word size, and a long word size. ADD
The instruction adds specified source data (immediate or register contents) and destination data (register contents), stores the result in the destination register, and stores the result in C, V,
This is reflected on each of the Z and N flags. Although there is no particular limitation, no operation is performed on the contents of the memory and the contents of the registers.

The ADD instruction has a byte size, a word size, and a long word size due to the nature of the data operation instruction. The ADD instruction is the same as the ADD instruction, but the addition is performed including the carry flag C. ADD
The C instruction preferably has a byte size, a word size, and a long word size because of its nature as a data operation instruction.
Instructions are not required unless they deal with data of 33 bits or more. On the other hand, if the ADDC instruction has only the byte size, the instruction format and internal control system of the CPU 1 can be simplified, and the logical and physical scales can be reduced. Although there is no particular limitation in consideration of the necessity and the scale of reduction, the ADDC instruction has only a byte size. The longword size is used for calculating address data, and performs addition by combining a general-purpose register and an extension register.

As a comparison instruction, there is a CMP instruction, and there is no comparison instruction with carry. As the subtraction instruction, there are a SUB instruction and a SUBC instruction for each function, and their contents are different from the addition instruction only in the function of subtraction.

In FIG. 25, #x: 8, #x: 16
Denotes 8-bit and 16-bit immediate data, Rd8 and Rd16 denote 8-bit and 16-bit general-purpose registers, respectively, and Ed: Rd: 16 denotes the contents of extension registers and general-purpose registers.

When the general-purpose register Ri and the extension register Ei as described above are provided and a 16-Mbyte address space can be used, the main operation is performed between the registers, and the operation between the memory and the register is not performed directly ( That is, 1
It is advisable to use an instruction system (not performed by instructions). 1
In order to effectively use the 6 Mbyte address space, the complicated addressing mode as described above is required. If such a complicated addressing mode can be executed for many of the operation instructions, the configuration of the control unit CONT becomes complicated, which is against the purpose of minimizing the logical and physical scales. For accessing the memory, data may be transferred to and from the register by the transfer instructions having the various addressing modes described above, and data processing such as operation may be performed on the register. General-purpose register Ri is 8
A maximum of 16 bits can be used, and the general-purpose register Ri and the extension register Ei can be used as a maximum of 16 bits, and data necessary for a certain process can be placed on the register. Alternatively, at least most of the frequently used data can be placed on registers. Therefore, it is considered that there are few cases where inconveniences such as an increase in processing programs and a decrease in execution speed occur.

An instruction that needs to perform an operation on a memory is a bit operation instruction. These are designated as the n-th bit of the address assigned in byte units, but are not data handled in byte units, and each bit has an independent function. For example, in the case of a register that controls the operation of the timer, the timer clock is selected by the 0th bit and the 1st bit. The third bit specifies whether or not to generate an interrupt when the values match. These are 1
It must be set to 1 or cleared to 0 in bit units. Alternatively, a predetermined bit of the input port is 0
If the processing program of the CPU 1 differs depending on whether the data is 1 or 1, it is necessary to determine the 1-bit data. Such 1-bit data must be directly operated on the memory or the register for controlling the timer.
This is because, if the bit operation is performed after the data is once transferred to the register in byte units, an interrupt occurs between the transfer and the bit operation, which causes a problem such as a change in the value of the input port. Therefore, the CPU 1 in this embodiment supports a bit operation instruction for a direct operation between an internal register such as a general-purpose register and an external register such as a control register of a peripheral circuit. It should be noted that the target address of such a bit manipulation instruction is fixed and does not require a complicated addressing mode. It is sufficient that the absolute address and at least the register indirect can be executed. In addition, even in the case of absolute addresses, it is not necessary to be able to use the entire address space, and it is considered sufficient to be able to use only the address range where the timer / input / output port and the like exist. Eight bits are sufficient as the absolute address that can be used to specify such an address range. The use of 16 bits widens the usable address range, but increases the instruction length and complicates the control. It is considered very unlikely that the entire space of 16 Mbytes must be available for at least 24 bits. Therefore, even if a 1-bit or several-bit bit manipulation instruction is directly issued to an external peripheral circuit, there is no possibility that the scale of the control unit or the type of instruction will be extremely increased.

[11] List of Combinations of Instruction Functions and Addressing Modes FIG. 26 shows an example of the relationship between combinations of instruction functions and addressing modes. In the figure, # is immediate, R is register direct, ＠R is register indirect, ＠
(D16, R) and ＠ (d24, R) are register indirect with displacement, ＠ −R is indirect with predecrement register, ＠ R + is indirect with postincrement register, ＠ a8, ＠ a16, ＠ a24 are absolute address,
(D8, PC) and ＠ (d16, PC) mean each addressing mode relative to the program counter. Also, in the figure, B means byte, W means word, and L means long word. The program counter relative is used exclusively for branch instructions. Other addressing modes can be used with transfer instructions. The operation instruction can use immediate and register directly. However, the unary operation is directly performed only on the register. Arithmetic operation instructions can use bytes, words, and long words as described above. However, addition and subtraction with carry can use only byte size. Increment and decrement are used when the register is a counter.
Although ± 1 enables the use of bytes, words and longwords, ± 2 and ± 4 are used for address calculation, and therefore only longwords can be used. Although the logical operation instruction, shift, and rotate are not particularly limited, bytes, words, and long words can be used. This is 16M
This is because, as one application using the byte address space, when handling character data of a printer, it is considered that these instructions are frequently used for processing black and white inversion and italicization of character data.

[12] Example of Circuit Configuration of Register FIG. 27 shows a specific example of a logic circuit of a general-purpose register, an extension register, a program counter, and a temporary register. FIG. 1 representatively shows a 3-bit configuration. The register is composed of a flip-flop circuit FF,
Data can be input from the bus C and output can be made to the buses A and B. Data input / output is performed during a low level period of the system clock φ (symbol * in the drawing means low enable) based on a signal from the register selection unit REGSEL. The general-purpose registers RiH and RiL and the extension register Ei have independent control signals AH, BH, CH, AL, BL, CL, respectively.
AE, BE, and CE are provided, and independent input / output is possible. Since the program counter PC is 24 bits long, AE, AH and AL, BE, BH and BL,
CE, CH, and CL are common signals (AP described later).
C, BPC, CPC), and performs collective input / output. The temporary register TR depends on the method of use, but is the same as the general-purpose register and the extension register.

Although not particularly limited, each of the buses A, B, and C has a negative logic. The buses A and B are fixed at a high level (0 level) by a P-channel MOS transistor Qp while the system clock φ is at a high level. If no data is output from any of the blocks while the system clock φ is at the low level, the high level is maintained.

[13] Example of Operation of General-purpose Register and Extension Register FIG. B ＠ (1
234, ER0), an example operation timing chart of the general-purpose register and the extension register when the R1H # instruction is executed is shown.

In the first cycle (corresponding to the first step Sc1) and the fifth cycle (corresponding to the fifth step Sc5) synchronized with the system clock φ, the control signal APC becomes 1 level, and the contents of the program counter PC are set to the A bus. Is output to At the same time, the control signal CPC becomes 1 level,
The contents of the C bus are input to the program counter PC.
Although not particularly limited, the output of the program counter PC is a so-called master / slave, so that the content of the immediately preceding program counter PC is output to the A bus instead of the content of the C bus. In the second cycle (corresponding to the second step Sc2), the extension register E0 and the general-purpose register R0
Control signals AE0, AH0, and AL0 attain a 1 level, and the contents of the extension register E0 and the general-purpose register R0 are output to the A bus. In the sixth cycle (corresponding to the sixth step Sc6), the control signal AH1 of the general-purpose register R1 becomes 1 level, and the contents of the C bus are output to the general-purpose register R1H. The control signals AE1 and AL1 are at the 0 level, and the contents of the extension register E1 and the general-purpose register R1L are held.

FIG. 29 shows the (MO) shown in FIG.
V. An operation timing chart of an example of the general-purpose register at the time of executing the (L @ ER7 +, ER2) instruction is shown.

In the second cycle (corresponding to the second step Sd2) synchronized with the system clock φ, the control signals AE7, AH7 and AL7 of the extension register E7 and the general-purpose register R7 become 1 level, and the extension register E7 and the general-purpose register R7
Is output to the A bus. At the same time, the control signal CE
7, CH7 and CL7 become 1 level, and the contents of the C bus are input to the extension register E7 and the general-purpose register R7.
Similarly to the above, since the output of the general-purpose register is a so-called master / slave, the content of the immediately preceding program counter PC is output to the A bus instead of the content of the C bus. In the sixth cycle (corresponding to the sixth step Sd6), the control signal APC becomes 1 level, and the program counter PC
Is output to the A bus. At the same time, the control signal CPC becomes 1 level, and the contents of the C bus are
Input to C. In the seventh cycle (corresponding to the seventh step Sd7), the control signals CE2, CH2, CL2 of the extension register E2 and the general-purpose register R2 become 1 level, and the contents of the C bus are input to the extension register E2 and the general-purpose register R2.

[14] Configuration Example of Register Selector FIG. 30 is a block diagram showing an example for specifying a general-purpose register and an extension register in the register selector REGSEL. The register designating section includes decoders DEC1,
DEC2, three AND gates G1, four AND gates G2, six AND gates G3, and nine output control gates G4 such as clocked inverters. The decoder DEC1 controls the control signals S0 to S2
And the decoder DEC2 outputs the control signals D0 to D
Decode 2. The AND gate G1 receives predetermined output signals of the decoders DEC1 and DEC2 and predetermined control signals among the control signals DB, SB, DA, SA, CD and CS. The AND gate G2 receives two predetermined signals among the control signals D3, BY, and WO, and takes a logical product. The gate G3 includes an output of the AND gate G1, an output of the AND gate G2, and a control signal B.
A predetermined signal in Y is input to three inputs and its logical product is taken.
Output gate G4 outputs the output of corresponding AND gate G3 and the output of AND OR gate G1 in synchronization with clock signal φ.

The control signal DB instructs to output the register designated by the register designation section rd in the instruction format to the B bus, and the control signal CS designates the contents of the C bus by the register designation section rs in the instruction format. Indicates input to a register. The control signal DA instructs to output the register specified by the register specifying unit rd to the A bus. Control signal SB instructs to output the register specified by register specifying section rs to B bus. The control signal SA instructs to output the register specified by the register specifying unit rs to the A bus. The control signal CD is C
Register contents rd in instruction format
Instructs input to the register specified by. Control signals BY and WO indicate that the operation is to be performed in byte size and word size, respectively. The data corresponding to the register to be selected is a control signal S0 to S2 or a control signal D
0, D2 and control signals DB, SB, DA,
By providing predetermined signals to SA, CD, CS and control signals BY, WO, D3, the control signals AE, B
One or more of E, CE, AH, BH, CH, AL, BL, CL are activated.

FIG. 31 shows an example of the correspondence between the data in the register specifying section and the register specified by the data in the instruction format.

The register specifying section specifies the register number (0 to 7) with bits 0 to 2, and bit 3 indicates whether the upper or lower side (H / L) of the general-purpose register is a byte size.
For word size, specify whether it is a general-purpose register or an extension register. As described above, in the use of long word size data as an address register, bit 3 is ignored and does not substantially exist. For example, the control signal D
0 to D3 are B'0000, the control signal DA and the control signal BY
Are set to 1 level, the control signal AH of the general-purpose register is set to 1 level.

FIG. 32 shows the (MO) described with reference to FIG.
V. 5 shows an operation timing chart of the register specifying unit when the (LR2, ＠ -ER7) instruction is executed.

In the second step, the control signals AE7, AH7 and AL7 of the extension register E7 and the general purpose register R7 become 1 level, and the contents of the extension register E7 and the general purpose register R7 are output to the A bus. At the same time, control signals CE7 and CH
7, CL7 becomes 1 level, and the contents of the C bus are input to the extension register E7 and the general-purpose register R7. Similarly to the above, since the output of the general-purpose register is a so-called master / slave, the content of the immediately preceding extension register E7 and the content of the general-purpose register R7 are output to the A bus instead of the content of the C bus. In the sixth step, the control signal APC becomes 1 level,
The contents of the program counter PC are output to the A bus.
At the same time, the control signal CPC becomes 1 level, and the contents of the C bus are input to the program counter PC. In the seventh step, the control signal A for the extension register E2 and the general-purpose register R2
E, AH, and AL become 1 level, and the contents of the extension register E2 and the general-purpose register R2 are output to the C bus.

FIG. 33 shows an example of signal generation logic for generating the control signals S0 to S2 and D0 to D3 as register selection control signals.

As described above, since the register designation section rs is bits 7 to 4 of the instruction code, the contents of these bits 7 to 4 are directly used as the control signals S0 to S3. Further, since the register designating part rd is bits 3 to 0 or bits 12 to 8 of the instruction code, one of the contents of these bits 3 to 0 or bits 11 to 8 is selected and the control signals D0 to D0 are selected.
D3 is set. The signal for the selection is generated by decoding bits 15 to 12 of the instruction code. Bits 11 to
When 8 is used as the register designation section rd, since the operation code is bits 15 to 12, decoding the bits 15 to 12 makes it possible to determine whether the register designation section rd has bits 11 to 8. If the register designation section rd is not bits 11 to 8, bits 3 to 0 are used as control signals D0 to D3, including the case where the register designation section does not exist.

[15] Selector Circuit Section FIG. 34 shows the selector circuit section SEL shown in FIG.
A circuit focusing on the B bus is shown as an example.

When performing byte size addition between general purpose registers R0H and R1L, general purpose register R0H is connected to A bus H, B bus H, and C bus H (bits 15 to 8), and general purpose register R1L is connected to A bus L , B bus L and C bus L (bits 7 to 0) and are not directly connected to the same bit of the ALU. At this time, the selector circuit unit SEL outputs the contents of the general-purpose register R1L output to the B bus L to the B bus H. In the case of the byte size, the control signal BY is set to 1 level, and if the control signal S3 is 1 level, data is output to the B bus L from the general-purpose register specified by the register specifying unit rs. Is output to the B bus H through the selector circuit unit SEL. As a result, the same data is output to the B bus H and the B bus L, and regardless of the general-purpose register register specified by the register specifying unit rd, data of a register in a different block is input to the same bit of the ALU. Computable. Since the extension register is not used as a byte size register, it is not output to the B bus E.
Similarly, the control signal BY is set to 1 level and the control signal S3
Is 0 level, data has been output to the B bus H from the general-purpose register specified by the register specifying unit rs, and can be output to the B bus L.

In the case of the word size, the control signal WO
Is at one level, and if the control signal S3 is at one level, data has been output from the extension register designated by the register designation unit rs to the B bus E, and this is output to the selector circuit unit S
The signal is output to B bus H and B bus L through EL. As a result, the same data is output to the B bus E (bits 31 to 16), the B bus H, and the B bus L (bits 15 to 0), and either the extended register or the general-purpose register designated by the register designation section rd. Even when the data is input to the same bit of the ALU, the operation can be performed. Similarly, the control signal W
When O is at 1 level and the control signal S3 is at 0 level, data has been output to the B bus H and B bus L from the general-purpose register specified by the register specifying unit rs, and is output to the B bus E. be able to.

[16] Read Data Buffer FIG. 35 shows read data buffers RDBE, RDBH,
A specific circuit example of the RDBL is shown.

In the figure, read data buffer RDB
L and RDBH are composed of a first read buffer part RDB1 and a second read buffer part RDB2.
The read data buffer RDBE includes a first read buffer portion RDB3 and a second read buffer portion RDB4.
Consists of First read buffer portion RDB1,
RDB3 is a single-chip microcomputer 10
0 is connected via a gate circuit to the internal data buses D0 to D15 including 0, and the output is connected to the second data bus via the gate circuit.
Are connected to the inputs of the read buffer portions RDB2 and RDB4. Second read buffer portions RDB2, RDB4
Are connected to the A bus and the B bus via gates. Further, the output of the second read buffer portion RDB2 is also connected to an input of an instruction read data buffer (hereinafter also referred to as an instruction read buffer portion) RDBI via a gate. The output of the instruction read buffer portion RDBI is supplied to the control unit CONT. The first read buffer portions RDB1 and RDB3 and the second read buffer portion RD
B2, RDB4 and the instruction read buffer part RDBI are all 16 bits. "B bus E" shown in the figure
19 corresponds to “B (E)” in FIG. 19, “A bus E” corresponds to “A (E)” in FIG. 19, and similarly “B bus H” corresponds to “B (H)” in FIG. "A bus H" is shown in FIG.
9, “A (H)”, “B bus L” corresponds to “B (L)” in FIG. 19, and “A bus L” corresponds to “A (H)” in FIG.
(L) ".

When the control signal R4 shown in FIG. 35 is at the 0 level, the control signal R5 is at the 1 level, and the system clock φ * (* means inverted or low enable) is at the 1 level, the first read data The buffer portions RDB1 and RDB3 each take in data. At this time, if the control signal R4 is at one level, one read data buffer portion RDB3 does not take in data.
The first read data buffer portions RDB1 and RDB3 and the second read data buffer portions RDB2 and RDB4 operate as a master / slave, and are synchronized with one level of the system clock φ.
1, RDB3 to second read data buffer portion RD
Data is passed to B2 and RDB4. The data held by the second read data buffer portions RDB2 and RDB4 are supplied to the B bus based on one level of the control signal R3, and supplied to the A bus based on one level of the control signal R2. It is applied to instruction read data buffer portion RDBI based on one level of control signal R1.

The read data buffer shown in FIG. 35 includes a 32-bit second read data buffer portion RDB2 and RDB4 connected to the internal bus and a 32-bit first read data buffer portion connected to data buses D0 to D15. The first read data buffer portion RDB1 on the lower bit side always stores read data during reading, and the first read data buffer portion RDB3 on the upper bit side stores data. Specified by control signal R4. At this time, the lower 16 bits are always allowed to be input when reading, and the upper 16 bits are prohibited from being input when reading the lower word of the long word data (the upper word data is read first). . As a result, the 24-bit effective address designation section and long word data in the instruction code can be handled in the same manner, and the configuration of the read data buffer can be simplified, and the logical and physical scales can be reduced.

In FIG. 36, the above (MOV.L@ER7
FIG. 35 shows an operation timing chart of the read data buffer in FIG. 35 when the (+, ER2) instruction is executed.

In the first cycle, the fourth cycle and the sixth cycle, the control signal R5 goes to one level, and the data bus D15
To D0 are the first read buffer portions RDB1, RDB
Stored in DB3. However, in the sixth cycle, the control signal R4 is set to 1 level, and no data is stored in the first read data buffer portion RDB3. These contents are stored in the second read buffer portion RDB in the next cycle.
2, transferred to RDB4. In the second cycle, the control signal R
1 becomes the 1 level, and the second read buffer portion RDB
2 is transferred to the instruction read buffer part RDBI. The control unit CONT uses the contents from the seventh cycle to start decoding the next instruction.
In the seventh cycle, the control signal R3 becomes 1 level, and the 32-bit read data held in the second read buffer portions RDB2 and RDB4 is output to the B bus.

[17] Write Data Buffer FIG. 37 shows a specific circuit example of the write data buffer. Write data buffer WDBE receives data from 16-bit B bus E or 16-bit A bus E. Write data buffer WDBH receives data from 8-bit B bus H or 8-bit A bus H. Write data buffer WDBL receives data from 8-bit B bus L or 8-bit A bus L. The write data output buffers WDVOL and WDBOH are connected to the write data buffer WDBE or the write data buffers WDBL and WD
Upon receiving the output of the BOH, it is connected to the data buses D0 to D15.
Output to The data to be written is first output to the A bus or the B bus during the period when the system clock φ is at the low level, and the data is written according to the levels of the control signals W1, W2, and W3.
The data is stored in the write data buffers WDBL, WDBL, WDBE. The data stored in the write data buffer is transferred to the write data output buffers WDBOL and WDBOH according to the levels of the control signals W4, W5 and W6 while the system clock φ is at the low level.

FIG. 38 shows the (MO) described with reference to FIG.
V. An example operation timing chart of the write data buffer at the time of execution of the LER2, ＠ -ER7) instruction is shown. In the fourth cycle (corresponding to the fourth step Se4), the control signal W2 becomes 1 level, and the contents of the registers E2 and R2 output to the B bus are changed to the write data buffer WD.
BE, WDBH, and WDBL. At the same time, the control signal W6 goes to one level. Of these contents, the 16-bit contents corresponding to the data held in the register E2 are transferred from the write data buffer WDBE to the write data output buffers WDBOL and WDBOH. 1 level, and the internal data buses D0 to D15
Is output to In the sixth cycle (corresponding to the sixth step Se6), the control signals W4 and W7 become 1 level, and the contents of 16 bits corresponding to the register R2 held in the write data buffers WDBH and WDBL are written into the write data output buffers WDBOH and WDBOH. The data is transferred to WDVOL and output to internal data buses D0 to D15. The contents of the next instruction are transferred to the instruction read buffer.

[18] Address Buffer FIG. 39 representatively shows a 1-bit configuration as a specific example of a logic circuit of the address buffer. The address buffer includes flip-flop circuits MAB1 and MAB2. The flip-flop circuit MAB1 is connected to the bus A and the flip-flop circuit MAB2, and the flip-flop circuit MAB2 is connected to the flip-flop circuit MAB1 and the address bus. Flip-flop circuit MAB
Data input from the A bus 1 is performed while the system clock φ is at the low level when the control signal is at the 1 level. The contents of the flip-flop circuit MAB1 are transferred to the flip-flop circuit MAB2 while the system clock φ is at the high level and output to the address bus.

FIG. 40 shows the ΔMO described with reference to FIG.
V. FIG. 39 shows an operation timing chart of the address buffer of FIG. 39 when the B {(1234, ER0), R1H} instruction is executed. First cycle (first step Sc1
The control signal becomes 1 level in the third cycle (corresponding to the third step Sc3) and the fifth cycle (corresponding to the fifth step Sc5), and the contents of the A bus are stored in the flip-flop circuit MAB1. These contents are transferred to the flip-flop circuit MAB2 in the next step and output to the address bus.

FIG. 41 shows a modification of the address buffer. In the address buffer of FIG. 39, an adder, for example, an incrementer INC is added between the flip-flop circuits MAB1 and MAB2, and a constant value 2 can be added. In order to access 24-bit data, the access in 16-bit units is performed in two separate operations. Therefore, after the first access, 2 must be added to the address. In this addition, the incrementer INC is used. use.
Although the hardware increases as compared with the case of using the general-purpose ALU, the address once calculated when the general-purpose ALU is used is temporarily secured in, for example, a temporary register, and then the contents of the temporary register are read out. , ALU, and the trouble of transferring the addition result to the address buffer can be omitted.
The size of the ONT can be reduced. The format of these address buffers may be selected based on the overall configuration of the CPU. For example, compared to the scale of the execution unit EXE, the control unit CON
If it is considered that the size of T becomes too large and is not preferable in terms of the chip layout of the CPU or the like, the address buffer shown in FIG. 41 may be employed.

FIG. 42 shows the (MO) described with reference to FIG.
V. L ＠ ER7 +, ER2) FIG.
An operation timing chart of one address buffer is shown. The first cycle (corresponding to the first step Sd1) and the fifth cycle
In the cycle (corresponding to the fifth step Sd5), the control signal A1 becomes 1 level, and the contents of the A bus are stored in the flip-flop circuit MAB1. These contents are transferred to the flip-flop circuit MAB2 in the next step and output to the address bus. From the second half of the third cycle (corresponding to the third step Sd3), the control signal A2 becomes 1 level, and the content obtained by adding 2 to the flip-flop circuit MAB1 is transferred to the flip-flop circuit MAB2 in the fourth step and output to the address bus. . At this time, the calculation in the second step in FIG. 23 is set to +4, and the register is not operated in the fifth step.

[19] Address Map of Microcomputer FIG. 43 shows a microcomputer 100 according to this embodiment.
An example of the address map of FIG.

The built-in ROM 2 is arranged from address H'00000, and has built-in peripheral functions (timer 4, SCI 5, etc.)
And the built-in RAM 3 are arranged after the H'FF 800, and the space between them is an external space. The built-in peripheral functions and the built-in RAM 3 are located in the middle of the address space, for example, H'0F8
However, in this case, the external space is separated into two places. In addition, the program written in the internal ROM 2 and the program existing in the external space cannot be used continuously. This is contrary to the object of the present invention. Therefore, the built-in ROM 2, which is mainly used as the program area, and the built-in peripheral functions and the built-in RAM 3, which are mainly used as the data area, are arranged opposite to each other in the address space. By doing so, the microcomputer 100
Even if the data area or program area becomes large depending on the system to which the system is applied, it is possible to easily secure each of them in a continuous address space, manage data and programs on the system, and manage them. Access procedures are simplified. The built-in ROM 2 includes a start address for reset processing or an address (start vector) storing the start address.

At this time, as described above, since the 8-bit absolute address can use H'FFFF00 to H'FFFFFF, it can be used for the built-in peripheral function area. Also, a bit manipulation instruction can be used for such an area.

The 16-bit absolute address is H'00000
0 to H'007FFF and H'FF8000 to H'FF
Since FFFF can be used, built-in ROM, built-in RAM,
Can be used for built-in peripheral functions. Since these built-in areas are frequently used and can use instructions having a relatively short instruction length, code efficiency and effective time can be improved.

It is considered that a fixed address is rarely used for the external space. When using a fixed address in the external space, use H'FF8000
H'FFFFFF or H'FFFF00 to H'F
What is necessary is just to arrange in the area of FFFFF.

[20] Minimum Mode, Maximum Mode In the above description, the address space is 16 Mbytes. However, the function of the CPU 1 is a single chip computer 100 while having an address space of 16 Mbytes.
As a whole, 16
It is conceivable that an M-byte address space is not required and a large number of input / output port terminals is required. In such a case, it is not advisable to have 24 address terminals, and it is necessary to reduce the number of address terminals and increase the number of input / output port terminals. For example, if there are 20 address terminals, the actually usable address space is 1 Mbyte. In addition, there is also a sufficient application that the address space is 64 kbytes as in the related art while the CPU is the same. For example, if all the terminals of a single-chip microcomputer are used as input / output ports without using external space and the mounting area of an application system is to be reduced, if the total area of the built-in area is 64 kbytes or less, the address is There is no problem with the space of 64 kbytes as in the past.

In such an application, the reading of the vector or the stacking of the program counter only needs to be performed in units of 16 bits, that is, in units of 2 bytes. It is useless to access 4 bytes as described above. This leads to a decrease in memory use efficiency.

FIG. 44 shows an example of a data arrangement format on a memory in each of the minimum mode and the maximum mode. Although not particularly limited, a mode that operates in an address space of 64 kbytes is a minimum mode, and a mode that operates in an address space of 64 kbytes or more is a maximum mode as described above.

In the maximum mode, the vector is arranged in 4-byte units starting from an address that is a multiple of four. The first byte is a reserved area, and the remaining three bytes are used as a start address. The stack is arranged starting from an even address in 4-byte units both in exception processing and in subroutine calls.

In the minimum mode, vectors are arranged in 2-byte units starting from an even address. These are used as start addresses (the lower 16 bits; the upper 8 bits are regarded as 0). During exception processing, the stack stores the lower 16 bits of the condition code register CCR, the reserved area, and the program counter PC starting from an even address in 4-byte units. At the time of a subroutine call, the lower 16 bits of the PC are stored in 2-byte units starting from an even address.

FIG. 45 shows a flowchart of a reset sequence in the minimum mode. Third in FIG.
The steps are basically the same except that the step Sa3 and the fourth step Sa4 are omitted. In a sixth step Sa6 ', the contents of the vector are output to the lower 16 bits of the A bus.
Although not particularly limited, the upper bits are indefinite and are fixed to 0 in the address buffer AB. In this case, it is desirable that the extension register Ei is not affected when the effective address is calculated. Extension register Ei
As a data register.

FIG. 46 shows an example of a method of calculating the effective address in the minimum mode. In the case of the post-increment register indirect and the pre-decrement register indirect, the increment and decrement results are stored only in the general-purpose registers RiH and RiL after the transfer. Even if a carry or borrow occurs due to the increment or decrement, the extension register Ei is not affected. The other addressing modes are the same as the maximum mode because the registers used for the address calculation are not updated, and the upper bits may be fixed to 0 in the address buffer AB.

FIG. 47 shows a difference in operation of CPU 1 between the minimum mode and the maximum mode. As described above, in the maximum mode, the maximum number of addresses is 24 bits, and the vector, the stack for exception processing, and the stack for subroutine calls are all in units of 4 bytes including 24 bits for addresses. In the minimum mode, the maximum number of addresses is 16 bits, and the stack at the time of calling a vector or a subroutine is reduced to 2 bytes corresponding to the address 16 bits. Further, at the time of post-increment register indirect or pre-decrement register indirect, the extension address used for address calculation is not updated.

[21] Operation Mode of Single-Chip Microcomputer FIG.
Is shown. The operation mode shown here is the operation mode signals MODE1 to MODE3 shown in FIG.
Specified by

As described above, the address space is 16M, 1
M, 64 kbytes. In the ROM invalid expansion mode, considering the use of a large address space to handle a large amount of data, the 16 M and 1 M byte address spaces can be used, and the number of address outputs (the number of bits of the output address signal) is determined accordingly. Is done. Further, the bus width used immediately after the reset can be selected depending on the mode. For this reason, there are four types of ROM invalid extension modes. Note that the bus width can be reset by software by setting the register as described above. Although there is no particular limitation, the upper part of the data bus is used for the 8-bit bus.

In the ROM effective extension mode, the CPU is operated by the built-in ROM 2 immediately after the reset, and the number of addresses and the bus width can be set by software on the built-in ROM 2, so that the mode is set to one mode.

In the single chip mode, if the total area of the built-in area is 64 kbytes or less, one mode may be used.
As described above, since the operation of the CPU 1 is changed, there are two modes, for example, when it is desired to use the same software as the ROM invalid extension mode, and for future extension.

FIG. 49 shows an example of the terminal functions of the single-chip microcomputer 100 for each operation mode.

Although not particularly limited, the first port I
OP61 (port 1) has addresses 0 to 7, second port I
The OP62 (port 2) has addresses 8 to 15, the third port IOP 63 (port 3) has addresses 16 to 23, the fourth port IOP 64 (port 4) has addresses 8 to 15, and the fifth
Port IOP65 (port 5) has addresses 0-7,
The port IOP6 (port 6) is also used as a bus control signal, and the seventh port IOP67 (port 7) is also used as an address decode signal, and functions differ depending on the operation mode and register settings. For example, in ROM disabled extended mode,
All the predetermined addresses are output. However, in the ROM effective expansion mode, the address is not output immediately after reset, but if 1 is written to a predetermined register (PDDR) by software and output, the address is output.

The address decode signal occupies 8 address spaces.
It is divided, that is, divided in units of 2 Mbytes in a 16 Mbyte address space, and in units of 128 Kbytes in a 1 Mbyte address space, and each is assigned one by one. This is effective in the extension mode. If 1 is written to the register (PDDR) by software and output is performed, an address decode output is obtained. However, in the ROM invalid extension mode, the address decode signal corresponding to the first area, that is, the area including the vector area is output immediately after the reset. Thus, if the reset vector or the beginning of software is set in such an area, an address decode signal can be used immediately after reset, and an external address decode circuit can be omitted.

[22] Single Chip Microcomputer with DMA Further, the present inventor considers that the processing time is unnecessarily long when only the CPU 1 processes data, so that the dedicated data transfer is performed. We considered incorporating a device. That is, the so-called block transfer of data is
When the PU1 performs a transfer instruction, it requires an instruction read time in addition to data read / write.
For example, if a post-increment register indirect / long word transfer instruction is used, if an instruction with an instruction length of 2 bytes and an execution time of 7 states is used twice, the execution time will be 14 even if the transfer time is 8 states. State becomes inefficient.

FIG. 50 shows a second example examined by the present inventor.
Single-chip microcomputer 2 which is an embodiment of the present invention
FIG. The single-chip microcomputer 200 shown in the figure includes a direct memory access controller (DMAC) 201 in addition to the single-chip microcomputer 100 of FIG.
The CPU 1 and the DMAC 201 are connected to a bus controller (BS
C) is connected to the internal bus 69 via 202). D
The MAC 201 is a data transfer device that reads / writes data according to the designation of the CPU 1.
Or used by either DMAC 201.

FIG. 51 shows an address map of the single-chip microcomputer 200. As mentioned above,
The address map is divided into eight areas of 2 kbytes each, and the access method of each area is determined by four registers BSWCR, A included in the bus controller 202.
Specified by STCR, WSCER, MPXCR. First, the bus width designation register BSWCR designates whether to use an 8-bit bus or a 16-bit bus. For example, when a memory (not shown) connected to the external space of the area 0 has a 16-bit configuration, the BSWC
If the 0 bit is set to 1 and the input / output circuit (not shown) connected to the external space of the area 7 has an 8-bit configuration, the BSWCR7 bit may be cleared to 0.
Similarly, access state designation register ASTCR designates whether one access is performed in two states or three or more states. The wait state control permission designation register WSCER is
Specifies whether to prohibit or permit the wait request by the wait state controller (WSC) included in the command.
The address multiplex designation register MPXCR designates whether to not multiplex the address or to multiplex the address to connect the dynamic random access memory. However, while there is no particular limitation, when access is made in two states, wait and address multiplexing are prohibited. Therefore, there are ten attributes of the area specified by the register. CPU1 and DMAC201 for these attributes
May be determined individually to determine the access method. However, in that case, the processing becomes complicated, and the CPU 1 and the DMAC 201 must have the same logic and circuit in duplicate. The purpose of the present invention, which minimizes the increase in physical scale, cannot be sufficiently satisfied. Therefore, it is considered to be advantageous to make the bus controller 202 execute such control.

FIG. 52 is a block diagram showing an example of the bus controller 202. This bus controller 202
Is an address decoder ADRDEC, an AND circuit AND
LOG, control register CONTREG, wait control circuit WSCONT, and access control circuit ACSCONT
Composed of The address decoder ADRDEC receives an address signal output from the CPU 1 or the DMAC 201, generates a selection signal for a built-in functional block, and outputs an address signal. Control register CONTR
The EG includes the bus width designation register BSWCR, access state designation register ASTCR, wait state control permission designation register WSCER, and address multiplex designation register MPXCR.
The contents are set arbitrarily by the control of 1. The AND circuit ANDLOG includes the address decoder AD.
Address signals supplied through RDEC and registers BSWCR and AS included in control register CONTREG
Based on the values of TCR, WSCER, and MPXCR, control signals related to wait permission, bus width, access state, and address multiplex are generated and provided to the access control circuit ACSCONT. Wait control circuit WS
The CONT receives a wait signal issued from a built-in function block or the like and gives a wait request corresponding to a required number of states to the access control circuit ACSCONT. The access control circuit ACSCONT is connected to the AND circuit ANDLOG.
And a strobe signal AS, HRD, LRD, HWR, LWR, and CP for access control in response to a signal given from a weight control circuit WSCONT or the like.
A buffer control signal for U1 and DMAC 201 is generated.

When a data transfer activation factor occurs in the DMAC 201, the DMAC bus request signal is set to one level. In response to this bus request, the bus controller 202 permits the DMAC 201 to use the bus at a predetermined timing, and sets the DMAC bus permission signal to one level. At other times, the CPU 1 can use the bus. The bus start signal and the address input are multiplexed between the output of the CPU 1 and the output of the DMAC 201. That is, D
If the MAC bus permission signal is at one level, DMAC2
A bus start signal and an address input from the CPU 1 are received. Otherwise, a bus start signal and an address input from the CPU 1 are received. The internal operation of the bus controller 202 is as follows.
Both the access by the CPU 1 and the access by the DMAC 201 are the same. C during read / write
The buffer control signal to be provided to the PU1 / DMAC 201 is also multiplexed.

FIG. 53 shows an example of a read data buffer controlled by the bus controller 202. FIG.
The difference from this is a configuration for supplying data from the data buses D15 to D0 to the first data buffer portions RDB1 and RDB3. That is, the bus controller 202
Control signals RHH, RLH, RHL, RLL output from the data buses D15 to D8 and D7 to D0.
Is controlled in units of bytes from which data is stored in the read data buffer of the CPU 1.

FIG. 54 shows an example of a write data buffer controlled by the bus controller 202. FIG.
The difference from the write data output buffer WDBOL,
This is a configuration for outputting data from WDBOH to data buses D15 to D0. That is, the control signals WHH, W
The contents of the write data output buffers WDBOL and WDBOH are changed to the upper data bus D by LH, WHL and WLL.
Which of 15 to D8 and lower D7 to D0 is output is controlled in byte units.

FIG. 55 shows an example of an operation timing chart of the read data buffer shown in FIG.
This is a case where word data is read from an 8-bit bus / 3-state area. The bus controller 202 is started by the read signal RD and the word signal WORD output from the CPU 1. According to this example, the bus access is a two-byte read operation for each byte, and is performed in the order of even and odd addresses. At the time of the first read, data is stored in the upper part of the read data buffer from the data bus upper parts D15 to D8. At the time of the second read, data is stored in the lower part of the read data buffer from the upper data buses D15 to D8. During this time, the wait request becomes 1 level, and the CPU 1 enters the standby state. At the time of releasing the standby state, word data is stored in the read data buffer.
The CPU 1 uses the data, for example, in FIGS.
The operation as described in can be performed.

FIG. 56 shows an example of an operation timing chart of the write data buffer shown in FIG.
This is a case where word data is written to an 8-bit bus / 3-state area. The bus controller 202 is activated by the write signal WR and the word signal WORD output from the CPU 1. According to this example, the bus access is performed twice for each byte, and is performed in the order of even and odd addresses. The output data of the CPU 1 is stored in the write data buffer WDBH, WDBL or WDBE in the first state. At the time of the first write, data is output from the upper write data output buffer WDBOH to the data buses D15 to D0. At the time of the second write, data is output from the lower write data output buffer WDBOL to the data buses D15 to D0. During this time, the wait request is at 1 level, and the CPU 1 is in a standby state.

FIGS. 57 to 60 show control signals RHH, R
HL, RLH, RLL and control signals WHH, WHL, W
An example of the output specifications of LH and WLL is shown. In the figure, the size B is a byte and the size W is a word.
T1 is the first state, T2 is the second state, T3
Is a third state, and Tw is a wait state. Furthermore, in the figure,-means that there is no state corresponding to it. The specifications shown in the figure are DM
The same applies to the case where the AC 201 performs read / write.

[23] Modified Example of CPU FIG. 61 shows another embodiment of the CPU. The CPU shown in the figure extends the address buffer AB (ABL, ABH, ABE) to 32 bits in addition to the CPU 1 of FIG.
It has BR. The instruction designating part (op) and the register designating part (rs, rd, etc.) of the instruction code are stored in the read data buffer IDBR for the instruction code, and the effective address part (d, aa, xx) is stored in the EXEC inside as described above. Read data buffers RDBL, RDBH, RDB
E. As the address buffer AB is expanded to 32 bits, the displacement in the instruction code and the reserved area at the head of the absolute address (see FIGS. 14 and 16) are used, and the 32-bits of the general-purpose register Ri and the extension register Ei are used. The whole can be used as an address register. Since these can be easily realized from the above description, detailed description will be omitted.

Although not particularly limited, in FIG. 61, the program counters PCL, PCH, and PCE are 24 bits. It is unlikely that a program exceeding 16 Mbytes will be created by a single-chip microcomputer, so there is no problem. In particular, when the program counter is extended to 32 bits, the program counter PC in the EXEC is set to 32 bits, the vector area and the stack for subroutine calls are set to 4 bytes, and the stack for exception processing is set to the program counter P.
C may be 6 bytes including 4 bytes and the condition code register CCR may be 1 byte.

[24] Advantages of Embodiment (1) The 32-bit registers Ri and Ei are used collectively or partially as address registers, and are divided into two to form 16-bit data registers. By making one of the bit data registers usable as an 8-bit register, a wide address space of 16 Mbytes can be used while efficiently performing data processing. (2) By setting the instruction length to 2 bytes and setting the 24-bit absolute address displacement to 4 bytes including the reserved area, a 4 Gbyte address space can be used in the future. (3) By making the number of registers available as 8-bit registers and the number of registers available as 16-bit registers the same, instruction length can be reduced and program efficiency can be improved. (4) By configuring the register designating portion in the instruction code with 3 bits for designating the entire register and 1 bit for designating the register portion, the logical
Physical scale can be reduced. (5) By making the least significant bit of the effective address designating part in the instruction code the least significant bit of the word in the instruction code, the configurations of the execution part and the control part can be simplified, and the logical and physical scales can be reduced. . (6) By configuring the write data buffer with 32 bits connected to the internal bus and 16 bits connected to the data bus, the configuration of the write data buffer can be simplified, and the logical and physical scales can be reduced. . (7) When the read data buffer is connected to the internal bus
The instruction consists of 2 bits and 32 bits connected to the data bus. The lower 16 bits are always input when reading, and the upper is prohibited from inputting when reading the lower word of long word data. 24 in the code
The effective address designation part of bits and long word data can be handled in the same manner, so that the configuration of the read data buffer can be simplified and the logical and physical scales can be reduced. (8) If the address space has areas for different accesses and there is a data transfer device that performs read / write in addition to the CPU, read / write control is performed by a common bus controller. It controls the read data buffer and write data buffer of the CPU or other data transfer device, and furthermore, if necessary,
Alternatively, by configuring other data transfer devices to be in a standby state, the logical and physical scale of the entire single-chip microcomputer can be reduced. (9) The address space of 64 Kbytes or more can be used while minimizing the logical and physical scale of a single-chip microcomputer.

The invention made by the present inventor is not limited to the above embodiment, but can be variously modified without departing from the gist of the invention. For example, CPU1
There is no limitation on the block configuration, register configuration, specific example of a logic circuit, and the like. The number of bits of the register or the number of registers can be arbitrarily selected. Various modifications can be used for the addressing mode and the method of calculating the effective address.

In the above description, the case where the invention made by the present inventor is mainly applied to a single-chip microcomputer which is the background of the application has been described. However, the present invention is not limited to this. The present invention can be applied to an apparatus, and can be applied to a case where data scale is more important than data processing performance.

[0135]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a data holding means which is constructed by adding a 16-bit extension register to a 16-bit general-purpose register of an 8-bit CPU and comprising 32 bits in total is as follows.
The data can be held in whole or in two, or one of the two can be used by further dividing it into two parts, thereby improving the usability of the data holding means on software and hardware. Thus, the logical and physical scale of the data processing device can be reduced. In addition, in terms of holding address data using the whole or a part of the data holding means, it is easy to expand the address space that can be used linearly. In addition, compilation can be facilitated. Therefore, a program created in a high-level language can be executed efficiently.

In consideration of an operation instruction for n-bit data and an operation instruction for 2n-bit data, a portion used by dividing the whole into two equal parts, and one of the two equally divided parts are used by further dividing into two equal parts. Each data holding means is configured so as to have the following parts, and the total number of the parts used in the halving is further equal to the total number of the parts used in the halving. By providing a plurality of units of the data holding means, the instruction length can be shortened and the program efficiency can be improved.

By making the instruction unit twice as long as the data unit, it is possible to easily cope with future expansion of the address space. Further, by making the least significant bit of the effective address designating part in the instruction code the least significant bit of the word in the instruction code, the configuration of the execution means and the control means can be simplified, and the logical and physical scale can be reduced. Contribute.

By adopting an instruction format in which the part for designating the data holding means is fixed to a part of the instruction unit, the logical arrangement of the selecting circuit for the data holding means such as a register or the instruction decoding circuit is improved. Physical scale can be reduced. Further, in that case, the designated portion is constituted by an area for designating a required data holding means from a plurality of units, and an area for designating any part in one data holding means, and further comprising an instruction Based on the data size specified in the area, the area for specifying which part in the data holding means specifies which part is divided into two equal parts, and further specifies which part is divided into two equal parts. By determining whether or not to specify, the number of bits of the register specification part in the instruction format can be changed even when the data and the address data stored in the data holding means are several types of bytes, words, and long words. Can be minimized.

The write buffer means from the data holding means or the like has a first part of the number of bits corresponding to the number of bits of the data holding means and a number of bits equal to the number of bits of the equally divided area of the data holding means. A second part of the number of bits to be stored, and collectively store the contents of the data holding means in the first part based on a data write instruction, and store the data stored in the first part twice. By transferring the data to the second part and outputting the data, the configuration of the write buffer means can be simplified, and the logical and physical scale of the data processing device can be reduced.

The read buffer means for the data holding means and the like is provided with the number of bits corresponding to the number of bits of the data holding means as a whole, and is equally divided into an upper side and a lower side to read data. Based on the instruction, the lower side always stores read data at the time of reading, and the upper side specifies whether to store it or not,
The structure of the read buffer means can be simplified, and the logical and physical scale of the data processing device can be reduced.

When the address space has areas for accessing in different states and there is a data transfer device for reading and writing in addition to a data processing device such as a CPU, the read / write control is performed by a common bus control. The bus control device controls the read buffer means and the write buffer means included in the CPU or other data transfer device, and if necessary, sets the CPU or other data transfer device in a standby state. With this configuration, the logical and physical scale of the entire microcomputer is reduced in terms of the configuration for bus access.

[Brief description of the drawings]

FIG. 1 is a block diagram of a single-chip microcomputer according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a register configuration that has been studied by the inventor before;

FIG. 3 is a data configuration diagram in the register configuration of FIG. 2;

FIG. 4 is a data configuration diagram on a memory when the register configuration of FIG. 2 is adopted;

FIG. 5 is an explanatory diagram of a register configuration of a CPU which is an embodiment of the data processing device according to the present invention.

FIG. 6 is a data configuration diagram on a register of a CPU.

FIG. 7 is a diagram illustrating an example of a data configuration on a memory managed by a CPU;

FIG. 8 is an explanatory diagram of an example of an effective address calculation method by a CPU.

FIG. 9 is an explanatory diagram of another example of the effective address calculation method by the CPU.

FIG. 10 is an explanatory diagram of another example of the effective address calculation method by the CPU.

FIG. 11 is an explanatory diagram of an example of a command format of a CPU.

FIG. 12 is an explanatory diagram of another instruction format of the CPU.

FIG. 13 is an explanatory diagram of another instruction format of the CPU.

FIG. 14 is an explanatory diagram of another instruction format of the CPU.

FIG. 15 is an explanatory diagram of still another instruction format of the CPU.

FIG. 16 is an explanatory diagram of still another instruction format of the CPU.

FIG. 17 is an explanatory diagram of still another instruction format of the CPU.

FIG. 18 is an explanatory diagram of the instruction format of the remaining part of the CPU.

FIG. 19 is a block diagram of an embodiment of a CPU.

FIG. 20 is an explanatory diagram of an example of an internal operation flowchart of a CPU;

FIG. 21 is a flowchart of another internal operation of the CPU.

FIG. 22 is a flowchart of another internal operation of the CPU.

FIG. 23 is a flowchart of another internal operation of the CPU.

FIG. 24 is a flowchart of yet another internal operation of the CPU.

FIG. 25 is an explanatory diagram of an arithmetic operation instruction of the CPU.

FIG. 26 is an explanatory diagram showing a combination of a CPU instruction and an addressing mode.

FIG. 27 is a specific circuit configuration of a register of the CPU.

FIG. 28 is an example operation timing chart of a register of the CPU;

FIG. 29 is an explanatory diagram of another operation timing chart of the register of the CPU.

FIG. 30 is a circuit diagram of a register selection unit included in the CPU.

FIG. 31 is an explanatory diagram of a register designation mode;

FIG. 32 is an example operation timing chart of a register selection unit;

FIG. 33 is a diagram illustrating an example of a configuration of a register selection unit;

FIG. 34 is an example circuit configuration of a selector of an internal bus included in a CPU.

FIG. 35 shows an example circuit configuration of a read data buffer.

FIG. 36 is an operation timing chart of the read data buffer.

FIG. 37 shows an example circuit configuration of a write data buffer.

FIG. 38 is an operation timing chart of the read data buffer.

FIG. 39 is a circuit configuration example of an address buffer;

FIG. 40 is an operation timing chart of an address buffer.

FIG. 41 is a configuration explanatory diagram showing another example of the address buffer.

FIG. 42 is an operation timing chart of the address buffer of FIG. 41;

FIG. 43 is an example address map of a CPU;

FIG. 44 is an explanatory diagram of a data configuration on a memory for each mode.

FIG. 45 is a flowchart showing an example of the operation inside the CPU in the minimum mode.

FIG. 46 is an explanatory diagram of an example of an effective address calculation method in the minimum mode.

FIG. 47 is an explanatory diagram of the operation of the CPU in each mode.

FIG. 48 is an explanatory diagram of an operation mode of the single-chip microcomputer.

FIG. 49 is an explanatory diagram of terminal functions of a single-chip microcomputer.

FIG. 50 is a block diagram of a single-chip microcomputer according to a second embodiment of the present invention.

FIG. 51 is an address map of a CPU in the single-chip microcomputer of FIG. 50;

FIG. 52 is a block diagram of a bus controller included in the single-chip microcomputer of FIG. 50;

FIG. 53 is an explanatory diagram of an example of a read data buffer applied to the CPU of FIG. 50;

FIG. 54 is an explanatory diagram of an example of a write data buffer applied to the CPU of FIG. 50;

FIG. 55 is an example operation timing chart for a bus controller and a CPU;

FIG. 56 is another operation timing chart relating to the bus controller and the CPU.

FIG. 57 is a diagram illustrating an example of operation of a bus controller;

FIG. 58 is another operation explanatory view of the bus controller;

FIG. 59 is another explanatory diagram of the operation of the bus controller.

FIG. 60 is an explanatory diagram of another operation of the bus controller.

FIG. 61 is a block diagram showing another embodiment of a CPU.

[Explanation of symbols]

1 CPU 2 ROM 3 RAM 4 Timer 5 SCI 100 Single-chip microcomputer R0L, R0H to R7L, R7H General-purpose register E0 to E7 Extension register PC Program counter SEL Selector circuit section EXEC execution section CONT control section REJSEL Register selection circuit section ABL, ABH , ABE Address buffer ALUL, ALUH, ALUE Arithmetic logic unit RDBL, RDBH, RDBE Read data buffer RDB1, RDB3 First read data buffer part RDB2, RDB4 Second read data buffer part WDBL, WDBH, WDBE Write data buffer WDVOL , WDBOH write data output buffer 200 single chip microcomputer 201 DMAC 202 bus controller ACSCONT access control circuit BSWCR bus width specification register ASTCR access state specification register WSCER wait state control permission specification register MPXCR address multiplex specification register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 9/30-9/355 G06F 7/00 G06F 12/00-12/06

Claims (9)

(57) [Claims] 1. A data processing apparatus comprising: a plurality of general-purpose registers; an arithmetic and logic operation circuit connected to the plurality of general-purpose registers; and a selection circuit connected to the plurality of general-purpose registers. Each of the general-purpose registers has a first bit length, and each of the plurality of general-purpose registers has a first bit length of a second bit length.
And a second portion of a second bit length, wherein each of the second portions includes a third portion of a third bit length and a fourth portion of a third bit length, wherein the selection circuit comprises: Selecting one of the plurality of general-purpose registers in response to a first instruction instructing a long operation, and selecting one of the plurality of general-purpose registers in response to a second instruction instructing the second bit length operation One of the first part and the second part is selected, and in response to a third instruction instructing the operation of the third bit length, one of the plurality of general-purpose registers, all SANYO for selecting any part of the portion and the fourth portion, the arithmetic and logic circuit is connected to the first portion of the general purpose register, the second bit length
And a third unit connected to the third part of the general-purpose register, and having a third bit length.
And a third unit connected to the fourth part of the general-purpose register and having a third bit length.
The data processing apparatus according to claim der Rukoto those containing a third unit capable of performing operations. 2. The data processing apparatus according to claim 1, wherein said data processing apparatus is formed on one semiconductor substrate. 3. The first bit length is twice the second bit length, and the second bit length is two times the third bit length.
3. The data processing apparatus according to claim 2, wherein the number is doubled. 4. The data processing apparatus according to claim 3 , wherein said first bit length is 32 bits, said second bit length is 16 bits, and said third bit length is 8 bits. 5. An arithmetic and logic circuit connected to the plurality of general-purpose registers, connected to the plurality of general-purpose registers, and performing an arithmetic operation in response to an instruction decoding result, and a selection circuit connected to the plurality of general-purpose registers. The bit length of each of the plurality of general-purpose registers is 4N (N is an integer), and each of the plurality of general-purpose registers has a first portion having a bit length of 2N and a bit length of made from the second portion is 2N, each of said second portion, third portion and the bit length bit length is N is made from a fourth portion which is N, the instruction includes a operation code area, register and the number specified area, including Four and a register area specified area
One of the plurality of general-purpose registers is selected by the selection circuit in response to the information of the register number designation area and the operation of the bit length 4N by the operation code area; One of the first part and the second part is responsive to the calculation of the bit length 2N by the information of the register number designation area, the information of the register area designation area, and the operation code area. One of the plurality of general purpose registers, wherein one of the third part and the fourth part is the information of the register number designation area, the information of the register area designation area, and the operation code A data processing device which is selected in response to a calculation of a bit length N by a region. 6. The data processing apparatus according to claim 5 , wherein said data processing apparatus is formed on one semiconductor substrate. 7. The arithmetic logic circuit is connected to a first part of the general-purpose register and has a bit length of 2N.
And a second unit coupled to the third part of the general-purpose register and capable of performing an operation of bit length N, and a second unit coupled to the fourth part of the general-purpose register and The data processing apparatus according to claim 6 , further comprising a third unit capable of executing the calculation of (3). 8. The data processing apparatus according to claim 6 , wherein said N is eight. 9. A above general register number 8, the register number designated region consists of three bits, data processing according to claim 8, wherein said register area specified region, characterized in that it is made of 1 bit apparatus.