JPH0997211A - Bus controller and information processor provided with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a high-speed data transfer and the simultaneous processing of both endian by judging the endian by seeing the higher-order bits of an address, and switching the endian of data corresponding to a byte aligner. SOLUTION: In the address map of 32 bits, the area to be allocated to the external space is bisected for two pieces of endian data. When performing access to the external space, an address space discriminator 112 judges which area of endian is accessed, every time of access by seeing higher-order 3 bits A31-A29 of 32-bit addresses A31-A0. The information on this endian is transmitted to a byte aligner 111. Based on three kinds of information on external data bus width, endian and the length of transfer data, this byte aligner 111 selects any path required for transfer so as to rearrange the order of bytes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device capable of equally processing data represented in two types of byte arrangement order in an information processing device.

[0002]

2. Description of the Related Art So-called microcomputers (including microcomputers, microprocessors, and microcontrollers) use a byte arrangement order format (hereinafter referred to as little endian) in which the upper byte is placed at a higher address depending on the format of data to be processed and the upper byte. Byte arrangement order format (hereinafter called big endian) to be placed at a low address 2
It can be roughly divided into types. The endian has two meanings, that is, an endian in a bit unit (bit polarity) and an endian in a byte unit (byte polarity). In the present specification, simply saying “endian” means an endian in a byte unit.

Microcomputers implicitly assume to work in either little or big endian. Most 32-bit or more microcontrollers currently in use
It has some endian switching function so that the endian data different from the implicit endian can be processed. The following examples have been realized as main endian switching methods.

The method of writing to the mode bit in the program status word (PSW) The method of switching the value of the external control terminal (signal) The method of determining the address space Further, as the main byte rearrangement method, the following example Has been realized.

A method of exchanging with software by a byte rearrangement instruction A method of inverting the lower bits of an address A method of rearranging with a byte aligner A configuration of a system including a conventional bus controller will be described. 9, 10, and 11 are system configuration diagrams including the bus control devices of the first, second, and third conventional examples, respectively. The conventional example is not necessarily a 32-bit microcomputer, but in the following
The description will be given for all 32-bit microcomputers. In the figure,
32-bit microcomputers 901, 1001, 1101 control the entire system. Bus control devices 902, 1002
1102 is an interface between the microcomputer and the external bus. The CPU cores 903, 1003, 1103 perform general-purpose program processing as the core of the microcomputers 901, 1001, 1101. It is assumed that these can process only little endian data. Built-in instruction memory 904
1004 and 1104 are CPU cores 903, 1003 and 1
The instruction to be processed by 103 is stored. Built-in data RAM 90
5,1005,1105 are CPU cores 903,100
Stores work data that can be accessed at high speed from 3, 1103. DMA controller (DMAC) 906,100
6, 1106 are CPU cores 903, 1003, 1103
And control DMA processing independently. 32-bit external address buses 907, 1007, 1107 transfer address data. 32-bit external data bus 908, 100
8, 1108 transfers 1 to 4 bytes of data. Big endian input / output device 909,100
Reference numerals 9 and 1109 denote peripheral devices whose interfaces are in big endian format. These are assigned addresses in the external memory space, and CPU cores 903, 100
3, 1103 can be accessed in the same manner as the external memory.
In particular, the big endian input / output device 909 is placed in the big endian area of the external memory space. The external memories 910, 1010, 1110 are typically DRAM or the like. Bite aligners 911, 1011 and 1111 are
Swap the byte order of the data. Bite aligner 91
1, 1011 have a data transfer path corresponding to only little endian. The byte aligner 1111 has a data transfer path corresponding to both endians, and can convert the endian of data to the other endian. The address space determiner 912 determines the address space by observing a part of bits of the address, and further determines which endian area to access by observing another bit. The address lower bit invertors 913 and 1013 invert the lower two bits of the address when accessing the big endian space.

When the CPU cores 903, 1003, 1103 access an external big endian input / output device or an external memory, the operation of the system including the three bus control devices of the conventional example will be described. (1) First conventional example-The address space determiner 912 determines the endian of the data to be accessed by looking at the address. When it is determined to be a big endian area, the address lower bit inverting unit 913 inverts the lower 2 bits of the external address output. Otherwise, do not flip. The CPU core 903 or the DMAC 906 inputs / outputs data to / from the external space in byte units. (2) Second conventional example-After reset, the endian mode is written by software to the mode bit in the PSW in the CPU core 1003. In the big endian mode, the address lower bit inverter 1013 inverts the lower 2 bits of the external address output. Otherwise, do not flip. The CPU core 1003 or the DMAC 1006 inputs / outputs data to / from the external space in byte units. (3) Third conventional example-After reset, the endian mode is written by software to the mode bit in the PSW in the CPU core 1103. -The byte aligner 1111 selects the transfer path corresponding to the endian specified in the endian mode,
Input and output data while converting endian.

Big endian input / output device 909, 1
Specific examples of 009 and 1109 include a CD-ROM drive and the like. CD-ROM drive, media CD-R
The OM format is specified as big endian. Conversely, as a little endian input / output device,
A personal computer that uses Intel's X86 microprocessor and peripheral devices that incorporate it can be mentioned. In this way, since the endian is different for each peripheral device, devices of different endian may coexist in one system. Regardless of the endian, it is required to process both endian data in the system by one microcomputer at the same time.

[0008]

In the first and second conventional examples, when transferring big endian data, any one byte, two bytes, or four bytes of data must be transferred in byte units, so the transfer speed is slow. . Also, the output timing of the lower 2 bits of the inverted address is delayed.
In the second and third conventional examples, since two endians are not compatible in one system, data of both endians cannot be processed at the same time, and the endian of the data cannot be converted. In reality, many microcomputers have a specification that the endian mode can be changed only immediately after reset.

In view of the above points, the present invention provides a new bus control device in which two endians are compatible in one system and the transfer speed is not reduced even when processing data of different endians. With the goal.

[0010]

In order to solve the above problems, the bus control device of the present invention discriminates whether the data area to be accessed is in the little endian area or the big endian area by looking at the upper bits of the address. If the address space determining means and the address space determining means at the time of data transfer determine to access the little endian area of the external data address space, they pass through a path storing the byte order of the little endian, while the external data address space When it is determined that the big endian area is accessed, a byte rearrangement means for rearranging the byte order between the internal little endian format and the external big endian format and passing through a path for mutual conversion is provided.

[0011]

With the above configuration, the bus control device of the present invention internally processes data in little endian format,
The external data address space is divided into a little endian area that stores data in little endian format and a big endian area that stores data in big endian format, and little endian data and external I / O devices are stored in the little endian area in the system. Pre-allocated, big-endian data and external I / O devices are pre-allocated to the big-endian area in the system.

When accessing data to the outside, the address space determining means identifies which data space the data space is based on the upper bits of the data address. Further, the endian of the data is identified based on the other 1 bit in the data address.

When accessing little endian data, a byte aligner performs an ordinary alignment process according to the data length, and then inputs / outputs. When loading big endian data, the byte aligner performs normal alignment processing according to the data length, rearranges the byte order of the data to little endian order, converts it to little endian data, and inputs it. When storing internal little endian data in the big endian area, the byte aligner performs normal alignment processing according to the data length, rearranges the byte order of the data to big endian order, and converts it to big endian data. Output.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, the bytes displayed on the right are lower than the bytes on the left. The bit-wise arrangement is assumed to be little endian. The data in the memory shall be placed at the address aligned to the word length boundary. The system including the bus controller of this embodiment shall support an external 32 or 16 or 8 bit bus.

First, the memory addressing and the bus interface related to the byte polarity will be described. Four
Byte data L is expressed as a sequence of 1 byte a, b, c, d as follows. L = (abcd) where a is the most significant byte and d is the least significant byte. When the external data bus width is 8 bits, L is stored in the memory as shown in FIG. 8A in little endian.
In big endian, L is stored in the memory as shown in FIG. When the external data bus width is 16 bits and 32 bits, L is stored in the memory in little endian as shown in (c) and (d) of FIG. 8, respectively. In the figure, it is assumed that the left byte is connected to the upper byte of the external data bus. In big endian, reflecting the difference in the physical connection method between the external memory and the system bus,
There are several possible formats for the memory model that stores L. Here, when the external data bus width is 16 bits and 32 bits, it is assumed that L is physically stored in the memory as shown in (e) and (f) of FIG. That is, the high-order (low-address) byte of a big-endian I / O device shall be connected to correspond to the high-order (high-address in little-endian) byte of a 16- or 32-bit system bus. .

The system configuration of this embodiment will be described. FIG.
FIG. 3 shows a system configuration diagram including a bus control device of the embodiment. In the figure, 101 to 112 have the same roles as the corresponding constituent elements of the conventional example. The CPU core 103 is designed to be able to process only little endian data.

In the system of the present embodiment, as shown in FIG. 7, the area allocated to the external space in the 32-bit address map is divided into two areas for two endian data. 7A and 7B are examples of address maps in an operation mode in which the 32-bit microcomputer 101 has an instruction memory (memory expansion mode) and an operation mode in which the 32-bit microcomputer 101 does not have an instruction memory (processor mode). When accessing the external space, the address space determiner 112 looks at the upper 3 bits A31 to A29 of the 32-bit address A31 to A0 and determines which endian area is being accessed each time. Specifically, it determines whether to access the internal or external memory by looking at A31 and A30. When accessing the external memory space, further looking at A29, access either the big or little endian area. To determine. However, as shown in the figure, the internal memory space, instruction memory space, and external I / O space store only little endian data. Therefore, when accessing the address (A31, A30, .., A0), the logical BER indicating that the address is in the big endian area
Is BER = EXT ・ (A31 ・ A30 ・ A29) + PROC ・ (A31 ・ A30 ・ A29 + A31
・ A30 ・ A29). Here, EXT and PROC are logics indicating the memory expansion mode and the processor mode, respectively, and the upper line of the variable represents the logic inversion. If the BER is true, it is judged as the big endian area, and if it is false, it is judged as the little endian area.

Information about the endian is transmitted to the byte aligner 111. Bite aligner 111
The byte order is rearranged by selecting the path required for the transfer based on the external data bus width, endian, and the length of transfer data. 2 to 4 show the relationship between these three pieces of information and the byte rearrangement path of the selected byte aligner 111. In the figure, BCBUS is the CPU
EXBUS is an internal bus that connects to the core 103, and EXBUS is an internal bus that connects to the external data bus 108. The width of one path indicated by a solid line with an arrow is 1 byte, that is, 8 bits. When the external data bus width is 8, 16 and 32 bits, it is shown in FIGS. 2, 3 and 4, respectively. When the external data is little and big endian for each, it is shown in (a) and (b), respectively. Furthermore, for each of them, the path required when the data length to be transferred is 4, 2, or 1 byte is shown. In FIGS. 2 to 4, the number of cycles required for transfer and the number of cycles and the path to be taken are shown by the numbers enclosed in circles. In the present embodiment, if the data width of the transfer path is narrower than the transferred data width, the bytes at the lower addresses are always transferred first. The numbers given here correspond to the case where the data to be transferred is aligned on a 4-byte boundary address. Circled unnumbered paths are used when they are not aligned on a 4-byte boundary.

FIG. 5 shows the aligner paths shown in FIGS. 2 to 4 for each external bus width. 5 (a), (b),
(C) is a compilation of FIGS. 2, 3, and 4, respectively. FIG. 5 (d) summarizes all of them, and finally shows all the paths necessary for the byte aligner 111 of this embodiment. Table 1 shows the number of transfer paths of the byte aligner 111 required in this embodiment for each external data bus size and each supported endian.

[0020]

[Table 1]

Another byte aligner is provided inside the CPU core 103. This byte aligner serves to match the internal 32-bit data path when accessing 8-bit and 16-bit data. The operation of this byte aligner is independent of endian and external data bus size. If you load the data,
If it is 8 bits to 16 bits, the data is placed in a right-justified position with a width of 32 bits. When storing data,
If the data length is 8 to 16 bits, the right-justified data in the internal register is
Place it at an appropriate position within the bit width. The path configuration for the byte rearrangement operation of the byte aligner inside the CPU core 103 is shown in FIG. When the data length is 4, 2 or 1 byte, the path of the byte aligner is shown in (a), (b) and (c) of (Fig. 6), respectively. (FIG. 6) (d) summarizes them and shows all paths necessary for the byte aligner inside the CPU core 103. The byte aligner inside the CPU core 103 requires eight 8-bit paths.

The operation of this embodiment will be described below. In this embodiment, little or big endian data can be transferred between the register inside the CPU core 103 and the outside. Also, external big-endian data can be
The big endian data can be converted into the little endian data by transferring to the register inside the core 103 and then to the outside little endian area. The reverse is also true. Similar data processing is possible even in the case of DMA. Hereinafter, as shown in (Table 2), the data transfer is divided into cases, and the operation flow is described for each case.

[0023]

[Table 2]

(1) Loading little endian data External little endian data is fetched from the little endian area and stored in a register inside the CPU core 103 via the byte aligner 111 without rearranging the byte order. (2) Store to little endian area Read the data in the register inside CPU core 103,
The data is stored in the external little endian area via the byte aligner 111 without rearranging the byte order. (3) Loading big endian data Fetch external big endian data from the big endian area. The byte aligner 111 performs byte rearrangement operation according to the external data bus width and the data length to convert big endian data into little endian data. Converted data to CPU
It is stored in a register inside the core 103. (4) Store to big endian area Read the data in the register inside the CPU core 103.
By performing the byte rearrangement operation by the byte aligner 111, the little endian data is converted into the big endian data, contrary to (3). Store the converted data in the specified external big-endian area. (5) DMA transfer from little endian area to little endian area Little endian data is loaded as in (1) above and temporarily stored in a register inside DMAC 106. Subsequently, the data in the register inside the DMAC 106 is stored as in the above (2). The data format inside the DMAC 106 is always little endian. (6) DMA transfer from big-endian area to little-endian area Big-endian data is loaded as described in (3) above and temporarily stored in a register inside DMAC 106. Subsequently, the data in the register inside the DMAC 106 is stored as in the above (2). (7) DMA transfer from little endian area to big endian area Little endian data is loaded as described in (1) above and is temporarily stored in a register inside DMAC 106. Then, the data in the register inside the DMAC 106 is stored as in the above (4). (8) DMA transfer from big-endian area to big-endian area Load big-endian data as in (3) above and temporarily store it in a register inside DMAC 106. Then, the data in the register inside the DMAC 106 is stored as in the above (4).

According to this embodiment, the endian of the data area to be accessed can be determined at high speed by decoding the address of up to 3 bits, and the byte order can be rearranged at high speed by switching the byte unit path. Becomes Therefore, the endian switching function for each data transfer can be added to the microcomputer without extending the data transfer cycle of the pipeline-controlled microcomputer.

In this embodiment, the same system configuration can be applied by changing the aligner path even when the little endian data is handled by the CPU core corresponding to only big endian. Even if the big and the little are interchanged in the description of the embodiment, the present invention is equally effective. Even if the big-endian external bus configuration is different, the same system configuration can be applied by changing the aligner path.

[0027]

According to the prior art, since the endian is exchanged by inverting the lower 2 bits of the address output and transferring the data in byte units, the data transfer performance is deteriorated. Also, because the endian is switched by the mode bit in the status flag or the value of the pin, only the data of either endian can be processed. According to the bus control device of the present invention, the endian is determined by looking at the upper bits of the address, and the endian of the data is switched by the byte aligner, whereby high-speed data transfer independent of endian and simultaneous processing of both endian data are performed. Will be possible.

[Brief description of drawings]

FIG. 1 is a system configuration diagram including a bus control device according to an embodiment.

FIG. 2 is a diagram showing a path configuration of a byte aligner 111 in a bus control device.

FIG. 3 is a diagram showing a path configuration of a byte aligner 111 in the bus control device.

FIG. 4 is a diagram showing a path configuration of a byte aligner 111 in the bus control device.

FIG. 5 is a diagram showing a summary of path configurations of the byte aligner 111 for each external bus width.

FIG. 6 is a diagram showing a path configuration of a byte aligner in the CPU core.

FIG. 7 is a diagram showing area division of an address space for identifying endian.

FIG. 8 is a conceptual diagram of an external bus and an external memory model.

FIG. 9 is a system configuration diagram including a bus control device of a first conventional example.

FIG. 10 is a system configuration diagram including a bus control device of a second conventional example.

FIG. 11 is a system configuration diagram including a bus control device of a third conventional example.

[Explanation of symbols]

 101 32-bit microcomputer 102 Bus controller 103 CPU core 104 Built-in instruction memory 105 Built-in data RAM 106 DMA controller (DMAC) 107 External address bus 108 External data bus 109 Big endian I / O device 110 External memory 111 Byte aligner 112 Address space determiner

Claims (8)

[Claims] 1. A first byte arrangement order area for storing data in a first byte arrangement order format in a data address space and a second byte arrangement order area.
And a second byte arrangement order area for storing data in the byte arrangement order format, and identifies whether the data area to be accessed is in the first or second byte arrangement order area based on a specific bit of an address. Address space determining means for
The first in the address space determination means at the time of data transfer
When it is determined to access the byte arrangement order area, the received data of the first byte arrangement order is input / output in the same byte arrangement order, and the address space determination means determines to access the second byte arrangement order area. In this case, the bus control device is provided with a byte rearrangement means for rearranging the byte order between the first byte arrangement order format and the second byte arrangement order format, converting the byte order, and inputting / outputting. 2. An address space determining means for identifying whether the data area to be accessed based on a specific 1 bit of an address is in the first or second byte arrangement order area. Bus control device as described. 3. A first byte arrangement order area for storing data in a first byte arrangement order format in a data address space and a second byte arrangement order area.
It is divided into a second byte arrangement order area for storing data in the byte arrangement order format of, and the data area to be accessed is determined based on a specific bit of the address to determine which data address space is to be accessed. When it is determined that the data area is in a specific data address space, an address space determining means for identifying whether the data area to be accessed is in the first or second byte arrangement order area based on another specific bit of the address, and data. At the time of transfer, when the address space determination means determines to access the first byte arrangement order area of a specific data address space, the first byte arrangement order is input / output in the same byte arrangement order, and the address space determination means If it is determined to access the second byte-aligned area of the specific data address space, the first byte Bus control device according to claim converted by rearranging byte ordering comprise a byte rearrangement means for input and output to and from the micro-forward type and the second byte ordering format. 4. A data address space to be accessed is determined based on a specific bit of the address, and when it is determined that the data region to be accessed is in a specific data address space, another one of the addresses is determined. 4. The bus control device according to claim 3, further comprising address space determining means for identifying whether the data area to be accessed is in the first or second byte arrangement order area based on the bit. 5. A data processing means for processing internal data in a first byte arrangement order format, a first byte arrangement order area for storing data in an external data address space in the first byte arrangement order format, and a second. And a second byte arrangement order area for storing data in the byte arrangement order format, and the first and second data areas are accessed based on a specific bit of the address.
An address space determination means for identifying which byte arrangement order area is located, and a first received when the address space determination means determines to access the first byte arrangement order area of the external data address space during data transfer. When the data in the byte arrangement order is input and output in the same byte arrangement order, and the address space determination means determines to access the second byte arrangement order area of the external data address space, the first byte arrangement format and the first byte arrangement order An information processing apparatus, comprising: a byte rearranging unit for rearranging and converting a byte order between two byte arrangement order formats and inputting / outputting. 6. The address space determining means for identifying whether the data area to be accessed is in the first or second byte arrangement order area based on one bit of the address. Information processing equipment. 7. A data processing means for processing internal data in a first byte arrangement order format, a first byte arrangement order area for storing data in an external data address space in a first byte arrangement order format, and a second. The data is divided into a second byte arrangement order area for storing data in the byte arrangement order format, and whether the data area to be accessed is in the external data address space is determined based on a specific bit of the address, and the data to be accessed is determined. Address space determining means for identifying whether the data area to be accessed is in the first or second byte arrangement order area based on another specific bit of the address when it is determined that the area is in the external data address space, When the address space determination means determines to access the first byte arrangement order area of the external data address space during data transfer If the same byte arrangement order is input and output, and the address space determination means determines to access the second byte arrangement order area of the external data address space, the internal first byte arrangement order format and the external An information processing apparatus, comprising: a byte rearrangement unit for rearranging and converting a byte order to and from a second byte ordering format and inputting and outputting the byte order. 8. A method of determining whether a data area to be accessed is in an external data address space based on a specific bit of an address, and determining that the data area to be accessed is in an external data address space 8. The information processing apparatus according to claim 7, further comprising address space determining means for identifying whether the data area to be accessed based on 1 bit is in the first or second byte arrangement order area.