JP2010250905A - Semiconductor integrated circuit and method for testing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit and its test method, which change the number and combinations of memories which are simultaneously tested even after manufacture. <P>SOLUTION: Access to the memories MEM1-MEMn is controlled by controlling a test sequence of the memories MEM1-MEMn by a test sequence control part 1 according to the test sequence setting from the outside, and by enabling/disabling chip enable signals CE1-CEn by a memory access control part 2 according to instructions from the test sequence control part 1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and a test method thereof.

  In recent years, with the increase in scale and functionality of semiconductor integrated circuits, many memories may be mounted on one semiconductor integrated circuit.

  When testing a semiconductor integrated circuit in which such a plurality of memories are mounted, it is common to separately perform a logic test and a memory test. This is because there are various failure modes in the memory, and it is possible to test more efficiently by creating a test pattern dedicated to the memory.

  When such a memory test is performed, if the tests are performed one by one, the test time becomes longer. Therefore, conventionally, a semiconductor integrated circuit has been proposed in which a plurality of memories can be performed in parallel (see, for example, Patent Document 1).

  In the proposed semiconductor integrated circuit, a control circuit for controlling access to the memory is provided so that a plurality of memories can be tested in parallel. By testing a plurality of memories in parallel, the memory test time can be shortened.

  However, in the case of a clock-synchronized memory, if a plurality of memories are operated at the same time, a current flows to the plurality of memories at the same time at the clock edge, and the power supply voltage is lowered due to so-called IR drop in the power supply wiring of the semiconductor integrated circuit. . When the power supply voltage drop due to the IR drop is large, it is necessary to lower the clock frequency in order to avoid malfunction of the memory under test. As a result, there arises a problem that it becomes difficult to test the memory at the actual operation speed.

  In that case, if the number of memories to be simultaneously tested is reduced, the problem caused by IR drop can be avoided. However, when a control circuit for operating a plurality of memories in parallel is incorporated as in the above proposed semiconductor integrated circuit, even if it is found that a problem due to IR drop occurs after the manufacture of the semiconductor integrated circuit, At the same time, there was a problem that the number of memories to be tested could not be reduced.

JP 2001-273800 A (Page 4, FIG. 2)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit and a test method thereof that can change the number and combination of memories to be tested at the same time even after manufacture.

  According to one aspect of the present invention, a plurality of memories, a test sequence control unit that controls a test sequence of the plurality of memories according to an external setting, and a plurality of memories that are transmitted to the plurality of memories according to an instruction from the test sequence control unit There is provided a semiconductor integrated circuit comprising memory access control means for controlling access.

  According to another aspect of the present invention, there is provided a test method for a semiconductor integrated circuit having test sequence control means for controlling a test sequence of a plurality of built-in memories, wherein each of the plurality of memories is individually tested. Generating unit test data to be performed; executing a simulation of the semiconductor integrated circuit using the unit test data; and from the result of the simulation, the semiconductor integrated circuit at the time of executing a test using each of the unit test data Analyzing the current consumption, generating a test sequence of the plurality of memories based on the current consumption analysis result, and setting the test sequence in the test sequence control means. A featured test method is provided.

  According to the present invention, it is possible to change the number and combination of memories to be tested at the same time in consideration of the influence of IR drop even after manufacturing.

1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention. The flowchart which shows the example of the test sequence production | generation flow of the memory contained in the semiconductor integrated circuit of the Example of this invention. The figure which shows the production | generation example of a test sequence. 1 is a diagram showing an example of a configuration of a memory included in a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 5 is a diagram showing an example of a test sequence for a memory having the configuration shown in FIG. 4. FIG. 6 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 6 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. FIG. 10 is a waveform diagram showing an example of the operation of the clock phase adjustment unit of the semiconductor integrated circuit according to the third embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention.

  The semiconductor integrated circuit according to the present embodiment includes n memories MEM1 to MEMn, a test sequence control unit 1 that controls a test sequence of the memories MEM1 to MEMn according to an external test sequence setting, and an instruction from the test sequence control unit 1 And a memory access control unit 2 that controls access to the memories MEM1 to MEMn.

  The memories MEM1 to MEMn are RAM, ROM, etc., and each have a chip enable terminal CE. When the signal input to the chip enable terminal CE is valid, the memories MEM1 to MEMn operate. At the time of testing, an address is designated by test data for each memory. If it is a RAM, a test pattern writing and reading operation is tested. If it is a ROM, a reading operation is tested.

  The test sequence control unit 1 includes, for example, firmware that is rewritten according to an external test sequence setting, and controls the order in which the memories MEM1 to MEMn are tested and the number of memories to be tested simultaneously.

  The memory access control unit 2 switches validity / invalidity of the chip enable signals CE1 to CEn input to the memories MEM1 to MEMn at the timing specified by the test sequence control unit 1.

  When testing the memories MEM1 to MEMn, the test time can be shortened if many memories can be tested at the same time. However, as more memories are tested simultaneously, the current consumption of the semiconductor integrated circuit increases, and if the value exceeds a certain value, a malfunction due to IR drop occurs.

  Therefore, in this embodiment, an upper limit value of current consumption that can permit IR drop is determined, and a test sequence of the memory test is programmed so that as many memories as possible can be simultaneously tested within the range of the upper limit value.

  Since the test sequence program can be written to the test sequence control unit 1 using an external terminal, the test sequence can be freely recombined even after the semiconductor integrated circuit is manufactured.

  FIG. 2 is a flowchart showing an example of a flow for generating the above-described test sequence.

  In this flow, first, unit test data for testing each of the memories MEM1 to MEMn alone is generated (step S01).

  Next, a simulation of the semiconductor integrated circuit is executed using the unit test data (step S02).

  Subsequently, from the simulation results, the current consumption of the semiconductor integrated circuit at the time of the test execution by each unit test data is analyzed, and the current consumption of each memory is calculated (step S03).

  Next, based on the analysis result of the current consumption, a test sequence for controlling the combination of the memories to be tested and the test order is generated so that as many memories as possible can be simultaneously tested within the upper limit range ( Step S04).

  Finally, the test sequence is set in the test sequence control unit 1 as a firmware program, for example (step S05).

  FIG. 3 shows an example of a test sequence generated by the above flow.

  For example, when a unit test pattern for testing each memory is created when eight memories MEM1 to MEM8 having the same memory capacity are built in the semiconductor integrated circuit, the test time of each memory becomes the same. Therefore, if all of MEM1 to MEM8 can be tested at the same time, the test time of the memory becomes the shortest.

  Therefore, the current consumption during the test of each memory is calculated, and it is verified whether or not eight simultaneous tests are possible. As a result, as shown in FIG. 3A, when five or more memories are tested at the same time, it is found that the total current consumption exceeds the upper limit value that allows IR drop.

  From this, it is determined that eight simultaneous tests are not possible, and in this case, a test sequence is assembled so that four memories are tested simultaneously. That is, first, a test sequence is generated in which MEM1 to MEM4 are tested simultaneously, and then MEM5 to MEM8 are tested simultaneously.

  FIG. 4 is an example of another memory combination. In this case, it is assumed that the memory MEM1 and the memory MEM2 have the same size address space, and the memory MEM3 has an address space twice that of the memory MEM1. Therefore, in this case, when a single memory test is performed, the test time of the memory MEM3 takes twice as long as the test time of the memory MEM1. On the other hand, the test time of the memory MEM2 is the same as the test time of the memory MEM1.

  Also in this case, first, it is verified whether or not three memories can be simultaneously tested. As a result, as shown in FIG. 5A, it is assumed that the total of the current consumption does not exceed the upper limit until two simultaneously, but when the three are tested simultaneously, it is found that the upper limit is exceeded.

  Therefore, in this case, a test sequence is assembled so that two pieces are tested simultaneously. In that case, considering the difference in test time, the combination of memories to be tested at the same time is determined.

  That is, as shown in FIG. 5B, first, the memory MEM3 and the memory MEM1 are tested at the same time, and after the test of the memory MEM1, the test of the memory MEM2 is performed simultaneously while continuing the test of the memory MEM3. Is generated.

  According to the present embodiment, since the test sequence can be set from the outside, the test sequence of the memory test can be freely recombined even after the semiconductor integrated circuit is manufactured.

  In addition, the number of memories to be tested simultaneously is determined so that the total current consumption of the memory during the test does not exceed the upper limit value that allows IR drop, so it is necessary to reduce the operation speed to prevent malfunction due to IR drop The memory test can be performed at the actual operation speed.

  In addition, since the combination of memories to be tested at the same time is determined in consideration of the difference in test time length, the time required for the memory test can be shortened.

  FIG. 6 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.

  The semiconductor integrated circuit of the present embodiment is obtained by adding a test data generation unit 3 to the semiconductor integrated circuit of the first embodiment.

  The test data generation unit 3 includes a memory BIST (Built In Self Test) circuit, generates test data to be supplied to the memories MEM1 to MEMn in accordance with instructions from the test sequence control unit 1, and supplies the test data to the test target memory To do.

  According to the present embodiment, test data to be supplied to the test target memory is automatically generated in the semiconductor integrated circuit in accordance with the test sequence, thereby reducing the time required for test data creation. Can do.

  FIG. 7 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to Embodiment 3 of the present invention.

  The semiconductor integrated circuit of the present embodiment is provided with a phase adjustment unit 4 that adjusts the phase of a clock supplied to each memory during execution of a test sequence by the test sequence control unit 1 when the memories MEM1 to MEMn are clock synchronous. It is a thing.

  The clock phase adjustment unit 4 generates clocks CK1 to CKn to be supplied to the memories MEM1 to MEMn by changing the phases from the input clock CK.

  In the case of a clock synchronous memory, a large amount of current instantaneously flows at the operating edge of the clock. Therefore, when a plurality of memories are tested at the same time during execution of the test sequence by the test sequence control unit 1, if the clocks of the respective memories are in phase, the current consumption peaks overlap and the IR drop increases.

  Thus, in this embodiment, the phases of the clocks CK1 to CKn supplied to the memories MEM1 to MEMn are shifted little by little so that the peaks of the current consumption do not overlap even if a plurality of memories are tested simultaneously during the memory test.

  FIG. 8 is a waveform diagram showing an example of the operation of the clock phase adjustment unit 4.

  The phases of the clocks CK <b> 1 to CKn output from the clock phase adjustment unit 4 are slightly shifted, and accordingly, the current consumption peaks of the memories MEM <b> 1 to MEMn are also shifted little by little. As a result, even when a plurality of memories are tested at the same time, current consumption peaks do not overlap, and the size of the IR drop can be reduced.

  According to the present embodiment, since the size of the IR drop when a plurality of memories are tested simultaneously can be reduced, the operation margin during the memory test can be increased.

  In addition, since current consumption peaks do not overlap, more memories can be tested simultaneously, and the test time can be shortened.

  FIG. 7 shows an example in which the memories MEM1 to MEMn of the second embodiment are of the clock synchronization type. However, in the case where the memories MEM1 to MEMn of the first embodiment are of the clock synchronization type, the phase is the same as in the present embodiment. By providing the adjustment unit 4, the phase of the clock supplied to each memory can be adjusted.

DESCRIPTION OF SYMBOLS 1 Test sequence control part 2 Memory access control part 3 Test data generation part 4 Clock phase adjustment part MEM1-MEMMn Memory

Claims (5)

Multiple memories,
Test sequence control means for controlling a test sequence of the plurality of memories according to an external setting;
Memory access control means for controlling access to the plurality of memories in accordance with instructions from the test sequence control means. 2. The semiconductor integrated circuit according to claim 1, further comprising test data generation means for generating test data to be supplied to the plurality of memories in accordance with an instruction from the test sequence control means. When the plurality of memories are clock synchronous,
3. The semiconductor integrated circuit according to claim 1, further comprising: a clock phase adjusting unit that varies a phase of a clock input to the plurality of memories during execution of the test sequence by the test sequence control unit. A test method of a semiconductor integrated circuit having a test sequence control means for controlling a test sequence of a plurality of built-in memories,
Generating unit test data for testing each of the plurality of memories alone;
Performing a simulation of the semiconductor integrated circuit using the unit test data;
From the result of the simulation, analyzing the current consumption of the semiconductor integrated circuit at the time of test execution by each unit test data,
Generating a test sequence of the plurality of memories based on the analysis result of the current consumption;
Setting the test sequence to the test sequence control means. 5. The test method according to claim 4, further comprising a step of generating the unit test data by a test data generating means built in the semiconductor integrated circuit.

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