KR20100042388A - Delay locked loop circuit - Google Patents

Abstract

PURPOSE: A delay locked loop circuit is provided to control delay duration according to a clock frequency and a fuse cutting by changing delay duration in a delay locked loop circuit. CONSTITUTION: A delay locking part(601) outputs an internal clock by delaying an external clock by coarse delay duration and fine delay duration in order to compensate a phase skew of a semiconductor memory device. A delay duration controlling part(615) controls the fine delay duration according to a frequency of the external clock or a test mode. A phase comparison part(602) outputs a phase comparison signal by comparing the external clock with the phase of a feedback clock. A delay part(603) outputs an internal clock after delaying the external clock by the coarse delay duration and the fine delay duration in response to the phase comparison signal. A replica model part(613) outputs the feedback clock by receiving the internal clock.

Description

DELAY LOCKED LOOP CIRCUIT}

The present invention relates to a delay locked loop circuit, and more particularly, to a delay locked loop circuit capable of adjusting a delay amount according to clock frequency and fuse cutting.

1 is a block diagram of a conventional delayed fixed loop circuit having a single loop structure.

Referring to FIG. 1, a conventional delay locked loop circuit having a single loop structure includes a phase comparator 101, a delay unit 103, and a replica model unit 113.

The phase comparison unit 101 compares the phase of the feedback clock FB_CLK output from the replica model unit 113 that models the external clock EXT_CLK and the clock delay component inside the semiconductor memory device, and the external clock EXT_CLK and the feedback clock. A phase comparison signal CMP including information on the phase difference of FB_CLK is output to the delay unit 103.

The delay unit 103 is composed of a coarse delay control unit 105, a fine delay control unit 107, a coarse delay unit 109, and a fine delay unit 111.

The coarse delay control means 105 and the fine delay control means 107 determine a coarse delay control signal COARSE_CTRL and a fine delay control signal FINE_CTRL for determining a delay amount of the external clock EXT_CLK in response to the phase comparison signal CMP. )

The coarse delay means 109 is composed of a plurality of delay elements (not shown) having a unit delay amount UNIT_DD. In response to the coarse delay control signal COARSE_CTRL, the coarse delay means 109 delays the external clock EXT_CLK by a coarse delay amount COARSE_DD, which is twice the unit delay amount UNIT_DD, by a difference by the unit delay amount UNIT_DD. Generates first and second coarse delay clocks CLKDC_1 and CLKDC_2.

The fine delay means 111 mixes the phases of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 in response to the fine delay control signal FINE_CTRL so that the external clock EXT_CLK is smaller than the coarse delay amount COARSE_DD. The internal clock CLK_OUT is output by delaying by the delay amount FINE_DD. The fine delay means 111 performs the fine delay operation after the coarse delay operation of the coarse delay means 109 is completed, and does not mix the phases of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 during the coarse delay operation. Only one of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 is driven. For example, if the phase of the feedback clock FB_CLK is earlier than the phase of the external clock EXT_CLK, a coarse delay operation is performed. After that, the feedback clock FB_CLK is delayed so that the phase of the feedback clock FB_CLK is a unit delay amount (UNIT_DD). In the case where the phase of the external clock EXT_CLK is close to the phase, the fine delay operation may be performed.

Detailed operations of the fine delay unit 111 and the fine delay control unit 107 will be described later with reference to FIGS. 3 and 4.

When the internal clock CLK_OUT is input to the replica model unit 113 and the phases of the external clock EXT_CLK and the feedback clock FB_CLK coincide with each other through the above process, the internal clock CLK_OUT is delayed, that is, locked.

2 is a block diagram of a conventional delayed fixed loop circuit having a dual loop structure.

Referring to FIG. 2, a conventional delay locked loop circuit having a dual loop structure includes a first delay delay unit 201, a second delay delay unit 203, and a duty ratio correction unit 205.

The configuration of each of the first and second delay delay units 201 and 203 is similar to that of the delay locked loop circuit of FIG. However, since the second delay delay unit 203 inverts and outputs the external clock EXT_CLK in relation to the duty ratio correction operation performed by the duty ratio correction unit 205, the first internal clock CLK_OUT1 and the second internal clock are output. The rising edges of CLK_OUT2 are in phase with each other and the duty ratios of the first internal clock CLK_OUT1 and the second internal clock CLK_OUT2 are opposite to each other. The bubble shown at the output of the second delay delay unit 203 means inversion.

The duty ratio corrector 205 mixes the phases of the first and second internal clocks CLK_OUT1 and CLK_OUT2 to correct the duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2, and the first and second correction clocks. Outputs (CLK_CC1, CLK_CC2). As described above, since the rising edges of the first and second internal clocks CLK_OUT1 and CLK_OUT2 are in phase with each other, the duty ratio correction unit 205 phases the falling edges of the first and second internal clocks CLK_OUT1 and CLK_OUT2. Mix. According to the design, the duty ratio correction unit 205 detects the duty ratios of the first and second internal clocks CLK_OUT1 and CLK_OUT2 and further adds to the falling edges of one of the first and second internal clocks CLK_OUT1 and CLK_OUT2. Phase mixing can be done closer.

3 is a block diagram of the fine delay unit 111 of FIG.

Referring to FIG. 3, the fine delay means 111 includes first and second driving means 301 and 303 for driving each of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 with different driving forces. Each of the first and second driving means 301 and 303 is turned on / off in response to a positive / negative fine delay control signal FINE_CTRL <1: N> and FINE_CTRLB <1: N>. It consists of multiple inverters connected in parallel.

The fine delay control signal (FINE_CTRL <1: N>) is enabled sequentially from the least significant bit signal, and the negative delay control signal (FINE_CTRLB <1: N) is inversely related to the fine delay control signal (FINE_CTRL <1: N>). >) Is sequentially disabled from the least significant bit signal. Therefore, since the number of turned-on inverters among the inverters constituting the first and second driving means 301 and 303 is different, the driving force of the first and second driving means 301 and 303 is different. The edge of the internal clock CLK_OUT, which is an output signal of the fine delay unit 111, is the fine delay FINE_DD toward the edge of the coarse delay clock that is driven more strongly among the first and second coarse delay clocks CLKDC_1 and CLKDC_2. Move by).

On the other hand, when the frequency of the external clock EXT_CLK is higher than that, the jitter component has a worse effect on the operation performance of the semiconductor device. Therefore, the fine delay amount FINE_DD when the frequency of the external clock EXT_CLK is high. Need to be reduced. In this case, if you change the layout and connect nodes A, B, E, F and nodes C, D, G, and H through metal revision, respectively, Since the number of inverters capable of driving the first and second coarse delay clocks CLKDC_1 and CLKDC_2 is increased, when the nodes C, D, G, and H are not connected, the fine delay amount FINE_DD is reduced.

4 is a configuration diagram of the fine delay control means 107 of FIG.

Referring to FIG. 4, the fine delay control means 107 outputs a plurality of positive and negative fine delay control signals FINE_CTRL <1: N> and FINE_CTRLB <1: N> in response to the phase comparison signal CMP. And counting means 401-405.

At the beginning of operation, the counting means 401 to 405 are all initialized so that the fine delay control signals FINE_CTRL <1: N> are disabled and the fine delay control signals FINE_CTRLB <1: N> are enabled. It is a state. In this case, the fine delay means 111 outputs the second coarse delay clock CLKDC_2 to the internal clock CLK_OUT. Afterwards, when the phase of the external clock EXT_CLK is earlier than the phase of the second core delay clock CLKDC_2 by the coarse delay means 109, the counting means 401 to 405 may be connected to the phase comparison signal CMP. In response, the fine delay control signals FINE_CTRL <1: N> are sequentially enabled and the negative delay control signals FINE_CTRLB <1: N> are sequentially disabled. On the other hand, each of the counting means (401 to 405) receives the input fine delay control signal previously enabled to enable the fine delay control signal (FINE_CTRL <1: N>) sequentially.

On the other hand, in the case of FIG. 5B, even if all of the fine delay control signals FINE_CTRL <1: N> are enabled, the phases of the feedback clock FB_CLK and the external clock EXT_CLK may not coincide. In this case, if the nodes A, B, E and F of the fine delay means 111 and each of the nodes C, D, G and H are not connected, the coarse delay means 109 corresponds to the inverter of the fine delay means 111. In response to the delay control signal FINE_CTRL <N-2> of the last counting means 403, as shown in FIG. 5C, the delay amount of the second coarse delay clock CLKDC_2 is reduced by the coarse delay amount COARSE_DD. The fine delay control means 107 sequentially disables the fine delay control signal FINE_CTRL <1: N> and sequentially enables the negative fine delay control signal FINE_CTRLB <1: N>. On the other hand, each of the counting means (401 to 405) receives the input of the fine delay control signal previously disabled to disable the fine delay control signal.

When the number of inverters connected to each of nodes A, B, E, F and nodes C, D, G, and H through the metal revision in the fine delay means 111 is increased, the fine delay control means 107 correspondingly. ), The fine delay control signal FINE_CTRL <N> of the last counting means 405 corresponding to the inverter of the fine delay means 111 is input to the coarse delay control means 105 through the metal revision.

As a result, when the configuration of the fine delay control means 107 and the fine delay means 111 is changed through the metal revision in the conventional delay lock loop circuit, a new layout operation is required, and the delay amount of the delay lock loop circuit is changed. In the case of the test, the delayed loop circuit of the conventional delayed fixed loop circuit consumes unnecessary time and money due to the fact that the test should be performed by removing the package of the semiconductor device and performing a FIB (Focus Ion Beam) experiment. There is this.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a delay locked loop circuit which can change a delay amount without unnecessary time and cost.

According to an aspect of the present invention, a delay fixing unit outputs an internal clock by delaying an external clock by a coarse delay amount and a fine delay amount less than the coarse delay amount to compensate for phase skew of a semiconductor memory device; And a delay amount controller configured to adjust the fine delay amount according to a frequency or a test mode of the external clock.

In addition, the present invention for achieving the above object, the delay fixing unit for outputting the internal clock by delaying the external clock by the coarse delay amount and the fine delay amount less than the coarse delay amount to compensate for the phase skew of the semiconductor memory device; A fuse circuit unit enabling a fuse option signal according to whether a fuse is cut; And a delay amount control unit controlling the fine delay amount according to the fuse option signal or the test mode.

According to the present invention, the delay amount of the delay locked loop circuit can be changed according to the cas latency and the fuse option signal without using the metal revision. In addition, the delay amount of the delay locked loop circuit can be changed according to the test mode without using the FIB experiment. Therefore, the present invention has the effect of reducing the time and cost unnecessarily consumed in the production of semiconductor devices.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

6 is a configuration diagram of a delay locked loop circuit according to an embodiment of the present invention.

As shown in the figure, the delay lock loop circuit according to the present invention includes a delay fixer 601 and a delay controller 615. The delay fixing unit 601 includes a phase comparison unit 602, a delay unit 603, and a replica model unit 613.

The phase comparison unit 601 compares the phase of the feedback clock FB_CLK output from the external clock EXT_CLK and the replica unit 613 that models the clock delay component inside the semiconductor memory device to delay the phase comparison signal CMP. Output to (603).

The delay unit 603 includes a coarse delay control unit 605, a fine delay control unit 607, a coarse delay unit 609, and a fine delay unit 611.

The coarse delay control means 605 and the fine delay control means 607 include a coarse delay control signal COARSE_CTRL and a fine delay control signal FINE_CTRL for determining a delay amount of the external clock EXT_CLK in response to the phase comparison signal CMP. )

The coarse delay means 609 is composed of a plurality of delay elements (not shown) having a unit delay amount UNIT_DD. The coarse delay means 609 delays the external clock EXT_CLK by the coarse delay amount COARSE_DD in response to the coarse delay control signal COARSE_CTRL, thereby making the first and second coarse delay clocks different from each other by the unit delay amount UNIT_DD. Create (CLKDC_1, CLKDC_2).

The fine delay means 611 mixes the phases of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 in response to the fine delay control signal FINE_CTRL to delay the external clock EXT_CLK by the fine delay amount FINE_DD. Outputs the delay-locked internal clock (CLK_OUT). The fine delay means 611 performs a fine delay operation after the coarse delay operation of the coarse delay means 609 is completed, and does not mix phases of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 during the coarse delay operation. Only one of the first and second coarse delay clocks CLKDC_1 and CLKDC_2 is driven.

On the other hand, unlike the prior art, the fine delay control means 607 and the fine delay means 611 of the delay locked loop circuit according to the present invention are fine in response to the selection signal SEL generated by the delay amount control unit 615 described later. You can adjust the delay amount (FINE_DD).

The delay amount control unit 615 outputs the selection signal SEL for determining the fine delay amount FINE_DD according to the frequency of the external clock EXT_CLK to the fine delay control means 607 and the fine delay stage 611. As described above, when the frequency of the external clock EXT_CLK is higher, the jitter component has a worse effect on the operation performance of the semiconductor device. Therefore, when the frequency of the external clock EXT_CLK is high, the fine delay amount FINE_DD is reduced. I need to. The delay amount controller 615 generates the selection signal SEL according to the cas latency (CL) as an example.

The CAS latency CL is the number of cycles of the external clock EXT_CLK until a data is output to the outside of the semiconductor memory device after a read command is input from the semiconductor memory device. In general, the frequency of the external clock EXT_CLK is increased. As it increases, the CAS latency also increases. Accordingly, the delay amount control unit 615 generates the selection signal SEL in response to the cascade latency signal CL_CTRL including information on the cascade latency CL. The CAS latency signal CL_CTRL may be generated in a mode register set (MRS).

On the other hand, the delay amount control unit 615 generates the selection signal SEL even in response to the test signal TM according to the test mode regardless of the cascade latency CL.

Detailed operations of the fine delay unit 611, the fine delay control unit 607 and the delay amount control unit 615 will be described later with reference to FIGS. 7 to 9.

As a result, the delay locked loop circuit according to the present invention can adjust the fine delay amount (FINE_DD) according to the frequency and test mode of the external clock EXT_CLK without using metal revision and FIB experiments, so it is unnecessary to produce semiconductor devices. The time and cost of doing so can be reduced.

On the other hand, the delay lock loop circuit according to the present invention can be employed in the first and second delay delay section (201, 203) of FIG.

7 is a configuration diagram of the fine delay unit 611 of FIG.

As shown in the figure, the fine delay means 611 includes first and second driving means 701 and 703 and second selecting means 705, 707, 709 and 711. As shown in FIG.

The first and second driving means 701 and 703 are turned on / off in response to the positive / negative fine delay control signals FINE_CTRL <1: N> and FINE_CTRLB <1: N>. It includes a plurality of inverters for adjusting the driving force of each of the first and second core delay clock (CLKDC_1, CLKDC_2).

The fine delay control signal (FINE_CTRL <1: N>) is enabled sequentially from the least significant bit signal, and the negative delay control signal (FINE_CTRLB <1: N) is inversely related to the fine delay control signal (FINE_CTRL <1: N>). >) Is sequentially disabled from the least significant bit signal. Accordingly, since the number of turned-on inverters among the inverters constituting the first and second driving means 701 and 703 is different, the driving force of the first and second driving means 701 and 703 is different. The edge of the internal clock CLK_OUT, which is an output signal of the fine delay unit 611, is equal to the fine delay amount FINE_DD toward the edge of the coarse delay clock driven more strongly among the first and second coarse delay clocks CLKDC_1 and CLKDC_2. Move.

The second selecting means 705, 707, 709, 711 selects the number of inverters that receive the first and second coarse delay clocks CLKDC_1 and CLKDC_2 in response to the selection signals SEL <1: 2>.

When the delay control unit 615 enables the selection signal SEL <2> to 'high' in response to the high cascade latency CL, the pass gate included in the second selection means 705, 707, 709, and 711 is included. Reference numerals 713 to 716 turn on to increase the number of inverters that receive and drive the first and second coarse delay clocks CLKDC_1 and CLKDC_2. That is, when the selection signal SEL <2> is enabled, all inverters of the first and second driving means 701 and 703 receive and drive the first and second coarse delay clocks CLKDC_1 and CLKDC_2. When the signal SEL <2> is disabled, only the inverter turned on / off in response to the positive / negative fine delay control signals FINE_CTRL <1: N-2> and FINE_CTRLB <1: N-2> It is driven by receiving two-core delay clocks CLKDC_1 and CLKDC_2. Therefore, when the frequency of the external clock EXT_CLK increases, the number of inverters used in the fine delay means 611 increases, so the fine delay means 611 responds to the selection signal SEL <1: 2> to determine the fine delay amount ( FINE_DD) can be decreased.

On the other hand, the second selecting means 705, 709 transmits a signal of the ground voltage VSS level to the second selecting means 705, 707, 709, 711 in response to the selection signal SEL <1>, as shown. It may include a passgate for transmitting to the inverter not selected by the case, in which case the current consumption of the inverter not selected by the second selection means (705, 707, 709, 711) is reduced.

7 illustrates a case in which the number of inverters is determined in two cases, but the number of inverters may be determined in various cases according to a selection signal and a passgate. 8 and 9 will be described as one embodiment corresponding to the embodiment of FIG.

8 is a configuration diagram of the fine delay control means 607 of FIG.

As shown in the figure, the fine delay control means 607 includes a plurality of counting means 801 to 805 and first selection means 807.

At the beginning of operation, the counting means 801 to 805 are all initialized so that the fine delay control signals FINE_CTRL <1: N> are disabled and the fine delay control signals FINE_CTRLB <1: N> are enabled. It is a state. Then, in response to the phase comparison signal CMP, the counting means 801 to 805 sequentially enable or disable the positive / fine fine delay control signals FINE_CTRL <1: N> and FINE_CTRLB <1: N>. do. At this time, each of the counting means 801 to 805 receives a fine delay control signal (FINE_CTRL <1: N>) that is enabled or disabled previously, and then sequentially / fine fine delay control signals (FINE_CTRL <1: N>, Enable or disable FINE_CTRLB <1: N>). For example, the counting means 802 enables the fine delay control signal FINE_CTRL <2> only when the fine delay control signal FINE_CTRL <1> by the counting means 801 is enabled.

On the other hand, even when both the positive and negative fine delay control signals FINE_CTRL <1: N> and FINE_CTRLB <1: N> are enabled or disabled, there is a phase difference between the external clock EXT_CLK and the feedback clock FB_CLK. In this case, in response to the delay control signals FINE_CTRL <1> and FINE_CTRL <N>, which are the highest or lowest bit signals, the coarse delay means 609 may perform a first coarse delay clock CLKDC_1 or a second coarse delay clock CLKDC_2. The delay amount is increased or decreased by the coarse delay amount COARSE_DD.

The first selection means 807 includes passgates which are turned on / off in response to the selection signals SEL <1: 2> and determine valid top bit signals of the fine delay control signal FINE_CTRL <1: N>. do. Here, the most significant bit signal valid means a delay control signal that is a positive wave of the last counting means corresponding to the inverter of the fine delay means 611.

As described above, when all of the fine delay control signals FINE_CTRL <1: N> are enabled, the first coarse delay clock CLKDC_1 or the second coarse delay clock CLKDC_2 should be increased or decreased by the coarse delay amount. . Therefore, when the selection signal SEL <2> is enabled, all the inverters drive the first and second coarse delay clocks CLKDC_1 and CLKDC_2 in the fine delay means 611, so that the fine delay control signal of the counting means 805 ( FINE_CTRL <N>) is a valid most significant bit signal. In this case, the first selection means 807 transfers the fine delay control signal FINE_CTRL <N> of the counting means 805 to the coarse delay control means 605 in response to the selection signal SEL <2>.

In addition, when the selection signal SEL <2> is disabled and the selection signal SEL <1> is enabled as 'high', the fine delay means 611 provides a positive / negative fine delay control signal FINE_CTRL <1: N−. 2>, only the inverter turned on / off in response to FINE_CTRLB <1: N-2>) drives the first and second coarse delay clocks CLKDC_1 and CLKDC_2, so the fine delay control signal FINE_CTRL of the counting means 803 <N-2>) is a valid most significant bit signal. In this case, the first selection means 807 transfers the fine delay control signal FINE_CTRL <N-2> of the counting means 803 to the coarse delay control means 605 in response to the selection signal SEL <1>. .

9 is a configuration diagram of the delay amount control unit 615 of FIG. 6.

As illustrated in FIG. 9, the delay amount controller 615 includes an input unit 901 and an enable unit 907. The input means 901 receives the cascade latency signal CL_CTRL <1: 6> and the test signal TM <1: 2>, and the enable means 907 selects in response to the output signal of the input means 901. Enable signals SEL <1: 2>.

FIG. 9 illustrates a case in which the delay amount control unit 615 generates the selection signals SEL <1: 2> according to the cascade latency CL of two to seven and two test modes. The CAS latency signals CL_CTRL <1: 6> indicate that the CAS latency CL is 2 to 7, respectively. If the test mode is not in the test mode, the test signals TM <1: 2> are 'low' and node X is 'low' by the first or gate 904.

When the frequency of the external clock EXT_CLK is low, that is, when one of the cascade latency signals CL_CTRL <1: 3> is enabled as 'high', the first north gate 901 outputs a 'low' signal and thus the second signal. The or gate 910 outputs the select signal SEL <1> enabled with 'high'. Therefore, the fine delay means 611 described above increases the fine delay amount FINE_DD in response to the selection signal SEL <1>.

When the frequency of the external clock EXT_CLK is high, that is, when one of the cascade latency signals CL_CTRL <4: 6> is enabled as 'high', the second north gate 905 outputs a 'low' signal, thereby causing a third signal. The or gate 911 outputs the selection signal SEL <2> enabled with 'high'. Therefore, the fine delay means 611 described above reduces the fine delay amount FINE_DD in response to the selection signal SEL <2>.

In the test mode, when the test signal TM <1: 2> is enabled as 'high', the node X becomes 'high' and the third and fourth are independent of the cas latency signal CL_CTRL <1: 6>. NOR gates 908 and 909 output a 'low' signal. Therefore, when the test signal TM <1> is enabled as 'high', the selection signal SEL <1> is enabled by the second or gate 910 and the test signal TM <2> is 'high'. When enabled, since the selection signal SEL <2> is enabled by the third or gate 911, the operation of the delay locked loop circuit may be tested according to the test mode.

10 is a block diagram of a delay locked loop circuit according to another embodiment of the present invention.

As shown in the figure, the delay lock loop according to the present invention includes a delay lock 1001, a delay amount control unit 1015 and a fuse circuit unit 1017. The delay fixing unit 1001 includes a phase comparison unit 1002, a delay unit 1003, and a replica model unit 1013. Unlike the delay locked loop circuit of FIG. 6, the delay locked loop circuit of FIG. 10 further includes a fuse circuit unit 1017.

The fuse circuit unit 1017 enables the fuse option signal FUSE_OP according to whether the fuse is cut before the semiconductor device packaging. For example, the fuse option signal FUSE_OP may be enabled as 'high' when the fuse is not cut and may be disabled as 'low' when the fuse is cut by a laser or the like. The delay amount control unit 1015 receives the fuse option signal FUSE_OP generated by the fuse circuit unit 1017 instead of the cascade latency signal CL_CTRL and generates a selection signal SEL. Therefore, the fine delay means 1011 increases or decreases the fine delay amount FINE_DD depending on whether the fuse is cut.

As a result, the delayed fixed loop circuit according to the present invention, unlike the conventional delayed fixed loop circuit, can control the fine delay amount by only cutting the fuse before packaging the semiconductor device without using a metal revision and FIB experiment. Unnecessary time and cost consumed can be reduced.

On the other hand, the delay lock loop circuit according to the present invention can be employed in the first and second delay delay section (201, 203) of FIG.

FIG. 11 is a configuration diagram of the delay amount control unit 1015 of FIG. 10.

As shown in FIG. 11, the delay amount control unit 1015 includes an input unit 1101 and an enable unit 1105. The input means 1101 receives the cascade latency fuse option signal FUSE_OP and the test signals TM <1: 2>, and the enable means 1105 responds to the output signal of the input means 1101. Enable <1: 2>.

FIG. 11 illustrates a case where the selection signals SEL <1: 2> are generated according to one fuse option signal FUSE_OP and two test modes. When the test mode is not in the test mode, the test signals TM <1: 2> are 'low' and node Y is 'low' by the first or gate 1104.

When the fuse of the fuse circuit unit 1017 is not cut, that is, when the fuse option signal FUSE_OP is enabled as 'high', the 'low' signal is input to the first north gate 1106 by the inverter 1103. . Accordingly, the second or gate 1108 outputs the selection signal SEL <1> enabled with 'high'. Therefore, the fine delay unit 1011 described above increases the fine delay amount FINE_DD in response to the selection signal SEL <1>.

When the fuse of the fuse circuit unit 1017 is cut, that is, when the fuse option signal FUSE_OP is disabled as 'low', the 'low' signal is input to the second north gate 1107. Accordingly, the third or gate 1109 outputs the select signal SEL <2> enabled with 'high'. Therefore, the fine delay unit 1011 described above reduces the fine delay amount FINE_DD in response to the selection signal SEL <2>.

In the test mode, when the test signal TM <1: 2> is enabled as 'high', the node Y is in a 'high' state and the first and second knock gates 1106, 1 are independent of the fuse option signal FUSE_OP. 1107 outputs a 'low' signal. Therefore, when the test signal TM <1> is enabled as 'high', the selection signal SEL <1> is enabled by the second or gate 1108 and the test signal TM <2> is 'high'. When enabled, the select signal SEL <2> is enabled high by the third or gate 1109, so that the operation of the delay locked loop circuit may be tested according to the test mode.

Although the present invention has been described by means of limited embodiments and drawings, the present invention is not limited thereto and is intended to be equivalent to the technical idea and claims of the present invention by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible.

1 is a configuration diagram of a conventional delayed fixed loop circuit having a single loop structure,

2 is a configuration diagram of a conventional delayed fixed loop circuit having a dual loop structure,

3 is a configuration diagram of the fine delay means of FIG.

4 is a configuration diagram of the fine delay control means of FIG.

5A, 5B and 5C are waveform diagrams of signals for helping the description of FIG. 4,

6 is a configuration diagram of a delay locked loop circuit according to an embodiment of the present invention;

7 is a configuration diagram of the fine delay unit of FIG.

8 is a configuration diagram of the fine delay control means of FIG. 6;

9 is a configuration diagram of a delay amount control means of FIG. 6;

10 is a configuration diagram of a delay locked loop circuit according to another embodiment of the present invention;

FIG. 11 is a configuration diagram of the delay amount control means of FIG. 10.

Claims (20)

A delay fixing unit outputting an internal clock by delaying an external clock by a coarse delay amount and a fine delay amount less than the coarse delay amount to compensate for phase skew of the semiconductor memory device; And Delay amount control unit for adjusting the fine delay amount according to the frequency or test mode of the external clock Delay fixed loop circuit comprising a. The method of claim 1, The delayed fixing A phase comparator for comparing a phase of the external clock and a feedback clock to output a phase comparison signal; A delay unit outputting the internal clock by delaying the external clock by the coarse delay amount and the fine delay amount in response to the phase comparison signal; And A replica model unit for receiving the internal clock and outputting the feedback clock Delay fixed loop circuit comprising a. 3. The method of claim 2, The delay unit Coarse delay control means for outputting a coarse delay control signal in response to the phase comparison signal; Coarse delay means for generating first and second coarse delay clocks by delaying the external clock by the coarse delay amount in response to the coarse delay control signal; Fine delay control means for outputting a fine delay control signal in response to the phase comparison signal and the selection signal; And Fine delay means for generating the internal clock by mixing phases of the first and second coarse delay clocks by the fine delay amount in response to the fine delay control signal and the selection signal; Including; The delay amount control unit Generating the selection signal for determining the fine delay amount according to the cas latency or the test mode Delayed fixed loop circuit. The method of claim 3, The fine delay control means A plurality of counting means for sequentially enabling the fine delay control signal composed of a plurality of bit signals in response to the phase comparison signal; And First selecting means for determining a valid most significant bit signal of the fine delay control signal in response to the selection signal &Lt; / RTI &gt; When the most significant bit signal of the fine delay control signal is enabled, the external clock is delayed by the coarse delay amount by the coarse delay means. Delayed fixed loop circuit. The method of claim 4, wherein When the fine control signal is disabled, the delay amount of the external clock is reduced by the coarse delay amount by the coarse delay means. Delayed fixed loop circuit. The method of claim 4, wherein The first selection means A plurality of passgates for transmitting one bit signal of the fine delay control signal Delay fixed loop circuit comprising a. The method of claim 3, The fine delay means Driving means on / off in response to the fine delay control signal and including a plurality of inverters for adjusting driving force of each of the first and second coarse delay clocks; And Second selection means for selecting the number of the inverters receiving the first and second coarse delay clocks in response to the selection signal; Delay fixed loop circuit comprising a. The method of claim 7, wherein The second selection means A plurality of passgates which transmit the first and second coarse delay clocks or output signals of the inverter; Delay fixed loop circuit comprising a. The method of claim 8 The second selection means Passgate that delivers a signal at ground voltage level to the unselected inverter Delay fixed loop circuit further comprising. The method of claim 3, The delay amount control unit Input means for receiving a cascade latency signal and a test signal; And Enable means for enabling the selection signal in response to an output signal of the input means Delay fixed loop circuit comprising a. A delay fixing unit outputting an internal clock by delaying an external clock by a coarse delay amount and a fine delay amount less than the coarse delay amount to compensate for phase skew of the semiconductor memory device; A fuse circuit unit enabling a fuse option signal according to whether a fuse is cut; And Delay amount control unit for adjusting the fine delay amount in accordance with the fuse option signal or the test mode Delay fixed loop circuit comprising a. The method of claim 11, The delayed fixing A phase comparator for comparing a phase of the external clock and a feedback clock to output a phase comparison signal; A delay unit outputting the internal clock by delaying the external clock by a coarse delay amount or the fine delay amount in response to the phase comparison signal; And A replica model unit for receiving the internal clock and outputting the feedback clock Delay fixed loop circuit comprising a. The method of claim 12, The delay unit Coarse delay control means for outputting a coarse delay control signal in response to the phase comparison signal; Coarse delay means for generating first and second coarse delay clocks by delaying the external clock by the coarse delay amount in response to the coarse delay control signal; Fine delay control means for outputting a fine delay control signal in response to the phase comparison signal and the selection signal; And Fine delay means for generating the internal clock by mixing phases of the first and second coarse delay clocks by the fine delay amount in response to the fine delay control signal and the selection signal; Including The delay amount control unit Generating the selection signal for determining the fine delay amount according to the fuse option signal or the test mode Delayed fixed loop circuit. The method of claim 13, The fine delay control means A plurality of counting means for sequentially enabling the fine delay control signal composed of a plurality of bit signals in response to the phase comparison signal; And First selecting means for determining a valid most significant bit signal of the fine delay control signal in response to the selection signal &Lt; / RTI &gt; When the most significant bit signal of the fine delay control signal is enabled, the external clock is delayed by the coarse delay amount by the coarse delay means. Delayed fixed loop circuit. 15. The method of claim 14, When the fine control signal is disabled, the delay amount of the external clock is reduced by the coarse delay amount by the coarse delay means. Delayed fixed loop circuit. 15. The method of claim 14, The first selection means A plurality of passgates for transmitting one bit signal of the fine delay control signal Delay fixed loop circuit comprising a. The method of claim 13, The fine delay means Driving means on / off in response to the fine delay control signal and including a plurality of inverters for adjusting driving force of each of the first and second coarse delay clocks; And Second selection means for determining the number of the inverters receiving the first and second coarse delay clocks in response to the selection signal; Delay fixed loop circuit comprising a. The method of claim 17, The second selection means A plurality of passgates which transmit the first and second coarse delay clocks or output signals of the inverter; Delay fixed loop circuit comprising a. The method of claim 18 The second selection means Passgate that delivers a signal at ground voltage level to the unselected inverter Delay fixed loop circuit further comprising. The method of claim 13, The delay amount control unit Input means for receiving the fuse option signal and the test signal; And Enable means for enabling the selection signal in response to an output signal of the input means Delay fixed loop circuit comprising a.

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