JP2006091940A - Memory control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control device capable of reducing power consumption or unnecessary radiation. <P>SOLUTION: This device has a constitution wherein a memory control part 3 is provided with an inspection execution/determination part 2 for executing an inspection whether writing data on a memory 7 agree with reading data from the memory or not and determining its quality, and an output current from an memory interface part 7, an output voltage from the memory interface part and a pattern of a memory control timing of the memory control part 3 are adjusted according to a comparison result by the inspection execution/determination part 2. A driving current and a driving voltage of the memory 7 can be optimized, while avoiding a memory data error, by this constitution, and thereby the power consumption or unnecessary radiation can be reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory control device of a system using a memory.

  2. Description of the Related Art Conventionally, in a memory control device, a memory control timing margin is adjusted so that a memory data error due to insufficient memory driving capability or timing margin is avoided and the memory can be driven normally and at high speed.

  Such a timing margin control method and control apparatus are disclosed in, for example, Japanese Patent No. 3490403. The method disclosed in this publication is to inspect a memory and adjust the frequency of the memory drive clock signal by determining whether the inspection result is good or bad.

In the conventional memory control device, the drive capability of the memory interface unit that drives the memory is designed with a fixed value in advance. That is, in designing the drive capability of the memory interface unit, the drive current and the drive voltage are fixed to values having a sufficient margin in order to avoid memory data errors due to insufficient memory drive capability.
Japanese Patent No. 3490403

  However, in the case of the conventional memory control device as described above, only the frequency of the memory drive clock signal is adjusted, and the drive current and drive voltage of the memory interface unit are fixed to values having a sufficient margin in advance. More operating current than necessary has been a factor causing deterioration of power consumption and unnecessary radiation.

  Therefore, an object of the present invention is to provide a memory control device that can reduce power consumption and unnecessary radiation.

  In order to achieve the above-described object, the memory control device according to the present invention includes a determination unit that performs an inspection to determine whether the data written to the memory matches the data read from the memory, and determines whether the data is good or bad. The output current of the memory interface unit, the output voltage of the memory interface unit, and the pattern of the memory control timing are adjusted according to the comparison result of the determination means.

  Further, the memory control device of the present invention processes the data before writing to the memory, outputs the error occurrence status during the data processing, and processes the data after reading from the memory, A post-read processing means for outputting the error occurrence status during the data processing, and a comparison determination means for comparing the error occurrence status output from the pre-write processing means with the error occurrence status output from the post-read processing means And the output current of the memory interface unit, the output voltage of the memory interface unit, and the pattern of the memory control timing are adjusted according to the comparison result of the comparison / determination means.

  According to the above configuration, when the determination result is good according to the comparison result of the determination unit or the comparison result of the comparison determination unit, the output current and output voltage (memory drive current and drive voltage) of the memory interface unit are When the pattern of the memory control timing is later than the current state or the current state is maintained, and the determination result is NO, the output current and output voltage of the memory interface unit (memory drive current and drive voltage) are By increasing the memory control timing pattern faster than the current state, the memory drive current and drive voltage are optimized while avoiding memory data errors.

  The memory control device of the present invention has the above-described configuration, can optimize the memory driving capability (memory driving current and driving voltage) while avoiding memory data errors, and can reduce power consumption and unnecessary radiation. Has the effect of.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Embodiment 1]
FIG. 1 is a block diagram showing a configuration of a memory control device according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the memory control device controls the memory 7, the memory interface unit 6 that drives the memory 7, and the writing of data to the memory 7 and the reading from the memory 7 via the memory interface unit 6. The memory control unit 3 is provided, the memory interface unit 6 is provided with the current switching unit 4 and the voltage switching unit 5, and the memory control unit 3 is provided with the timing generation unit 1, the inspection execution / determination unit 2, and the access status determination unit 31. Yes.

  The inspection execution / determination unit 2 is a determination unit that determines whether or not the write data to the memory 7 and the read data from the memory 7 coincide with each other, and determines the quality. The timing generator 1, the current switching unit 4, and the voltage switching unit 5 are output. The access status determination unit 31 is an access status determination unit that monitors the access status of the memory 7 and compares it with an arbitrary reference value to determine whether the access status is rough or dense. To part 1.

  The current switching unit 4 is a current switching unit that switches the output current of the memory interface unit 6 (drive current of the memory 7) to an arbitrary value in accordance with the test determination result input from the test execution / determination unit 2. The output current of the memory interface unit 6 is switched according to the determination result of the inspection execution / determination unit 2. The current switching unit 4 has means for individually setting the output current of each signal line of the memory interface unit 6 when setting the output current of the memory interface unit 6. An example of the configuration of the current switching unit 4 is shown in FIG.

  As shown in FIG. 2, the current switching unit 4 includes a buffer 8 with an output current I, a buffer 9 with an output current 2I, and a buffer 10 with an output current 4I, a switch 11, a switch 12, 13 in parallel with each other. When only the switch 11 is connected, the output current of the memory interface unit 6 becomes I, when only the switch 12 is connected, the output current of the memory interface unit 6 becomes 2I, and when only the switch 13 is connected, the output current of the memory interface unit 6 becomes When the switch 11 and the switch 12 are connected, the output current of the memory interface unit 6 is 3I. When the switch 11 and the switch 13 are connected, the output current of the memory interface unit 6 is 5I. When the two switches 12 and 13 are connected, the output current of the memory interface unit 6 becomes 6I. When all the switches 11, 12 and 13 are connected, the output current of the memory interface unit 6 becomes 7I. Therefore, in the present configuration example, the switch 11, the switch 12, and the switch 13 are selected and driven according to the determination result of the inspection performed by the inspection execution / determination unit 2 to obtain the output current of each signal line of the memory interface unit 6. Seven types of I, 2I, 3I, 4I, 5I, 6I, and 7I can be selected.

  The voltage switching unit 5 is voltage switching means for switching the output voltage of the memory interface unit 6 (drive voltage of the memory 7) to an arbitrary value in accordance with the inspection determination result input from the inspection execution / determination unit 2. The output voltage of the memory interface unit 6 is switched according to the determination result of the inspection execution / determination unit 2. This voltage switching means 5 has means for individually setting the output voltage of each signal line of the memory interface 6 when setting the output voltage of the memory interface section 6. An example of the configuration of the voltage switching unit 5 is shown in FIG.

  As shown in FIG. 3, the voltage switching unit 5 includes a switching type transformation unit 14 that transforms an input voltage to generate an output voltage, and a switching control unit 17 that includes a pulse adjustment unit 15 and a pulse conversion unit 16. Yes. The switching pulse generated by the pulse converter 16 is adjusted by the setting in the pulse adjuster 15 and the feedback of the output voltage of the switching transformer 14, and the switching of the switching transformer 14 so as to obtain a desired output voltage. Is controlling. Therefore, in this configuration example, the output voltage of each signal line of the memory interface unit 6 can be switched by changing the setting in the pulse adjustment unit 15 according to the determination result of the inspection by the inspection execution / determination unit 2. it can.

The timing generator 1 is a timing generator that generates a plurality of patterns of write enable signals, address signals, and data signals in units of one cycle of the reference clock signal, that is, switches the memory control timing to a plurality of patterns. The memory control unit 3 controls the memory 7 via the memory interface unit 6 at the memory control timing generated by the timing generation unit 1. FIG. 4 is a timing chart showing an example of a memory control timing pattern generated by the timing generation unit 1 in the memory control device shown in FIG. This timing chart shows the timing of the reference clock signal 18, the write enable signal 19, the address signal 20, and the data signal 21, and the memory 7 performs a synchronization operation at the rising edge of the reference clock signal 18. The write enable signal 19 is a negative enable signal, and a write operation is performed at the L level. Three types of memory control timing patterns, Pattern 1 to Pattern 3, are preset as a plurality of patterns.
"Pattern 1"
In the pattern 1, the write enable signal 18, the address signal 20, and the data signal 21 are formed with one cycle of the reference clock signal 18 as a minimum cycle unit. In this timing chart, by enabling the write enable signal 19, the “D1” data set by the data signal 21 is written to the “A1” address set by the address signal 20, and then the “A3” address is set by the address signal 20. Thus, the operation of reading “D3” data from the data signal 21 is shown.
"Pattern 2"
In the pattern 2, the write enable signal 18, the address signal 20 and the data signal 21 are formed with the two cycles of the reference clock signal 18 as a minimum cycle unit. In this timing chart, by enabling the write enable signal 19, the “D2” data set by the data signal 21 is written to the “A2” address set by the address signal 20, and then the “A1” address is set by the address signal 20. Thus, the operation of reading “D1” data from the data signal 21 is shown.
"Pattern 3"
In the pattern 3, the write enable signal 18, the address signal 20, and the data signal 21 are formed with the three cycles of the reference clock signal 18 as a minimum cycle unit. In this timing chart, by enabling the write enable signal 19, the “D3” data set by the data signal 21 is written to the “A3” address set by the address signal 20, and then the “A2” address is set by the address signal 20. Thus, the operation of reading “D2” data from the data signal 21 is shown.

  Therefore, in the present configuration example, the three types of memory control timing patterns are arbitrarily switched and used in accordance with the test determination result of the test execution / determination unit 2 and the determination result of the access status determination unit 31.

  With the above configuration, the current switching unit 4 and the voltage switching unit 5 are adjusted according to the determination result output from the inspection execution / determination unit 2 to determine the current and voltage of the memory interface unit 6 that drives the memory 7. Further, the timing generation unit 1 is adjusted in accordance with the determination results output from the inspection execution / determination unit 2 and the access status determination unit 31, and the memory control timing of the memory control unit 3 is determined.

That is, when the determination result of the inspection execution / determination unit 2 is good, that is, when it is determined that the write data to the memory 7 and the read data from the memory 7 match,
a1. In the current switching unit 4, the output current of the memory interface unit 6 (drive current of the memory 7) is adjusted (switched) to be less than the current level, or adjusted to maintain the current level,
a2. In the voltage switching unit 5, the output voltage of the memory interface unit 6 (drive voltage of the memory 7) is adjusted (switched) to be smaller than the current level, or adjusted to maintain the current level,
a3. In the timing generation unit 1, the memory control timing pattern is selected to be slower than the current state or to maintain the current state. Subsequently, in the timing generation unit 1, when the access status determination unit 31 determines that the access status is rough, the memory control timing pattern is adjusted (set) to be slower than the current status, and the access status determination unit 31 determines the access status. Is determined (set) so as to maintain the current pattern of the memory control timing.

When the determination result of the inspection execution / determination unit 2 is negative, that is, when it is determined that the write data to the memory 7 and the read data from the memory 7 do not match,
b1. In the current switching unit 4, the output current of the memory interface unit 6 (drive current of the memory 7) is adjusted (switched) to be larger than the current state,
b2. In the voltage switching unit 5, the output voltage of the memory interface unit 6 (drive voltage of the memory 7) is adjusted (switched) to be larger than the current state,
b3. The timing generation unit 1 adjusts (sets) the memory control timing pattern so as to be faster than the current state.

  Due to the above action, when the determination result of the inspection execution / determination unit 2 is good, the drive current of the memory 7 and the drive voltage of the memory 7 are reduced or maintained from the current state, and the pattern of the memory control timing is later than the current state or When the current status is selected and the access status determination unit 31 determines that the access status is rough, the memory control timing pattern is adjusted (set) to be slower than the current status, and the access status is fine. , The memory control timing pattern is adjusted (set) so as to maintain the current state. When the determination result of the inspection execution / determination unit 2 is negative, the drive current of the memory 7 and the drive voltage of the memory 7 are increased from the current level, and the pattern of the memory control timing is adjusted (set) to be faster than the current level. . Therefore, the drive current of the memory 7 and the drive voltage of the memory 7 are optimized while avoiding memory data errors.

  As described above, according to the first embodiment, it is possible to optimize the driving capability of the memory 7 (the driving current of the memory 7 and the driving voltage of the memory 7) while avoiding the memory data error, thereby reducing power consumption and unnecessary radiation. Can be reduced.

  Further, according to the first embodiment, the timing generation unit 1 is provided as a means for adjusting the timing margin of memory control, and the timing generation unit 1 adjusts the memory control timing to switch between multiple timing patterns (patterns 1 to 3). Since the timing margin can be adjusted only by the logic circuit, the circuit scale can be reduced and the current consumption can be reduced.

Further, according to the first embodiment, when a change in the memory 7 or a change in the memory interface status occurs, a memory data error due to insufficient memory drive capability can be avoided by making an adjustment immediately, and the memory 7 is driven. Capability can always be maintained optimally.
[Embodiment 2]
FIG. 5 is a block diagram showing a configuration of the memory control device according to the second embodiment of the present invention. Note that the same components as those of the memory control device (FIG. 1) in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 5, the memory control device includes a pre-write processing unit 24 provided with a data processing unit 22 and an error signal generation unit 23, and a post-read processing unit provided with a data processing unit 25 and an error signal generation unit 26. 27 is provided, and the memory control unit 30 is provided with a comparison / determination unit 29 instead of the inspection execution / determination unit 2. The configuration example of the current switching unit 4 is the same as the configuration example shown in FIG. 2, and the configuration example of the voltage switching unit 5 is the timing generated by the timing generation unit 1 as in the configuration example shown in FIG. The pattern example is the same as the timing pattern example shown in FIG.

  The data processing unit 22 is means for processing data before being written to the memory 7, and the error signal generation unit 23 generates and outputs a processing error signal from an error occurrence situation that occurs when the data processing unit 22 processes the data. The pre-write processing unit 24 constitutes a pre-write processing unit that processes data before writing to the memory 7 and outputs an error occurrence status during the data processing. In the pre-write processing unit 24, data before being written to the memory 7 is processed by the data processing unit 22, and a processing error signal at that time is output from the error signal generating unit 23 to the comparison / determination unit 29.

  The data processing unit 25 is a means for processing the data read from the memory 7, and the error signal generation unit 26 generates a processing error signal from an error occurrence situation that occurs when the data processing unit 25 processes the data. The post-read processing unit 27 constitutes post-read processing means for processing the data read from the memory 7 and outputting the error occurrence status during the data processing. In the post-read processing unit 27, the data read from the memory 7 is processed by the data processing unit 25, and a processing error signal at that time is output from the error signal generation unit 26 to the comparison / determination unit 29.

  The comparison / determination unit 29 included in the memory control unit 30 includes a processing error signal (error occurrence state) output from the error signal generation unit 23 of the pre-write processing unit 24 and an error signal generation unit 26 of the post-read processing unit 27. The processing error signal (error occurrence status) output from the above is input, and a comparison / determination means for comparing and determining these two types of processing error signals is configured, and the quality is determined based on the difference between the two types of processing error signals. The result is output to the timing generation unit 1, the current switching unit 4, and the voltage switching unit 5.

  According to the determination result output from the comparison / determination unit 29 with the above configuration, the current switching unit 4 and the voltage switching unit 5 are adjusted to determine the current and voltage of the memory interface unit 6 that drives the memory 7, Further, the timing generation unit 1 is adjusted according to the determination results output from the comparison / determination unit 29 and the access status determination unit 31 to determine the memory control timing of the memory control unit 3.

That is, the determination result of the comparison / determination unit 29 is good, that is, the error occurrence state of the processing error in the pre-write processing output from the error signal generation unit 23 and the post-read processing output from the error signal generation unit 26 When it is judged that there is no difference in the error occurrence status of processing error,
c1. In the current switching unit 4, the output current of the memory interface unit 6 (drive current of the memory 7) is adjusted (switched) less than the current level, or adjusted to maintain the current level,
c2. In the voltage switching unit 5, the output voltage of the memory interface unit 6 (drive voltage of the memory 7) is adjusted (switched) to be smaller than the current level or adjusted to maintain the current level,
c3. In the timing generation unit 1, the memory control timing pattern is selected to be slower than the current state or to maintain the current state. Subsequently, when the access status determination unit 31 determines that the access status is rough, the memory control timing pattern is adjusted (set) to be slower than the current status, and the access status determination unit 31 determines that the access status is dense. Sometimes, the memory control timing pattern is adjusted (set) to maintain the current state.

Further, the determination result of the comparison / determination unit 29 is negative, that is, the error occurrence status of the processing error in the pre-write processing output from the error signal generation unit 23 and the processing in the post-read processing output from the error signal generation unit 26 When it is determined that there is a difference in error occurrence status,
d1. In the current switching unit 4, the output current of the memory interface unit 6 (drive current of the memory 7) is adjusted (switched) to be larger than the current state,
d2. In the voltage switching unit 5, the output voltage of the memory interface unit 6 (drive voltage of the memory 7) is adjusted (switched) to be larger than the current state,
d3. The timing generation unit 1 adjusts (sets) the memory control timing pattern so as to be faster than the current state.

  Due to the above action, when the determination result of the comparison / determination unit 29 is good, the drive current of the memory 7 and the drive voltage of the memory 7 are reduced or maintained from the current state, and the pattern of the memory control timing is later than the current state or the current state When maintenance is selected and subsequently the access status is determined to be rough according to the determination result of the access status determination unit 31, the memory control timing pattern is adjusted (set) to be slower than the current status, and the access status is When determining, the memory control timing pattern is adjusted (set) so as to maintain the current state. When the determination result of the comparison / determination unit 29 is negative, the drive current of the memory 7 and the drive voltage of the memory 7 are increased from the current level, and the pattern of the memory control timing is adjusted (set) to be faster than the current level. Therefore, the drive current of the memory 7 and the drive voltage of the memory 7 are optimized while avoiding memory data errors.

  As described above, according to the second embodiment, the difference between the error occurrence status (data processing error) before the memory write and after the memory read is used as the determination condition for the memory data error occurrence. Since the memory drive condition can be adjusted without the memory test circuit (test execution / determination unit 2) as described above, the circuit scale can be further reduced.

  Further, according to the second embodiment, as in the first embodiment, the drive capability of the memory 7 (drive current of the memory 7 and drive voltage of the memory 7) can be optimized while avoiding memory data errors, and consumption Power and unnecessary radiation can be reduced, and the timing generation unit 1 which is a means for adjusting the timing margin of memory control adjusts the memory control timing and switches between multiple timing patterns (patterns 1 to 3). As a result, the timing margin can be adjusted only by the logic circuit, so the circuit scale can be reduced and the current consumption can be reduced. In addition, when the memory 7 is changed or the memory interface status is changed, the adjustment is made immediately. By doing so, memory data errors due to insufficient memory drive capability can be avoided, and the drive capability of the memory 7 can always be maintained optimally. .

  The memory control device according to the present invention has an effect that power consumption and unnecessary radiation can be reduced while avoiding a memory data error, and a semiconductor chip incorporating a memory control and a memory chip such as a DRAM are mounted on a mounting substrate. Useful in systems connected above.

It is a block diagram which shows the structure of the memory control apparatus in Embodiment 1 of this invention. It is a figure which shows the structure of the electric current switching part in the memory control apparatus. It is a block diagram which shows the structure of the voltage converter in the memory control apparatus. 3 is a timing chart showing a memory control timing pattern in the memory control device. It is a block diagram which shows the structure of the memory control apparatus in Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Timing generation part 2 Inspection implementation / determination part 3 Memory control part 4 Current switching part 5 Voltage switching part 6 Memory interface part 7 Memory 8, 9, 10 Buffer 11, 12, 13 Switch 14 Switching type transformation part 15 Pulse adjustment part 16 Pulse converter 17 Switching controller 18 Reference clock signal 19 Write enable signal 20 Address signal 21 Data signal 22 Data processor 23 Error signal generator 24 Pre-write processor 25 Data processor 26 Error signal generator 27 Post-read processor 29 Comparison / determination unit 30 Memory control unit 31 Access status determination unit

Claims (12)

A memory control device including a memory, a memory interface unit that drives the memory, and a memory control unit that controls data writing to and reading from the memory via the memory interface unit,
The memory control unit is provided with a determination unit that performs an inspection of whether or not the write data to the memory and the read data from the memory match to determine whether the data is good or bad,
The memory interface unit is provided with a current switching unit that switches the output current of the memory interface unit to an arbitrary value according to the determination result of the determination unit,
When the determination means determines that the write data to the memory and the read data from the memory coincide with each other, the current switching means switches the output current of the memory interface unit to be less than the current value or maintains the current condition. Thus, when the determination means determines that the data written to the memory and the data read from the memory do not match, the memory control device switches the output current of the memory interface to be larger than the current state. 2. The memory control according to claim 1, wherein the current switching means has means for individually setting the current of each signal line of the memory interface unit when setting the output current of the memory interface unit. apparatus. A memory control device including a memory, a memory interface unit that drives the memory, and a memory control unit that controls data writing to and reading from the memory via the memory interface unit,
The memory control unit is provided with a determination unit that performs an inspection of whether or not the write data to the memory and the read data from the memory match to determine whether the data is good or bad,
The memory interface unit is provided with a voltage switching unit that switches the output voltage of the memory interface unit to an arbitrary value according to the determination result of the determination unit,
The voltage switching means switches the output voltage of the memory interface unit to be lower than the current state or maintains the current state when the determination means determines that the write data to the memory and the read data from the memory match. Thus, when the determination means determines that the data written to the memory and the data read from the memory do not match, the memory control device switches the output voltage of the memory interface unit to be larger than the current value. 4. The memory control device according to claim 3, wherein the voltage switching means has means for individually setting the voltage of each signal line of the memory interface when setting the output voltage of the memory interface section. . A memory control device including a memory, a memory interface unit that drives the memory, and a memory control unit that controls data writing to and reading from the memory via the memory interface unit,
A determination means for checking whether the write data to the memory and the read data from the memory coincide with each other in the memory control section, and a timing generation means for switching the memory control timing to a plurality of patterns And
The timing generation unit sets the memory control timing pattern to be slower than the current state or maintains the current state when the determination unit determines that the write data to the memory and the read data from the memory match. The memory control timing pattern is set to be faster than the current state when the determination means determines that the data written to the memory and the data read from the memory do not match. apparatus. The memory control unit is provided with access status determination means for monitoring the access status of the memory and comparing it with an arbitrary reference value to determine whether the access status is rough or dense,
When the timing generation unit sets the memory control timing pattern to be slower than the current state or sets the current state to maintain the current state, when the access state determination unit determines that the access state is rough, The memory control timing pattern is set so as to be later than the current state, and when the access status determining means determines that the access status is dense, the memory control timing pattern is set to maintain the current status. Item 6. The memory control device according to Item 5. A memory control device including a memory, a memory interface unit that drives the memory, and a memory control unit that controls data writing to and reading from the memory via the memory interface unit,
A pre-write processing means for processing data before writing to the memory and outputting an error occurrence status during the data processing;
Processing post-read data from the memory, and a post-read processing means for outputting an error occurrence status during the data processing,
The memory control unit is provided with comparison determination means for comparing and determining the error occurrence status output from the pre-write processing means and the error occurrence status output from the post-read processing means,
The memory interface unit is provided with a current switching unit that switches the output current of the memory interface unit to an arbitrary value according to the determination result of the comparison determination unit.
When the current switching means determines that there is no difference between the error occurrence status in the data processing before writing to the memory and the error occurrence status in the data processing after reading from the memory in the comparison determination means, After switching from the current output of the memory interface unit to be less than the current value or maintaining the current status, the comparison determination means and the error occurrence status in the data processing before writing to the memory and after reading from the memory A memory control device characterized in that when it is determined that there is a difference in error occurrence status in the data processing, the output current of the memory interface unit is switched to be larger than the current state. 8. The memory control according to claim 7, wherein the current switching unit includes a unit for individually setting a current of each signal line of the memory interface unit when setting an output current of the memory interface unit. apparatus. A memory control device including a memory, a memory interface unit that drives the memory, and a memory control unit that controls data writing to and reading from the memory via the memory interface unit,
A pre-write processing means for processing data before writing to the memory and outputting an error occurrence status during the data processing;
Processing post-read data from the memory, and a post-read processing means for outputting an error occurrence status during the data processing,
The memory control unit is provided with comparison determination means for comparing and determining the error occurrence status output from the pre-write processing means and the error occurrence status output from the post-read processing means,
The memory interface unit is provided with a voltage switching unit that switches the output voltage of the memory interface unit to an arbitrary value according to the determination result of the comparison determination unit.
When the voltage switching means determines that there is no difference between the error occurrence status in the data processing before writing to the memory and the error occurrence status in the data processing after reading from the memory in the comparison determination means, The output voltage of the interface unit is switched to be lower than the current state or the current state is maintained, and the error occurrence state in the data processing before writing to the memory in the comparison judgment unit and the data after reading from the memory A memory control device, characterized in that when it is determined that there is a difference in error occurrence status in processing, the output voltage of the memory interface unit is switched to be larger than the current state. 10. The memory control according to claim 9, wherein the voltage switching unit includes a unit for individually setting a voltage of each signal line of the memory interface unit when setting an output voltage of the memory interface unit. apparatus. A memory control device including a memory, a memory interface unit that drives the memory, and a memory control unit that controls data writing to and reading from the memory via the memory interface unit,
A pre-write processing means for processing data before writing to the memory and outputting an error occurrence status during the data processing;
Processing post-read data from the memory, and a post-read processing means for outputting an error occurrence status during the data processing,
The memory control unit is configured to compare and determine the error occurrence status output from the pre-write processing means and the error occurrence status output from the post-read processing means, and to determine the memory control timing in a plurality of patterns. Provide a timing generation means for switching,
The timing generation means determines that there is no difference between the error occurrence status in the data processing before writing to the memory and the error occurrence status in the data processing after reading from the memory in the comparison determination means. After setting the control timing pattern to be later than the current state or setting to maintain the current state and reading from the memory the error occurrence status in the data processing before writing to the memory in the comparison judgment means A memory control device characterized in that when it is determined that there is a difference in error occurrence status in the data processing, the pattern of the memory control timing is set to be faster than the current state. The memory control unit is provided with access status determination means for monitoring the access status of the memory and comparing it with an arbitrary reference value to determine whether the access status is rough or dense,
When the timing generation unit sets the memory control timing pattern to be slower than the current state or sets the current state to maintain the current state, when the access state determination unit determines that the access state is rough, The memory control timing pattern is set so as to be later than the current state, and when the access status determining means determines that the access status is dense, the memory control timing pattern is set to maintain the current status. Item 12. The memory control device according to Item 11.

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