JP2005283537A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device allowing a functional test of the whole chip including an input circuit, an output circuit and a phase adjustment circuit when performing the functional test of the semiconductor device, allowing easy production of a test pattern, and allowing the functional test having a dense request similar to an operation state of an actual system. <P>SOLUTION: This semiconductor device has test logic inside it, and the input circuit and the output circuit of the semiconductor device has a terminal connected with a signal inputted and outputted by the incorporated test logic. Thereby, the functional test of the semiconductor device including the input circuit and the output circuit can be performed. The semiconductor device is provided with a means adding a skew to the signal outputted by the incorporated test logic to perform the functional test of the phase adjustment circuit. By equipping a means controlling the issued request, the production of the test pattern is facilitated, and the functional test having the dense request can be performed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which test logic is built in the semiconductor device and a function test of the semiconductor device is performed.

  As a general method for testing a semiconductor device, a method called BIST (Built In Self Test) in which a pattern generator and a response compressor are built in the semiconductor device is widely used. However, since the BIST is tested in units of components such as a logic unit and a memory unit mounted on a semiconductor device, the operation of the logic unit due to noise generated by the operation of the memory unit may occur only on the actual system. There is a problem that it is impossible to detect a bad defect. In addition, since the limit operating frequency of each component and the limit operating frequency of the semiconductor device on the actual system are different, there is a problem that overkill (determining a non-defective product as a defective product) or a defective product is shipped. . For this reason, a function test is required to operate the entire chip in the same manner as in the actual system.

  In addition, there is a method in which test pattern data is generated by a device called a tester and input to the semiconductor device, and the data output from the semiconductor device is compared with the expected value obtained from the logic simulation. In this method, a functional test that operates the entire chip can be performed in the same way as the operating state in the actual system. However, due to the increase in the speed and the number of pins of the semiconductor device, a very expensive tester is required. There is a problem of increasing the cost.

  Therefore, as disclosed in Japanese Patent Application Laid-Open No. 2003-208797, a method of performing a function test of a semiconductor device using a built-in test logic is disclosed.

JP 2003-208797 A

  In the above publication, the request generated by the built-in test logic is input to the internal logic to be tested by the selector, and the response from the internal logic is captured from before the output circuit of the semiconductor device. For this reason, the input circuit and the output circuit of the semiconductor device are excluded from the test target, and the influence of noise generated by the input circuit and the output circuit is not reflected in the test. Furthermore, if there is a phase adjustment circuit etc. for canceling the skew of the input signal of the semiconductor device in the preceding stage of the selector that inputs the request, it is also excluded from the test, and there is a problem that the function test of all the chips cannot be performed. is there.

  Furthermore, in a semiconductor device such as a cache chip connected to a processor in a real system, requests that can be issued to the semiconductor device may be limited depending on the type of request being issued and the request tag. . When such a function test of a semiconductor device is performed using the built-in test logic disclosed in the publication, it is complicated to create a test pattern that satisfies the above restrictions. In addition, a NOP instruction for waiting for the end of the request must be described, which reduces the density of requests in the test pattern and makes the test insufficient.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device capable of performing a function test on all chips including an input circuit, an output circuit, and a phase adjustment circuit in a function test of the semiconductor device using the built-in test logic. is there.

  Another object of the present invention is to provide a semiconductor device capable of facilitating the creation of a test pattern and performing a function test with a high demand in the same manner as the operation state in an actual system.

  According to one embodiment of the present invention, a test logic is provided in a semiconductor device, an input terminal for connecting a signal output from the built-in test logic is provided in an input circuit of the semiconductor device, and a built-in test logic is provided in an output circuit of the semiconductor device. By providing an output terminal connected to, a function test of a semiconductor device including an input circuit and an output circuit can be performed.

  Further, a means for adding a skew to the signal output from the built-in test logic is provided, and a function test of the phase adjustment circuit can be performed by connecting to the input terminal of the input circuit.

  In addition, by providing a means to store the requests being issued and a means to control the requests issued by the stored requests being issued, it is possible to simplify the creation of test patterns and perform a dense function test of requests. Is.

  Similar to the operating state of the actual system, it is possible to perform a function test of all the chips with a high request, and it is possible to reduce the possibility of overkill or shipping defective products.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example in which a cache chip 100 is arranged in the center and a tester 101 is provided outside the cache chip 100. A test logic 102 is built in the cache chip 100, a microprogram is read from the tester 101, and the test logic 102 performs processing to perform a function test. Here, before describing the function test of the cache chip 100, the operation of the cache chip 100 in the actual system will be described.

  FIG. 2 is a configuration diagram of an actual system. The cache chip 100 is connected to the processor 200 and the main memory controller 201. In a normal operation in the real system, the cache chip 100 receives the request 1 output from the processor 200 and performs the following two operations.

  (I) Upon receiving request 1 from the processor 200, the cache chip 100 processes the request 1. Next, the cache chip 100 transfers the request 1 as the request 2 to the main memory controller 201. The main memory controller 201 receives the request 2 and processes it, and then transmits a response 2 to the cache chip 100. The cache chip 100 transmits the response 2 as the response 1 to the processor 200.

  (Ii) In response to the request 1 from the processor 200, the cache chip 100 processes the request 1. Thereafter, the cache chip 100 transmits response 1 to the processor 200.

  Here, the request 1 is the Address / Control / Data 103 shown in FIG. 1, and the request 2 is the Address / Control / Data 104 shown in FIG. Response 1 is Control / Data 105, and Response 2 is Control / Data 106.

  In an actual system, before performing the normal operation, in order to ensure communication between chips, a phase adjustment circuit built in each chip is operated to adjust the phase of a signal between the chips. The phase adjustment circuit adjusts the delay of each bit of the signal in order to cancel the skew of the signal transmitted from another chip so that the signal can be received stably.

  FIG. 3 shows the flow of phase adjustment processing in the actual system. First, in the phase adjustment 300 between the processor and the cache chip, the processor 200 transmits a signal of a specific pattern to the cache chip 100 and adjusts the skew of the signal received by the processor side phase adjustment circuit 107 in the cache chip 100. . In the next phase adjustment 301 between the cache chip and the processor, the processor-side phase adjustment circuit 108 in the cache chip 100 generates a specific pattern signal and transmits it to the processor 200, whereby the phase adjustment in the processor 200 is performed. The skew of the signal is adjusted by the circuit. Similarly, the phase adjustment 302 between the cache chip and the main memory controller and the phase adjustment 303 between the main memory controller and the cache chip are sequentially performed, and then the normal operation is started.

  Next, a normal operation test of the cache chip 100 will be described with reference to FIG. In the normal operation test, a processor-side phase adjustment test and a main memory controller-side phase adjustment test are performed, and then a normal operation test is performed.

  First, the tester 101 transmits a processor-side phase adjustment test microprogram to the microprogram storage circuit 109 in the built-in test logic 102. The microprogram storage circuit is provided with a register for switching the test mode, and is switched to the processor side phase adjustment test mode by the transferred microprogram.

  The execution control circuit 110 instructs the request generation circuit 111 to output a specific pattern. The specific pattern output from the request generation circuit 111 is input to the variable delay layer 112.

  The variable delay layer 112 is a circuit for simulating the skew between the processor and the cache chip on the real system, and adds a delay to each bit of the signal from the request generation circuit 111. The setting of the delay value of each bit is specified in the microprogram, and the execution control circuit 110 interprets the setting value and sets it. The output of the variable delay layer 112 is input to the input circuit 113.

  The input circuit 113 is provided with a selector for selecting the output of the Address / Control / Data 103 and the variable delay 112 from the outside of the chip, and the output signal of the variable delay 112 to which the skew is added by this selector is a processor-side phase adjustment circuit. Is input.

  Further, the execution control circuit 110 instructs the processor-side phase adjustment circuit 107 to start the phase adjustment operation, and the phase adjustment 300 between the processor and the cache chip is executed. The execution control circuit 110 monitors the completion of the phase adjustment operation of the processor side phase adjustment circuit 107, and when the completion is detected, instructs the request generation circuit 111 to stop outputting the specific pattern. Further, the test result determination circuit 114 is instructed to read the phase adjustment result data held in the processor-side phase adjustment circuit 107, and the test result determination circuit 114 reads the phase adjustment result from the read phase adjustment result data. Determine if the operation was performed correctly.

  Next, the execution control circuit 110 instructs the processor-side phase adjustment circuit 107 to output a specific pattern. The specific pattern output from the processor-side phase adjustment circuit 107 is input to the test result determination circuit 114 through the output circuit 115, and the test result determination circuit 114 determines whether the specific pattern is correctly output from the processor-side phase adjustment circuit 107.

  Based on the determination result of the phase adjustment operation of the processor side phase adjustment circuit 107 and the determination result of the specific pattern, the test result determination circuit 114 determines the PASS / FAIL of the test and outputs the result to the external tester 101.

  After the PASS of the processor side phase adjustment test is detected by the tester 101, the main memory controller side phase adjustment test is subsequently performed in the same manner as the processor side phase adjustment test. That is, the tester 101 transmits a memory controller-side phase adjustment test microprogram to the microprogram storage circuit 109 in the built-in test logic 102 to switch to the memory controller-side phase adjustment test mode. The execution control circuit 110 instructs the response generation circuit 116 to output a specific pattern, and the output specific pattern is input to the variable delay layer 117. The specific pattern to which the skew is added by the variable delay layer 117 is input to the input circuit 118, the phase is adjusted by the main memory controller side phase adjustment circuit 108, and the result data is read by the test result determination circuit 114. Further, the test of the specific pattern output of the main memory controller side phase adjustment circuit 108 is also performed using the output circuit 119 in the same manner as the processor side phase adjustment test.

  As described above, a signal from the built-in test logic 102 is input to the input circuits 113 and 118, an internal signal of the semiconductor device is output to the built-in test logic 102 in the output circuits 115 and 119, and the variable delay layers 112 and 117 are output to the built-in test logic 102. By incorporating, it becomes possible to perform a function test of the phase adjustment circuit.

  Next, a normal operation test of the cache chip 100 will be described. The delay settings of the variable delay layers 112 and 117 in the normal operation test, the processor-side phase adjustment circuit 107, and the main memory controller-side phase adjustment circuit 108 are performed while maintaining the state at the end of the phase adjustment test. That is, a normal operation test is performed on a request input from the built-in test logic 102 to each input circuit with a skew similar to that in the actual system and normal operation being added.

  First, the tester 101 transmits a normal operation test microprogram to the microprogram storage circuit 109 to switch to the normal operation test mode. The execution control circuit 110 executes the microprogram stored in the microprogram storage circuit 109 and instructs the request generation circuit 111 to output a request and data. Here, the request generated by the request generation circuit corresponds to request 1 transmitted from the processor 200 to the cache chip 100 in the real system.

  FIG. 4 is a configuration diagram of the request generation circuit 111. The request generation circuit 111 includes a request issuance determination circuit 400, a request storage circuit 401 that stores the type of request being issued and tag information, a specific pattern generation circuit 402 that generates a specific pattern during a phase adjustment test, and a normal during a phase adjustment test The selector 403 switches the request output 407 during the operation test.

  When a normal operation test is executed, the request issuance determination circuit 400 reads out the type of request being issued and tag information from the request storage circuit 401 according to a request issuance instruction 404 from the execution control circuit 110, and determines whether the request can be issued. . If the request can be issued, the request is issued and the type of the issued request and the tag information are written in the request storage circuit 401. If the request cannot be issued, a NOP instruction is issued while the request being held is erased from the request storage circuit 401, and the request issuance stop signal is sent to the execution control circuit 110. 406 is output, and the output of the new request issue command 404 in the execution control circuit 110 is stopped. When the request processing completion signal 405 is input from the response generation circuit 116, the request issuance determination circuit 400 deletes the information of the completed request from the request storage circuit.

  The request output from the request generation circuit 111 is input to the normal logic through the variable delay 112, the input I / O 113, and the processor side phase adjustment circuit 107, and is processed.

  In addition, Address / Control / Data 104 and Control / Data 105, which are output signals of the cache chip 100, are output to the response generation circuit 116 and the test result determination circuit 114 through the output circuit 119 and the output circuit 115, respectively.

  The response generation circuit 116 generates and outputs a response equivalent to the response 2 that is the output of the main memory controller 201 in the actual system, in response to the signal from the output circuit 119. The output response is input to the normal logic through the input circuit 118 and the main memory controller side phase adjustment circuit 108 and processed. Further, in response to a signal corresponding to the response 1 of the cache chip 100 in the real system from the output circuit 115, the response generation circuit 116 outputs a request processing completion signal 405 of the request to the request generation circuit 111.

  Further, the test result determination circuit 114 checks whether the responses of the cache chip 100 output from the output circuits 115 and 119 are correct, and outputs the result to the external tester 101.

  As described above, the request generation circuit 111 can control the issuance of the request so that the processor 200 controls the issuance of the request 1 in the real system, and the instruction waiting for the request issuance from the microprogram stored in the microprogram storage circuit 109. Can be omitted, and a normal operation test with high demand can be performed.

It is a block diagram which shows the Example of the semiconductor device of this invention. FIG. 2 is a configuration diagram when the semiconductor device shown in FIG. 1 operates in an actual system. It is a figure which shows the flow of the process of the phase adjustment in a real system. It is a block diagram of a request generation circuit in the built-in test logic.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Cache chip, 101 ... Tester, 102 ... Built-in test logic, 107 ... Processor side phase adjustment circuit, 108 ... Memory controller side phase adjustment circuit, 110 ... Execution control circuit, 111 ... Request generation circuit, 112 ... Variable delayer, 113 ... Input circuit, 114 ... Test result determination circuit, 115 ... Output circuit, 116 ... Response generation circuit, 117 ... Variable delay, 118 ... Input circuit, 119 ... Output circuit

Claims (3)

  A semiconductor device includes a built-in test logic in the semiconductor device, an input circuit of the semiconductor device having an input terminal for connecting a signal output from the built-in test logic, and further connected to the built-in test logic in an output circuit of the semiconductor device A semiconductor device characterized in that a functional test of a semiconductor device including an input circuit and an output circuit is performed by providing an output terminal.   An additional means for adding a skew to a request and data output from the built-in test logic is provided, and the additional means is connected to an input terminal of the input circuit to perform a function test of the phase adjustment circuit. Item 14. A semiconductor device according to Item 1. A semiconductor device comprising: a built-in test logic in the semiconductor device; and means for storing a request being issued at the time of a function test; and means for controlling a request issued by the stored request being issued apparatus.

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