JP2009079914A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the scale of mounting a BIST circuit. <P>SOLUTION: This semiconductor integrated circuit includes: a plurality of test target circuits having the same function; and a test circuit for testing the test target circuits. The test circuit comprises: an input signal generation part for generating an input signal to be inputted in common into the plurality of test target circuits; and a comparison part for comparing output signals corresponding to input signals outputted from the plurality of test target circuits, respectively, and determining the quality, based on a comparison result. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit.

A logic circuit mounted on a semiconductor integrated circuit may cause some failure during manufacturing, handling, mounting process, operation, etc., and may not operate normally.
Conventionally, as a failure detection method for a logic circuit, a method using a test program for operating a circuit and comparing it with an expected value is used. Secondly, a method in which a BIST (Built-In Self Test) circuit that generates an expected value is provided in advance in a semiconductor integrated circuit is used (see, for example, Patent Document 1). FIG. 4 is a block diagram showing a functional configuration of a conventional BIST circuit. The BIST circuit 100 includes an input signal generation unit 101, an expected value comparison unit 102, and an expected value generation unit 103. Hereinafter, the operation of the BIST circuit 100 will be described. When a test start signal is input to the input signal generation unit 101 from the outside, the input signal generation unit 101 generates an input signal and inputs the input signal to the circuit block 200 that is a logic circuit to be tested and the expected value generation unit 103. To do. The expected value generation unit 103 generates an expected value of an output signal to be output from the circuit block 200 with respect to the input signal, and inputs the expected value to the expected value comparison unit 102. The expected value comparison unit 102 compares whether or not the expected value input from the expected value generation unit 103 and the value of the output signal input from the circuit block 200 are the same. If there is, it is determined that the circuit block 200 is operating normally, and if it is not the same, it is determined that the circuit block 200 has failed.
JP 2003-332443 A

However, in the first method described above, in order to inspect all logic of the logic circuit to be tested, a huge length of test is necessary, which is difficult to perform at the time of product manufacture. is there. In the second method, an algorithm for generating an expected value by the expected value generator 103 is complicated, and it is necessary to mount a relatively large BIST circuit in order to realize this complex algorithm. There is a problem that a BIST circuit unrelated to the actual operation is mounted and the circuit area becomes large.
The present invention has been made in view of the above points, and an object thereof is to reduce the scale of mounting a BIST circuit in a semiconductor integrated circuit. Another object is to shorten the test time and perform an efficient test.

  The present invention has been made to solve the above problems, and one embodiment of the present invention includes a plurality of test target circuits having the same function, and a test circuit for testing the test target circuit. The test circuit includes an input signal generation unit that generates an input signal to be input in common to the plurality of test target circuits, and the input signal output from the plurality of test target circuits. A comparison unit that compares output signals with respect to each other and makes a pass / fail judgment based on the comparison result.

  According to the present invention, the same input signal is input to a plurality of circuits to be tested, and the output signals are compared to test the circuit without mounting the expected value generation unit. This makes it possible to reduce the scale for mounting the BIST circuit. In addition, by providing the BIST circuit, it is not necessary to perform an enormous length test at the time of product manufacture, and the test time can be shortened and an efficient test can be performed.

  Another embodiment of the present invention is a semiconductor integrated circuit including a test target circuit having an input and an output, and a test circuit for testing the test target circuit, wherein the test circuit is the test target An input signal generation unit for generating an input signal for input to the circuit, an input signal delay unit for delaying the input signal generated by the input signal generation unit, an output signal output from the circuit under test, and A comparison unit that compares the output from the input signal delay unit and determines pass / fail based on the comparison result, and the circuit under test includes an output register that holds a value to be output, and an input value And an input register that holds a predetermined value during normal operation, and a value of the input register is copied to the output register during a test. Is a semiconductor integrated circuit to be.

  According to the present invention, the circuit is tested without mounting the expected value generator by comparing the input signal generated by the input signal generator with the output signal generated by the test target circuit. As a result, the scale for mounting the BIST circuit can be reduced. In addition, by providing the BIST circuit, it is not necessary to perform an enormous length test at the time of product manufacture, and the test time can be shortened and an efficient test can be performed.

  According to another aspect of the present invention, the semiconductor integrated circuit includes a plurality of the test target circuits, and the plurality of test target circuits are configured such that an output of the previous test target circuit is an input of the next test target circuit. Are connected in series so that the input signal generated by the input signal generator is input to the test target circuit in the forefront stage, and is output from the test target circuit in the last stage. Are connected to input to the comparison unit.

  According to the present invention, a plurality of test target circuits can be tested at a time by connecting a plurality of test targets in series.

  According to the present invention, it is possible to reduce the scale of mounting a BIST circuit in a semiconductor integrated circuit. In addition, by providing a BIST circuit, it is not necessary to perform an enormous length test at the time of product manufacture, and the test time can be shortened and an efficient test can be performed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a functional configuration of a semiconductor integrated circuit 1 including a BIST circuit 10 according to the first embodiment of the present invention.
The circuit block 50-A and the circuit block 50-B built in the semiconductor integrated circuit 1 are logic circuits having the same configuration, for example, a circuit including a plurality of multipliers and adders.

The BIST circuit 10 is a circuit that tests the functions of the circuit block 50-A (test target circuit) and the circuit block 50-B (test target circuit). The BIST circuit 10 is provided in the semiconductor integrated circuit 1 and includes the input signal generator 11 and The expected value comparison unit 12 is configured. The BIST circuit 10 is different from the conventional BIST circuit 100 in that the expected value generator 103 is not included. The operation of the BIST circuit 10 having the above configuration will be described below.
When a test start signal is input from the outside, the input signal generator 11 inputs the input signal to the circuit block 50-A and the circuit block 50-B at the same time. This input signal is a signal for operating the circuit block 50-A and the circuit block 50-B as usual, and information for generating the input signal is stored in the input signal generation unit 11 in advance. The output signals of the circuit block 50-A and the circuit block 50-B corresponding to this input signal are input to the expected value comparison unit 12.
The expected value comparison unit 12 compares whether the output signal output from the circuit block 50-A is the same as the output signal output from the circuit block 50-B. 50-A and circuit block 50-B are determined to be operating normally, and if they are not the same, it is determined that either circuit block 50-A or circuit block 50-B has failed. The determination result is notified to a tester that performs a test through a CPU (not shown).

  As described above, according to the present embodiment, the same input signal is input to the logic circuit having the same function, and the output signal is compared to test the logic circuit without mounting the expected value generation unit 103. Do. This makes it possible to reduce the scale for mounting the BIST circuit. In addition, by providing the BIST circuit, it is not necessary to perform an enormous length test at the time of product manufacture, and the test time can be shortened and an efficient test can be performed.

  In this embodiment, the output signals of two logic circuits are compared, but the output signals of three or more logic circuits may be compared.

  In the present embodiment, the test for one input signal has been described. However, a plurality of input signal patterns may be sequentially generated to test each input signal pattern. At this time, a signal indicating the switching timing of the input signal is appropriately transmitted to the expected value comparison unit 12 through a signal line (not shown).

  In the present embodiment, the case where the circuit to be tested is a logic circuit is shown, but the circuit may be performed on another circuit. For example, a case where the test target circuit is a sequential circuit including a register will be described. A sequential circuit having two identical configurations to be tested has a means for initializing a register.

When a test start signal is input from the outside, the input signal generator 11 inputs a signal for initializing the register of the sequential circuit to the two sequential circuits simultaneously. In response to the input of the signal, the sequential circuit initializes the register.
When the input signal generator 11 inputs an input signal to the sequential circuit, a plurality of input signal patterns are sequentially generated and input to the two sequential circuits in synchronization with the clock signal. The output signals of the two sequential circuits for each input signal are sequentially input to the expected value comparison unit 12.
The expected value comparison unit 12 compares whether or not the output signals of the two sequential circuits with respect to each input signal are the same in synchronization with the clock signal. If it is determined that it is operating, and if it is not the same, it is determined that one of the two sequential circuits has failed. At this time, a signal indicating the switching timing of the input signal is appropriately transmitted to the expected value comparison unit 12 through a signal line (not shown).
Since other operations are the same as those of the logic circuit, description thereof is omitted.

Next explained is a semiconductor integrated circuit comprising a BIST circuit according to the second embodiment of the invention.
FIG. 2 is a block diagram showing a functional configuration of a circuit block 60-C (test target circuit) and a circuit block 60-D (test target circuit) to be tested in the present embodiment. The circuit block 60-C and the circuit block 60-D built in the semiconductor integrated circuit 1 are logic circuits having the same configuration with a function of going and returning, and a control unit 61, a register 62 (output register), And a register 63 (input register). In this figure, the BIST circuit is omitted.

The normal operation of the circuit block 60-C having the above configuration will be described. The circuit block 60-C performs the following normal operation when the input test signal is OFF. The control unit 61 controls the overall processing operation of the circuit block 60-C. When there is an input signal from the CPU 80 to the circuit block 60-C, the control unit 61 temporarily holds a value corresponding to the input signal in the register 62, and the CPU 80 designates that there is an input signal. Notify external output destination. The designated output destination circuit or device acquires the value held by the register 62 in response to the notification.
When the circuit block 60-C receives an input signal from an external circuit or device other than the CPU 80, the control unit 61 temporarily holds a value corresponding to the input signal in the register 63, and the input signal is The CPU 80 is notified of the fact. The CPU 80 receives the notification and acquires the value held in the register 63. In normal operation, a signal line (indicated by a broken line in FIG. 2) for directly passing data from the register 63 to the register 62 is not used.
The circuit block 60-D operates in the same manner as the circuit block 60-C.

  FIG. 3 is a block diagram showing a functional configuration of the semiconductor integrated circuit 1 including the BIST circuit 20 according to the present embodiment. Hereinafter, the operation of the circuit during the test will be described with reference to this figure. As illustrated, the semiconductor integrated circuit 1 includes a circuit block 60 -C and a circuit block 60 -D, and a BIST circuit 20. In the figure, the CPU 80 is omitted.

The circuit block 60-C and the circuit block 60-D perform the following test operation when the input test signal is ON.
When an input signal is input to the circuit block 60 -C from the BIST circuit 20, the control unit 61 temporarily stores a value corresponding to the input signal in the register 63, and stores the stored value from the register 63 to the register 62. make a copy. Thereafter, the controller 61 inputs the value copied and held in the register 62 as an output signal to the circuit block 60-D.
The circuit block 60 -D inputs an output signal to the BIST circuit 20 when an input signal is input from the circuit block 60 -C. Other operations are the same as those of the circuit block 60-C.
Since it operates in this way, the output signals of the circuit block 60-C and the circuit block 60-D are the same as the input signals that have been input during the test.

  The BIST circuit 20 is a circuit that tests the functions of the circuit block 60-C and the circuit block 60-D. The BIST circuit 20 is provided in the semiconductor integrated circuit 1, and includes an input signal generation unit 21, an expected value comparison unit 22, and an input signal. And a delay unit 23. The BIST circuit 20 is different from the conventional BIST circuit 100 in that the input signal delay unit 24 is newly provided and the expected value generation unit 103 is not included.

The input signal generation unit 21 receives an external test start signal, generates an input signal, and inputs this input signal to the circuit block 60 -C and the input signal delay unit 24. At that time, the input signal generator 21 inputs the test signal to the circuit block 60-C and the circuit block 60-D. This input signal is a signal for operating the circuit block 60-C and the circuit block 60-D as usual, and information for generating the input signal is stored in the input signal generation unit 21 in advance.
The input signal delay unit 24 generates a delay for the time until the output signal of the circuit block 60 -D is input to the expected value comparison unit 22, and inputs the input signal to the expected value comparison unit 22. .
The expected value comparison unit 22 compares whether or not the input signal input from the input signal delay unit 24 and the output signal input from the circuit block 60-D are the same. It is determined that 60-C and circuit block 60-D are operating normally, and if they are not the same, it is determined that one of circuit block 60-C or circuit block 60-D has failed. The result of the determination is notified to a tester performing a test through the CPU 80 or the like.

  Next, an example of the operation in FIG. 3 will be described. When the test start signal is input to the BIST circuit 20, the input signal is generated by the input signal generation unit 21 and input to the circuit block 60 -C and the input signal delay unit 24. At that time, a test signal is input to the circuit block 60-C and the circuit block 60-D. In response to the input signal and the test signal, an output signal corresponding to the input signal is input from the circuit block 60-C to the circuit block 60-D. This output signal is used as an input signal, and an output signal corresponding to the input signal is input from the circuit block 60 -D to the BIST circuit 20. The input signal input from the expected value delay unit 24 and the output signal input from the circuit block 60-D are compared in the expected value comparison unit 22 to determine whether they are the same. The circuit block 60-C and the circuit block 60-D are determined to be operating normally, and if they are not the same, it is determined that either the circuit block 60-C or the circuit block 60-D has failed. . The determination result is notified to the tester that performs the test through the CPU 80 or the like.

  Thus, according to the present embodiment, the input signal generated by the input signal generation unit 21 is compared with the output signal of the circuit block 60-D that receives the output signal of the circuit block 60-C. Thus, the circuit is tested without mounting the expected value generation unit 103. As a result, the scale for mounting the BIST circuit can be reduced. In addition, by providing the BIST circuit, it is not necessary to perform an enormous length test at the time of product manufacture, and the test time can be shortened and an efficient test can be performed.

  In the present embodiment, the two circuit blocks of the circuit block 60-C and the circuit block 60-D are connected in series. However, a test may be performed by connecting three or more circuit blocks in series. Alternatively, the test may be performed with one circuit block without connecting the circuit blocks. In any case, as in the present embodiment, the input signal generated by the input signal generator 21 is assumed to be connected in series so that the output of the previous test target circuit becomes the input of the next test target circuit. Are input so as to be input to the test target circuit in the foremost stage, and the output from the test target circuit in the last stage is connected to be input to the expected value comparison unit 22.

  The embodiments of the present invention have been described in detail above with reference to the drawings. However, the specific configuration is not limited to the above-described one, and various design changes and the like can be made without departing from the scope of the present invention. Is possible.

1 is a block diagram showing a functional configuration of a semiconductor integrated circuit including a BIST circuit according to a first embodiment. It is a block diagram which shows the functional structure of the circuit block used as the test object by 2nd embodiment. It is a block diagram which shows the functional structure of the semiconductor integrated circuit provided with the BIST circuit by 2nd embodiment. It is the block diagram which showed the functional structure of the conventional BIST circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 10 ... BIST circuit 11 ... Input signal generation part 12 ... Expected value comparison part 20 ... BIST circuit 21 ... Input signal generation part 22 ... Expected value comparison part 24 ... Input signal delay part 50-A, 50-B ... Circuit block (test target circuit) 60-C, 60-D ... Circuit block (test target circuit) 61 ... Control unit 62 ... Register (output register) 63 ... Register (input register) 80 ... CPU

Claims (3)

Multiple circuits under test with the same function,
A test circuit for testing the circuit under test;
A semiconductor integrated circuit comprising:
The test circuit includes:
An input signal generation unit for generating an input signal for common input to the plurality of test target circuits;
A comparison unit that compares output signals with respect to the input signals output from the plurality of test target circuits, and performs pass / fail determination based on a comparison result;
A semiconductor integrated circuit comprising: A circuit under test comprising an input and an output; and
A test circuit for testing the circuit under test;
A semiconductor integrated circuit comprising:
The test circuit includes:
An input signal generator for generating an input signal for input to the circuit under test;
An input signal delay unit that delays the input signal generated by the input signal generation unit;
A comparison unit that compares the output signal output from the circuit under test with the output from the input signal delay unit, and performs pass / fail determination based on the comparison result;
With
The circuit under test includes an output register for holding a value to be output and an input register for holding an input value, and performs a predetermined operation at a normal time, and sets the value of the input register at a test time. Copy to output register,
A semiconductor integrated circuit. A plurality of the test target circuits are provided,
The plurality of test target circuits are connected in series so that the output of the previous test target circuit becomes the input of the next test target circuit,
The input signal generated by the input signal generation unit is connected to be input to the test target circuit in the forefront stage,
The output from the circuit under test at the last stage is connected to be input to the comparison unit,
The semiconductor integrated circuit according to claim 2.

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