JP4806537B2 - Test circuit and mask control circuit - Google Patents

Description

  The present invention relates to a mask circuit, a mask control circuit, and a mask method, and more particularly to an improvement in a failure detection rate when a timing false path exists in the circuit.

  The scan method is the mainstream in the DFT (Design For Test) technology of the current LSI (Large Scale Integration), and the effect has shown great results in the fault detection rate for stuck-at faults. However, with the increase in LSI operating frequency or the complexity of LSI, delay faults occupy a large number of product failure factors, and it is impossible to select defects in a shipping test with only stuck-at faults.

  On the other hand, in recent years, the scan pattern length tends to increase as LSIs become larger due to the progress of miniaturization. However, there is a limit to the scan pattern memory of the existing LSI tester ATE (Automatic Test Equipment). In addition, since the increase in scan pattern length leads to an increase in test time, the necessity for compressing the scan pattern is increasing.

  For the above problems, Logic BIST (Built-In Self Test) technology using a scanning method is applied, an internal pattern generation circuit is included, and a delay fault test at the actual operating frequency using a PLL (Phase locked loop) (AtSpeed test).

  As LSIs become larger and more complex, LSIs having paths (timing false paths) that do not need to operate in one cycle of the clock, such as asynchronous transfer paths and paths that operate in a plurality of clock cycles, are increasing. When performing such an LSI delay fault test, it is necessary to exclude the timing false path from the delay fault detection target. In order to always set the signal output from the timing false pass during testing to “0”, a mask processing gate is provided.

  An example of performing a delay fault test by masking the timing false path during the delay fault test will be described with reference to FIG. When the path A and path B shown in FIG. 8 are timing false paths, the data input of the flip-flop (hereinafter referred to as F / F) 1 is performed in order to exclude the path A and path B from the delay fault object in the LogicBIST AtSpeed test. The mask circuit 2 is inserted immediately before, and a LogicBIST_Mode signal is input as a control signal input to the mask circuit 2.

  The LogicBIST_Mode signal is controlled by the LogicBIST Controller shown in FIG. 9, and “1” is always input from the start of LogicBIST as shown in FIG. That is, during the LogicBIST AtSpeed test, the data input of F / F1 is always fixed to “0”, and the path A and path B are excluded from the delay fault detection targets. Further, as shown in FIG. 11, since the insertion of the mask circuit 2 is performed as a circuit measure before the test pattern creation process, the F / F1 data input of the shipment test pattern is always fixed to “0”. Test patterns are generated.

  FIG. 12 is a circuit diagram in which a scan path D is added to FIG. A scanning operation will be described with reference to FIG. In the scan operation, by setting the Scan Enable signal to “1”, the scan path D is validated, and values that make the UserLogic included in the path C easier to be activated are F / F4, F / F5, A fault is detected by sequentially inputting the shift to F / F1 and F / F3, setting Scan Enable to “0” after the shift operation is completed, and changing the UserLogic portion.

  However, by masking the path A and the path B as described above, the data input value of the F / F 1 is always fixed to “0” at the time of capture. As a result, the activation rate (“0”, “1” change rate) in the path C decreases. This is because fall (transition from “1” to “0”) can occur in UserLogic included in the path C, but rise (transition from “0” to “1”) cannot occur. In this way, since the input at the time of capture is a fixed value, only the transition from the value set in F / F1 to the other logical value can be detected during the shift operation, so that the delay fault detection rate in path C decreases. End up.

  The mechanism for reducing the activation rate will be described in more detail with reference to FIGS. FIG. 13 shows that when performing an AtSpeed test between F / F6 and F / F7, the timing false path with F / F6 as the end point is excluded from the delay fault detection target, and is masked immediately before data input to F / F6. An example of a circuit in which the circuit 8 is inserted is shown, and FIG. 14 is a timing chart of an AtSpeed test in the case of the circuit configuration of FIG.

  As shown in FIGS. 13 and 14, with Scan Enable set to “1”, “1” is latched to F / F6 and “0” is latched to F / F7 by the shift operation. Then, Scan Enable is set to “0” and the capture period starts. By switching Scan Enable, “0”, which is an output from the mask circuit 8, is input to the F / F 6. In this case, the output of the F / F 6 changes from “1” to “0” at the first clock of the AtSpeed test, and the outputs of the gates 9 and 10 also change from “1” to “0” accordingly. Further, the input to the F / F 6 remains “0” due to the output of the mask circuit 8. Accordingly, since the output of F / F 6 remains “0” and does not change even in the second clock, the outputs of gate 9 and gate 10 do not change.

  In this way, in the gates 9 and 10, the fall (the transition from “1” to “0”) can be detected, but the rise (the transition from “0” to “1”) can be detected. Therefore, it can be said that the delay failure detection effect of the gates 9 and 10 is 50%. That is, it can be seen that the activation rate (“0”, “1” change rate) between F / F 6 and F / F 7 is reduced due to the influence of the mask circuit 8.

In order to detect the rise (transition from “0” to “1”) that could not be detected, it is necessary to prepare a normal scan pattern with LogicBISTMode = 0, but in this case, an external clock must be input. As a result, the internal PLL clock cannot be used and testing at the actual operating frequency is not possible. Furthermore, it leads to an increase in scan pattern. The activation rate (“0”, “1” rate of change) decrease when there are many mask circuit insertion locations due to such false paths inside the LSI greatly affects the delay failure detection rate of the entire LSI. It is impossible to create a test pattern that maintains a sufficient delay fault detection rate as a test.
Incidentally, as a related technique, there is a technique disclosed in Patent Document 1.
JP 2002-148309 A

  As described above, when there is a conventional mask circuit, the scan pattern length increases and it is difficult to test at the actual operating frequency.

  A test circuit according to the present invention is a test circuit for testing a user circuit by a scan path, and is provided in a stage subsequent to a failure detection target path included in the user circuit, and masks the failure detection target path. A mask circuit, and a failure detection target path and a subsequent element located at a subsequent stage of the mask circuit, the mask circuit sets a first or second logical value for the subsequent element, The succeeding element outputs an arbitrary signal that rises or falls according to the first clock based on a set logical value.

  On the other hand, the mask control circuit according to the present invention is a mask control circuit for controlling a mask circuit that masks a failure detection target path included in the user circuit when the user circuit is tested by a scan path, The mask circuit is controlled so as to mask the non-failure detection target path in accordance with at least a rising edge of the first clock among clock signals input to the scan path during the capture period of the test.

  The masking method according to the present invention is a masking method for masking a non-failure detection target path included in the user circuit when the user circuit is tested by a scan path, and is provided at a subsequent stage of the failure detection non-target path. A step of inputting an initial value for the test to a succeeding element located; a step of inputting a clock signal to the succeeding element to transition an output signal of the succeeding element; and a failure after the output signal of the succeeding element transitions Masking between the non-detection target path and the subsequent element.

  According to the present invention, it is possible to reduce the scan pattern length and perform the test only at the actual operating frequency in the LSI failure detection test using the scanning method.

  Hereinafter, embodiments to which the present invention can be applied will be described. The following description is to describe the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description is omitted and simplified as appropriate. Moreover, those skilled in the art can easily change, add, and convert each element of the following embodiments within the scope of the present invention.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a circuit to which the failure detection method according to this embodiment is applied. The circuit shown in FIG. 1 is provided on a path F that is a delay fault detection target, a timing false path E that is not a delay fault detection target, an F / F 101 provided on the input side of the path F, and an output side of the path F. F / F 102, F / F 103 provided on the input side of the timing false path E, a mask circuit 104 provided between the timing false path E and the F / F 101, and generation of a mask control signal for controlling the mask circuit 104 Part 200. The mask control signal generation unit 200 includes an F / F 201 and a gate 202, and the output of the F / F 201 is input to the gate 202.

  The F / Fs 101, 102, and 103 and the F / F 201 operate with the clock of the CK1 signal. The F / Fs 101, 102, and 103 are switched between a scan path D to which a Scan In signal is input and a user path (timing false path E, path F, etc.) to which a UserLogic In signal is input. The switching operation is controlled by a Scan Enable signal that distinguishes between a capture period and a shift period in a scan test. In other words, the Scan Enable signal is a capture signal. The Scan Enable signal is also input to the F / F 201. The gate 202 outputs a logical product of an inverted signal of the output of the F / F 201 (Scan Enable signal) and a Test Mode signal indicating that the circuit is being tested. The output of the gate 202 is used as an AtSpeed Mask_Mode signal for controlling the mask circuit 104. The mask circuit 104 is controlled by an inverted signal of the AtSpeed Mask_Mode signal.

  In FIG. 1, the timing false path E and path F are user paths, the UserLogic In signal is input, and the operation is performed based on the CK1 signal input to the F / Fs 101, 102, and 103. The scan path D is a path for inputting a signal to be latched to each F / F while sequentially shifting when the circuit is tested. The user path and the scan path D are selected by a Scan Enable signal. That is, when the Scan Enable signal is “1”, the scan path D is selected, and when the Scan Enable signal is “0”, the user path is selected.

  The mask circuit 104 is a mask circuit for excluding the timing false path E from the delay fault detection target. Since the Test Mode signal is “0” during normal operation, the AtSpeed Mask_Mode signal is always “0”, and the mask circuit Since 104 outputs the signal of the timing false path E as it is, the mask circuit 104 has no influence on the circuit during normal operation. During the test operation, the Test Mode signal becomes “1”, and the AtSpeed Mask_Mode signal is determined based on the Scan Enable signal and the CK1 signal. When the AtSpeed Mask_Mode signal is “1”, the output of the mask circuit 104 is always “0”, and the timing false path E is masked.

  The mask control signal generation unit 200 is provided between the LogicBIST controller and the scan target circuit as shown in FIG. An AtSpeed Mask_Mode signal is generated based on the Scan Enable signal and LogicBIST_Mode signal generated by the LogicBIST controller, and input to the scan target circuit, in this embodiment, the mask circuit 104. In FIG. 1, the LogicBIST_Mode signal is indicated as a Test Mode signal.

  FIG. 3 is a flowchart showing the flow of the LSI shipment test. Conventionally, a test pattern is created (S404) after inserting a BIST circuit (S401), specifying a False path, and inserting a mask circuit (S402). In the present embodiment, after specifying the False path, the mask control signal generation unit 200 is inserted (S403), and then the test pattern is created (S404). Thereafter, a shipping test is performed (S405).

  FIG. 4 is a timing chart showing the operation of the circuit shown in FIG. In the shift 1 period shown in FIGS. 4A and 4B, the Scan Enable signal is “1”, and the scan path D is selected as the input of the F / Fs 101, 102, and 103. A Scan In signal is input to each F / F using the scan path D, and an initial value is set. At this time, since the Scan Enable signal is set to “1” and the shift operation is performed according to the clock of CK1, the output of the F / F 201 is also set to “1” and the AtSpeed Mask_Mode signal is set to “0”.

  FIG. 4 shows only the final clock in the shift 1 period. At the time of the last clock of the shift operation in the shift 1 period, the output of the F / F 201 is “1” and the AtSpeed Mask_Mode signal is “0”. An example of the operation will be described with reference to FIG. In the example shown in FIG. 4A, “0” is input as the initial value of the F / F 101. Further, an initial value is inputted to the F / F 103 so that the signal inputted from the timing false path E to the mask circuit 104 becomes “1”.

  After the initial value is input to each F / F by the shift operation, the Scan Enable signal is set to “0” and the capture period starts. In the capture period, the CK1 signal is input at the actual operating frequency (user clock) of the circuit or a frequency similar thereto. When the Scan Enable signal becomes “0”, the input of each F / F is switched from the scan path D to the user path. As a result, the input of the F / F 201 becomes “0”. The output of the mask circuit 104, that is, the input of the F / F 101 is “1”. In this state, the output of the F / F 101 transitions from “0” to “1” by the first clock in the capture period. Further, since the output of the F / F 201 becomes “0” and the AtSpeed Mask_Mode signal becomes “1”, the output of the mask circuit 104 is fixed to “0”, and thereafter, the timing false path E is masked. . By the second clock in this state, the output of the F / F 101 transitions from “1” to “0”. Further, in the second clock, the timing false path E is masked and is not subject to delay fault detection, so that there is no problem in test accuracy.

  A more general case will be described with reference to FIG. In the shift 1 period, the Scan Enable signal is “1”, and an arbitrary initial value is input to the F / Fs 101, 102, and 103 using the scan path D. As shown in the figure, in the final clock state of the shift 1 period, the input of the F / F 101 is the output signal of the timing false path E, and the output of the F / F 101 is the initial value input by the shift operation. In this state, the Scan Enable signal is set to “0” and the capture period starts. By the first clock in the capture period, the output of the F / F 101 is changed from the initial value input by the shift operation to the value input to the F / F 101, that is, the output of the timing false path E at the final clock time of the shift 1 period. Transition to signal.

  Further, since the output of the F / F 201 becomes “0” and the AtSpeed Mask_Mode signal becomes “1”, the output of the mask circuit 104, that is, the input of the F / F 101 is fixed to “0”. Will be masked. By the second clock in this state, the output of the F / F 101 becomes “0”. In this way, by using the Scan Enable signal in the generation of the AtSpeed Mask_Mode signal for controlling the mask circuit 104, the timing false path E is not masked until the first clock in the capture period, and the timing false path E in the first clock. Can be used to transition the input signal of the F / F 101.

  In the prior art, the signal for controlling the mask circuit is not changed during the test like the Test Mode signal according to this embodiment, and the timing false path is always masked. It was impossible to transition signals. However, by using the mask control signal generation unit 200 according to the present embodiment, it is possible to transition the input signal of the F / F 101 that is the end point of the first clock of the capture period using the timing false path E. It becomes. Therefore, by selecting “0” as the initial value of the F / F 101 and selecting the initial value of the F / F 103 so that the value of the F / F 101 transitions from “0” to “1” in the first clock, In F / F 101, both fall (transition from “1” to “0”) and rise (transition from “0” to “1”) can be detected, and the delay fault detection effect in path F is 100. %.

  In the prior art, in order to set the delay fault detection effect of the path after the timing false path to 100%, it is necessary to supplement the normal scan pattern. However, the fault detection method and mask control signal generation according to the present embodiment By using the unit 200, such complementation is unnecessary. Accordingly, it is possible to reduce the scan pattern length and the number of scan pattern creation steps. In addition, it is not necessary to perform a test using an external clock, and it is possible to test the entire path of the LSI at the actual operating frequency.

  The mask control signal generation unit 200 in this embodiment operates based on the Scan Enable signal, the Test Mode signal, and the CK1 signal that is a clock signal. The Scan Enable signal is a signal that is absolutely necessary when a test using a scanning method is performed. The Test Mode signal is “1” during the test and “0” during the normal operation, and may be the same as the LogicBIST_Mode signal in the prior art. Therefore, the failure detection method according to this embodiment can be easily implemented only by using the mask control signal generation unit 200 according to this embodiment.

As described above, according to the first embodiment of the present invention, it is possible to reduce the scan pattern length and test only at the actual operating frequency in the LSI failure detection test using the scanning method.
Embodiment 2. FIG.

  In the first embodiment, the problem is solved by controlling the mask circuit 104 so that the signal of the timing false path E can be temporarily used at the time of capture. In the present embodiment, a method will be described in which the input signal after the end point of the timing false path is changed by another method while the timing false path E is masked as in the prior art. In addition, about the structure which attaches | subjects the code | symbol similar to Embodiment 1, the same or equivalent part as Embodiment 1 is shown, and description is abbreviate | omitted.

  FIG. 5 is a circuit diagram showing a circuit to which the failure detection method according to this embodiment is applied. As shown in the figure, in the present embodiment, the mask circuit 104 is directly controlled by a LogicBIST_Mode signal. That is, during the test of the circuit, the output of the mask circuit 104 is always fixed to “0”.

  An alternative signal generation unit 300 is provided between the mask circuit 104 and the F / F 101. The substitute signal generation unit 300 includes an F / F 301 and a gate 302, and the output of the F / F 301 and the output of the mask circuit 104 are input to the gate 302. The gate 302 is an EXOR circuit that outputs an exclusive OR of the output of the mask circuit 104 and the output of the F / F 301.

  The F / F 301 operates based on a clock signal CK2 different from CK1. The F / F 301 receives its own output signal and Scan In signal, and either one is selected by the Scan Enable signal. Further, a reset signal for initializing the output signal is input to the F / F 301.

  As shown in the figure, the input of the F / F 101 according to the present embodiment is only the output of the substitute signal generation unit 300 regardless of the Scan Enable signal. The F / F 301 included in the substitute signal generation unit 300 forms a shift chain together with the F / F 101 and the F / F 102, and the scan-in signal as a shift value is input to the F / F 301 and sequentially shifted by the CK2 signal. .

  During normal operation, the Scan Enable signal and the LogicBIST_Mode signal are “0”. Therefore, the mask circuit 104 outputs the timing false path E signal as it is. Further, the F / F 301 repeatedly outputs its own signal according to the CK2 signal, but when entering the normal operation, the value of the F / F 301 becomes “0” by the Reset signal, so that the output of the F / F 301 is “at the time of normal operation” Fixed to 0 ". Therefore, the output of the substitute signal generation unit 300 during normal operation, that is, the input of the F / F 101 is the same signal as the output of the timing false path E.

  During the test operation, the LogicBIST_Mode signal is “1”. Therefore, since the output of the mask circuit 104 is fixed to “0”, the output of the substitute signal generation unit 300, that is, the input of the F / F 101 is the same signal as the output of the F / F 301. During the shift operation, the Scan Enable signal becomes “1”, and the Scan In signal is sequentially input according to the CK2 signal. At the time of capture, the Scan Enable signal becomes “0”, and the output of the F / F 301 is fixed to the value of the final clock during the shift operation. That is, in this embodiment, the timing false path E is masked by the mask circuit 104, but the input of the F / F 101 corresponding to the end point of the timing false path E is not fixed to “0”, and the value of the F / F 301 is used. Thus, the value of F / F101 can be changed.

  FIG. 6 is a timing chart showing the operation of the circuit shown in FIG. The operation of the circuit shown in FIG. 5 will be described with reference to FIG. In the shift 1 period, the Scan Enable signal is “1”, the CK1 signal and the CK2 signal are synchronized, and arbitrary initial values are input to the F / Fs 101 and 102 and the F / F 301 using the Scan In signal. As shown in the figure, in the state of the final clock in the shift 1 period, the input of the F / F 101 is the output signal of the F / F 301, and the output of the F / F 101 is the initial value input by the shift operation. In this state, the Scan Enable signal is set to “0” and the capture period starts. By the first clock of the CK1 signal in the capture period, the output of the F / F 101 changes from the initial value input by the shift operation to the value input to the F / F 101, that is, the F / F 301 at the time of the final clock of the shift 1 period. Transition to the output signal.

  Here, in the capture period, the CK1 signal and the CK2 signal are not synchronized. Therefore, during the AtSpeed test of the CK1 signal, the input signal of the F / F 101 is the output signal of the F / F 301 at the time of the last clock of the shift 1 period. It is fixed to. Therefore, the output of the F / F 101 is the same as that of the first clock even in the second clock of the CK1 signal.

  The CK2 signal operates at a timing different from that of the CK1 signal. Since the Scan Enable signal is “0”, the F / F 301 repeatedly outputs its own output signal. In the capture period, the CK1 signal and the CK2 signal operate at different timings, so that a timing path that is subject to AtSpeed does not occur from the F / F 301 to the F / F 101. The reason why CK2 is operated is mainly for testing other circuits operated by CK2.

  As described above, by providing the substitute signal generation unit 300 between the mask circuit 104 and the F / F 101, the input signal of the F / F 101 in the capture period is not fixed to “0”, and the value of the F / F 101 is changed. Can be made. However, in the AtSpeed test of the CK1 signal during the capture period, since the output signal of the F / F 301 does not change, it is necessary to perform the capture operation twice when both rise and fall are detected.

  As described above, according to the second embodiment of the present invention, in a state where the timing false path is masked, the signal input to the subsequent stage of the timing false path can be shifted without being fixed to “0”. it can.

In the above description, the F / F 301 forms a shift chain together with the F / F 101 and the F / F 102. However, the present invention is not limited to this. F / F 301, F / F 101, and F / F 102 belong to different shift chains, and different Scan In signals may be input thereto. In this case, the input of the F / F 101 is configured such that the output of the substitute signal generation unit 300 and the Scan In signal are selected by the Scan Enable signal.
Other embodiments.

  In the first embodiment, the mask control signal generation unit 200 is provided in the circuit and the mask circuit 104 is controlled based on the internal clock. However, as shown in FIG. 7, the AtSpeed Mask_Mode signal is input from the outside, and the mask circuit The problem can also be solved by directly controlling 104. That is, as in the first embodiment, the AtSpeed Mask_Mode signal is not generated and controlled based on the CK1 signal and the Scan Enable signal, but the AtSpeed Mask_Mode signal is generated by the external device, and the mask circuit 104 is directly connected from the external device. Control. By controlling the AtSpeed Mask_Mode signal at the same timing as shown in FIG. 2, the same effect as in the first embodiment can be obtained.

  By using such a configuration, it is not necessary to provide the mask control signal generation unit 200, and the overhead of the circuit can be reduced. Further, the AtSpeed Mask_Mode signal can be controlled at a desired timing regardless of the CK1 signal and the Scan Enable signal.

1 is a circuit diagram showing a circuit configuration according to a first embodiment of the present invention. 1 is a block diagram showing a circuit configuration according to Embodiment 1 of the present invention. It is a flowchart which shows the flow of the test which concerns on Embodiment 1 of this invention. 3 is a timing chart showing the operation of the circuit according to the first embodiment of the present invention. It is a circuit diagram which shows the circuit structure concerning Embodiment 2 of this invention. It is a timing chart which shows operation | movement of the circuit which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the circuit structure which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the circuit structure based on a prior art. It is a block diagram which shows the circuit structure based on a prior art. It is a timing chart which shows operation | movement of the circuit which concerns on a prior art. It is a flowchart which shows the flow of the test which concerns on a prior art. It is a circuit diagram which shows the circuit structure based on a prior art. It is a circuit diagram which shows the circuit structure based on a prior art. It is a timing chart which shows operation | movement of the circuit which concerns on a prior art.

Explanation of symbols

1, 3, 4, 5, 6, 7 F / F, 2, 8 mask circuit, 9, 10 gate 101, 102, 103 F / F, 104 mask circuit,
200 mask control signal generator, 201 F / F, 202 gate,
300 Substitute signal generator, 301 F / F, 302 gate,
A, B, C path, D scan campus, E timing false path, F path,

Claims (2)

A test circuit for testing a user circuit by a scan path,
A mask circuit for masking the non-failure detection target path, provided at a subsequent stage of the non-failure detection target path included in the user circuit;
The failure detection target path and the succeeding element located in the subsequent stage of the mask circuit;
A capture signal indicating a capture period in the test is input, the capture signal is stored in accordance with a clock signal input to the scan path in the capture period of the test, and the stored signal is output simultaneously. 1 control element;
A second control element that outputs a logical product signal of the inverted signal of the output signal of the first control element and a test mode signal indicating that the user circuit is in a test mode as the mask control signal; And
The mask circuit outputs a logical product signal of the signal of the failure detection target path and an inverted signal of a mask control signal for controlling the mask circuit;
The succeeding element is a test circuit that outputs an arbitrary signal rising or falling according to the first clock based on a logical value set by the logical product signal . A mask control circuit for controlling a mask circuit for masking a path not included in the failure detection included in the user circuit when the user circuit is tested by a scan path,
A capture signal indicating a capture period in the test is input, the capture signal is stored in accordance with a clock signal input to the scan path in the capture period of the test, and the stored signal is output simultaneously. 1 control element;
A second control element that outputs a logical product signal of an inverted signal of the output signal of the first control element and a test mode signal indicating that the user circuit is in a test mode as a control signal for controlling the mask circuit And having
Before Among chrysanthemum lock signal, the mask control circuit for controlling the mask circuit to mask the fault detection object out path in response to a rising edge of the at least first clock.

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