JP2005017067A - Semiconductor integrated circuit incorporating self-testing circuit, and method for diagnosing fault in the semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit for performing an inspection in a logic BIST, and to provide a method for easily diagnosing a fault in the logic BIST using the circuit, even when a fault occurs on a scan path. <P>SOLUTION: Partial scan path selecting information is given to a scan path, formed by alternately connecting a partial scan path formed by the serial connection of a scan FF, and a selector, a specific partial scan path is bypassed, and a scan pattern is applied. Additionally, the state of the scan FF is locked so that an undefined value will not propagate to a combination circuit that should be subjected to a scanning test from the scan FF for composing the bypassed partial scan path. Additionally, a faulty circuit block is specified, by utilizing the partial scan path and testing only the specified circuit block. Additionally, control is made so that only the value of the specified scan FF is propagated to MISR at scanning out. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit with a built-in self-test circuit and a failure diagnosis method therefor.
[0002]
[Prior art]
One of the recent large-scale and high-speed semiconductor integrated circuit test methods is a built-in self-test (Build-In Self-Test) method (hereinafter referred to as BIST method). In the BIST system, by incorporating a self-test circuit inside the device, it is possible to easily generate a test pattern to be applied to the test target circuit, compress the output pattern from the test target circuit, and collate the expected value. . The BIST method is attracting attention as an effective means that can optimally perform tests on large-scale and high-speed semiconductor integrated circuits in which multiple circuits with different characteristics such as system LSIs are mounted as core blocks at high quality and at low cost. Collected and widely used.
[0003]
A major feature of the basic configuration of the logic BIST that is a built-in self-test method for a logic circuit is that a PRPG that is a pseudo-random test pattern generation circuit and a MISR that is a signature compressor are incorporated in the device.
[0004]
By applying a control signal such as a BIST activation signal or a clock signal from an external device such as an LSI tester, a test pattern is generated from the PRPG incorporated in the device and applied to the test target circuit. The output pattern from the circuit under test is input to the MISR and compressed into a signature. The signature is read using an external device and is used to determine whether the device is good or bad.
[0005]
In the logic BIST, the quality of the device is determined based on the MISR state at the end of the test. When an indefinite value is propagated to the MISR, all the values in the state register become indefinite values, which makes it unusable as an expected value used for inspection. In the circuit disclosed in Patent Document 1, a mask gate is arranged in front of a code compression circuit (MISR), and these are controlled by a mask register to solve this problem.
[0006]
FIG. 10 shows a basic configuration example of a circuit disclosed in Patent Document 1. The configuration of FIG. 10 will be described. Reference numerals 101, 102, and 103 denote scan paths. Reference numerals 104a, 104b, and 104c denote mask registers that store mask information for scan paths that are not to be tested during self-test execution. A pattern generator 105 generates an input sequence for the scan path. A code compressor 106 compresses an output response from the scan path. Reference numerals 107a, 107b, and 107c denote mask gates for masking signal values from the scan path to the code compressor.
[0007]
Outputs of the mask registers 104a, 104b, and 104c are connected to mask gates 107a, 107b, and 107c, and control the mask gates 107a, 107b, and 107c. The mask gates 107a, 107b, and 107c are OR gates disposed between the scan paths 101, 102, and 103 and the code compressor 106. When the values of the mask registers 104a, 104b, and 104c are “1”, Regardless of the values of the scan paths 101, 102, and 103, the outputs of the mask gates 107 a, 107 b, and 107 c are fixed to “1”, and signals from the scan paths 101, 102, and 103 are not input to the code compressor 106.
[0008]
Next, a description will be given of what tests can be performed by the states of the mask registers 104a, 104b, and 104c and the mask gates 107a, 107b, and 107c. When the values of the mask registers 104a, 104b, and 104c are all “0”, the scan paths 101, 102, and 103 are not masked, and the normal operation BIST is executed. When the value of the mask register 104a is “1”, the value of the scan path 101 is masked. When the value of the mask register 104b is “1”, the value of the scan path 102 is masked. When the value of the mask register 104c is “1”, the value of the scan path 103 is masked. As a result, even when the operation of a specific scan path is unstable and the output becomes an indefinite value, it is possible to execute the BIST by operating only the scan path that operates normally.
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-249164 (page 4-5, FIG. 1)
[0010]
[Problems to be solved by the invention]
In the circuit configuration shown in the prior art, the values of all the FFs (flip-flops) on the masked scan path cannot be observed, so the failure detection rate value obtained by BIST is significantly reduced. There is a problem.
[0011]
In addition, when signal transfer occurs between different scan paths, simply inserting a mask circuit between the output compression circuit (code compressor) and the scan path completely eliminates the effects of the unstable scan path. It cannot be excluded.
[0012]
The present invention was created in view of such circumstances, and even if a failure occurs in a certain scan path, a semiconductor integrated circuit with a built-in self-test circuit that can self-test without significantly reducing the failure detection rate It aims to provide a circuit.
[0013]
Another object of the present invention is to provide a failure diagnosis method capable of facilitating failure diagnosis in a semiconductor integrated circuit incorporating a self test circuit.
[0014]
[Means for Solving the Problems]
The present invention relates to a scan path for testing a semiconductor integrated circuit, a combinational circuit to be a scan test, a pattern generation circuit for supplying a test pattern to the scan path, and an output for compressing an output response from the scan path Assume a semiconductor integrated circuit with a self-test circuit and a compression circuit. And this invention solves said subject by taking the following means.
[0015]
As a first solution, in the semiconductor integrated circuit with a built-in self-test circuit according to the present invention, the scan path is first configured as follows. Divide the scan chain into multiple partial scan paths. Each partial scan path is configured by one scan FF, or is configured by serially connecting two or more scan FFs. A scan chain is configured by alternately connecting partial scan paths and selectors. In a module composed of a combination of a partial scan path and a selector, the output of the partial scan path is taken as one input of the selector. The other input of the selector is connected to the pattern generation circuit. The input of the partial scan path in the frontmost module is connected to the pattern generation circuit. The output of the selector is connected to the input of the partial scan path in the next stage module. However, the output of the selector of the last stage module is connected to the output compression circuit. In all the modules, one input of the selector is all connected to the pattern generation circuit. With this configuration, the shift operation is performed by bypassing the scan FFs included in one or more partial scan paths counted from the scan-in side of the scan path according to the partial scan path selection information given as selection signals for a plurality of selectors. It is characterized by doing.
[0016]
According to this configuration, when a certain scan FF in the scan path has a defect, the shift operation includes a defective scan FF and bypasses a partial scan path that may output an indefinite value. Reduce the influence of indeterminate values and enable self-embedding tests. The closer to the scan-in side on the scan chain, the smaller the number of scan FFs to be bypassed and the lower the failure detection rate. Therefore, this solution is effective in avoiding a problem in the scan FF close to the scan-in side.
[0017]
As a second solution, in the semiconductor integrated circuit with a built-in self-test circuit according to the present invention, first, the scan path is configured as follows. Divide the scan chain into multiple partial scan paths. Each partial scan path is configured by one scan FF, or is configured by serially connecting two or more scan FFs. Connect multiple partial scan paths serially. In other words, the output of a partial scan path is connected to the input of the next partial scan path. The output of each partial scan path is connected to an output compression circuit via a selector. A pattern generation circuit is connected to the input of the first partial scan path. One input of the selector may be connected to the pattern generation circuit. With this configuration, the shift operation is performed by bypassing the scan FFs included in one or more partial scan paths counted from the scan-out side of the scan path according to the partial scan path selection information given as selection signals for a plurality of selectors. It is characterized by doing.
[0018]
According to this configuration, when a certain scan FF in the scan path has a defect, the shift operation includes the defective scan FF and bypasses the partial scan path or the like that may output an indefinite value. Reduces the influence of undefined values caused by the self-built-in test. The closer to the scan-out side the scan FF in which a problem has occurred, the smaller the number of scan FFs to be bypassed and the lower the failure detection rate. Therefore, this solution is effective in avoiding a problem in the scan FF close to the scan-out side.
[0019]
As a third solution, in the semiconductor integrated circuit with a built-in self-test circuit according to the present invention, first, the scan path is configured as follows. Divide the scan chain into multiple partial scan paths. Each partial scan path is configured by one scan FF, or is configured by serially connecting two or more scan FFs. A scan chain is configured by alternately connecting partial scan paths and selectors. In a module composed of a combination of a partial scan path and a selector, the output of the partial scan path is taken as one input of the selector. The other input of the selector is connected to the output of the selector of the preceding module. One input of the selector of the frontmost module is connected to the pattern generation circuit. The input of the partial scan path in the frontmost module is connected to the pattern generation circuit. The output of the selector is connected to the input of the partial scan path in the next stage module. However, the output of the selector of the last stage module is connected to the output compression circuit. In all modules other than the final stage, the output of the selector is connected to the partial scan path and the selector of the next stage module. In all modules other than the first stage, the selector selects an input and an output in its partial scan path. With this configuration, the shift operation is performed by bypassing the scan FF included in an arbitrary partial scan path according to partial scan path selection information given as selection signals for a plurality of selectors.
[0020]
According to this configuration, when a certain scan FF in the scan path has a defect, the shift operation includes a defective scan FF and bypasses a partial scan path that may output an indefinite value. Reduce the influence of indeterminate values and enable self-embedding tests. The number of scan FFs to be bypassed is bypassed because only the partial scan path including the scan FF is bypassed and the other partial scan paths are not bypassed, regardless of the position of the scan FF in which the defect occurs on the scan path. And there is little decrease in failure detection rate. Therefore, it is effective regardless of the location of the scan path.
[0021]
In a preferred embodiment, the scan FF of the bypassed partial scan path is configured so that an indefinite value does not propagate to the scan test target combinational circuit from the scan FF constituting the partial scan path bypassed from the scan pattern application target. It is configured so that resetting or setting of the device is not released.
[0022]
According to this configuration, by locking the state of the scan FF for the partial scan path removed from the scan chain by bypass, an indefinite value is propagated from the bypass partial scan path to the combinational circuit. As a result, it is possible to prevent the inconvenience that the indefinite value is propagated to the partial scan path to be tested that is not bypassed. Thereby, the fall of the failure detection rate in a built-in self test can be suppressed.
[0023]
Further, in the above, a preferable aspect is that the indeterminate value is not propagated from the scan FF constituting the partial scan path bypassed from the scan pattern application target to the scan test target combinational circuit. The data output of the scan FF is configured to be fixed. This is to fix the output value of the scan FF by masking it with a gate or the like. Even if the internal state of the scan FF changes, it is locked externally.
[0024]
Even in this configuration, for the partial scan path removed from the scan chain by bypass, the indeterminate value is propagated from the bypass partial scan path to the combinational circuit by locking the output value of the scan FF. As a result, it is possible to prevent the inconvenience that the indefinite value is propagated to the partial scan path to be tested that is not bypassed. Thereby, the fall of the failure detection rate in a built-in self test can be suppressed.
[0025]
Furthermore, a preferable aspect in the above has a function of passing a signal from the scan path to the output compression circuit at a selected time and masking a signal from the scan path to the output compression circuit at other times. And a means for propagating only the influence of the fault propagated to the specific scan FF during the self-embedding test.
[0026]
According to this configuration, it is possible to know which scan FF among the plurality of scan FFs constituting the partial scan path has observed the failure. Thereby, narrowing down of a failure location can be further advanced.
[0027]
A fault diagnosis method for a semiconductor integrated circuit with a built-in self-test circuit according to the present invention is configured to include a plurality of steps having the following contents in a semiconductor integrated circuit with a built-in self-test circuit having any one of the above-described configurations. Yes. That is,
Selecting a partial scan path (a);
A step (b) of executing a self-test by bypassing a partial scan path other than the partial scan path selected in step (a) from the scan path; and all the partial scan paths are selected in step (a). Step (c).
[0028]
Then, the step (b) is executed after the step (a), and after the step (b), if the test result of the step (b) is successful (Pass), the step (c) is executed. When the test result in the step (b) is failure (Fail), the circuit block including the failure part is specified.
[0029]
According to this failure diagnosis method, it is advantageous to efficiently identify the circuit block including the failure location and narrow down the failure location.
[0030]
Also, another failure diagnosis method for a semiconductor integrated circuit with a built-in self-test circuit according to the present invention includes a plurality of steps having the following contents in the semiconductor integrated circuit with a built-in self-test circuit having any one of the above-described configurations. It is configured as. That is,
Dividing a plurality of partial scan paths in the circuit into two groups A and B;
Performing a built-in self-test by bypassing a partial scan path included in group A from the scan path; and
Determining whether group B includes more than one partial scan path (c);
Dividing the partial scan path included in group B into two groups A and B anew (d);
Determining whether group A includes two or more partial scan paths (e);
Dividing the partial scan path included in group A into two groups A and B anew (f);
The step (g) includes performing a self-test by bypassing all the partial scan paths except for the partial scan path included in the group A from the scan path.
[0031]
Then, the step (a) is executed first, and then the step (b) is executed. If the test result of the step (b) is failure (Fail), then the step (c) is executed. If the test result of the step (b) is successful (Pass), then the step (e) is executed, and if the determination result of the step (c) is affirmative, the step (d) is subsequently executed. If the determination result of step (c) is negative, a faulty circuit block is specified, and if the determination result of step (e) is affirmative, step (f) is subsequently executed, When the determination result of (e) is negative, the step (g) is continuously executed, and when the test result of the step (g) is failure (Fail), a faulty circuit block is specified.
[0032]
This is a failure diagnosis method using a binary search method, and the efficiency of narrowing down fault circuit blocks can be further improved as compared with the sequential search method.
[0033]
Furthermore, the failure diagnosis method for a semiconductor integrated circuit with a built-in self-test circuit according to the present invention is configured to include a plurality of steps having the following contents. That is,
A step (d) of selecting a time at which to unmask; and
(E) performing a built-in self-test by turning on the diagnostic mode signal so that the signal from the scan path is passed to the output compression circuit only at the mask release time selected in the step (d),
A step (f) for determining whether the mask is released at all times that can be selected in the step (e) is added.
[0034]
Then, after identifying the faulty circuit block, the step (d) is executed, the step (e) is executed after the step (d), and the test result of the step (e) is executed after the step (e). Is a success (Pass), step (f) is executed, and if the test result of the step (e) is failure (Fail), the scan FF in which the failure is detected is specified.
[0035]
According to this failure diagnosis method, it is possible to know which scan FF among the plurality of scan FFs constituting the partial scan path has observed the failure. Thereby, narrowing down of a failure location can be further advanced.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self-test circuit according to Embodiment 1 of the present invention.
[0037]
In FIG. 1, reference numerals 201 and 202 denote scan paths for testing the semiconductor integrated circuit of FIG. Reference numerals 203, 204, and 205 denote partial scan paths that constitute the scan path 201, and reference numerals 206, 207, and 208 denote partial scan paths that constitute the scan path 202. Each of the partial scan paths 203, 204, 205, 206, 207, and 208 is configured by serially connecting two scan FFs. The scan FF includes a data input terminal D from the combinational circuit, a data input terminal SI from the scan path, a data output terminal Q, an input terminal SE for switching between the data input terminal D and the data input terminal SI, and a clock terminal CK. Have. Reference numerals 209, 210, 211, 212, 213, and 214 are selectors. The selectors 209, 210, 211, 212, 213, and 214 have two data input signals A and B, a data input selection signal S, and a data output signal Y. When S = 1, Y = A, and when S = 0, Y = B.
[0038]
The scan paths 201 and 202 are formed by alternately connecting partial scan paths configured by serially connecting two scan FFs and selectors.
[0039]
Reference numerals 215, 216, 217, 218, 219, and 220 denote combinational circuits that are scan test targets. A pattern generation circuit (PRPG) 221 supplies a test pattern to the scan paths 201 and 202. An output compression circuit (MISR) 222 compresses output responses from the scan paths 201 and 202. Reference numerals 223, 224, 225, 226, 227, and 228 are signal lines connected to the S inputs of the selectors 209, 210, 211, 212, 213, and 214, respectively. 229 is partial scan path selection information given to the signal lines 223, 224, 225, 226, 227, and 228. 230 and 231 are signal lines through which test patterns for the scan paths 201 and 202 are propagated from the pattern generation circuit 221. The A inputs of the selectors 209, 210, 211, 212, 213, and 214 are connected to the Q terminals of the scan FFs on the most scan-out side of the partial scan paths 205, 204, 203, 208, 207, and 206, respectively. The B input is connected to the signal line 231 for the selectors 209, 210 and 211, and to the signal line 230 for the selectors 212, 213 and 214.
[0040]
Assuming that a partial scan path and a selector having the output of the partial scan path as one input are modules, the other one input of each selector 209 to 214 is connected to the pattern generation circuit 221 in each module. Inputs of the partial scan paths 205 and 208 in the frontmost module are connected to the pattern generation circuit 221. In the modules other than the final stage, the outputs of the selectors 209, 210, 212, and 213 are connected to the inputs of the partial scan paths 204, 203, 207, and 206 in the next stage module. However, the outputs of the selectors 211 and 214 of the final stage module are connected to the output compression circuit 222. In all the modules, all inputs of the selectors 209 to 214 are connected to the pattern generation circuit 221. With this configuration, the scan FFs included in one or more partial scan paths counted from the scan-in side of the scan paths 201 and 202 are determined by the partial scan path selection information 229 given as selection signals for the plurality of selectors 209 to 214. The shift operation is performed by bypass.
[0041]
When {1111011} is given to the partial scan path selection information 229, the values of the signal lines 228, 227, 226, 223, 224, and 225 are 1, 1, 1, 0, 1, 1, respectively. The scan FF included in the partial scan path 205 corresponding to 0 ″ is bypassed from the scan path 201. The shift operation during the built-in self test is performed with the scan FF included in the partial scan path 205 being bypassed.
[0042]
By adopting such a configuration, even if a shift operation occurs in the scan FF included in the partial scan path 205 and an indefinite value is output, the indefinite value is not captured by the output compression circuit (MISR) 222. Self-embedding tests can be performed.
[0043]
Further, when {111101} is given to the partial scan path selection information 229, scan FFs included in all partial scan paths 205 and 204 on the scan-in side from the partial scan path 204 corresponding to the bit “0” are scanned. The shift operation is performed by bypassing from the campus 201.
[0044]
When {111110} is given to the partial scan path selection information 229, the scan FFs included in all the partial scan paths 205, 204, and 203 on the scan-in side from the partial scan path 203 corresponding to the bit “0” among them. Are bypassed from the scan path 201 and the shift operation is performed.
[0045]
The above is the description of the operation on the scan path 201 side, but the same operation is performed on the scan path 202 side.
[0046]
In this configuration, the closer the malfunctioning scan FF is to the scan-in side on the scan chain, the smaller the number of bypass scan FFs and the lower the failure detection rate. Therefore, it is effective in avoiding a problem in the scan FF close to the scan-in side.
[0047]
(Embodiment 2)
FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to the second embodiment of the present invention.
[0048]
In FIG. 2, reference numerals 301 and 302 denote scan paths for testing the semiconductor integrated circuit. Reference numerals 303, 304, and 305 denote partial scan paths that constitute the scan path 301, and reference numerals 306, 307, and 308 denote partial scan paths that constitute the scan path 302. Each of the partial scan paths 303, 304, 305, 306, 307, and 308 is configured by serially connecting two scan FFs. The scan FF includes a data input terminal D from the combinational circuit, a data input terminal SI from the scan path, a data output terminal Q, an input terminal SE for switching between the data input terminal D and the data input terminal SI, and a clock terminal CK. Have. 309 and 310 are selectors each having four data inputs. The selectors 309 and 310 have four data input signals A, B, C and D, data input selection signals S0, S1 and S2, and a data output signal Y.
[0049]
FIG. 3 shows a detailed configuration of the selectors 309 and 310. When {S0, S1, S2} = {1, 1, 1}, Y = A, {S0, S1, S2} = {0, 1, 1}, Y = B, {S0, S1, S2 } = {X, 0, 1}, Y = C, and {S0, S1, S2} = {X, X, 0}, Y = D. Here, X is 0 or 1.
[0050]
The scan paths 301 and 302 are formed by serially connecting partial scan paths configured by serially connecting two scan FFs, and finally by connecting selectors 309 and 310.
[0051]
Reference numerals 311, 312, 313, 314, 315, and 316 are combinational circuits that are scan test targets. Reference numeral 317 denotes a pattern generation circuit (PRPG) that supplies a test pattern to the scan paths 301 and 302. An output compression circuit (MISR) 318 compresses output responses from the scan paths 301 and 302. 319, 320, and 321 are signal lines connected to the S0 input, S1 input, and S2 input of the selector 309, respectively. 322, 323, and 324 are signal lines connected to the S0 input, S1 input, and S2 input of the selector 310, respectively. Reference numeral 325 denotes partial scan path selection information given to the signal lines 319, 320, 321, 322, 323, and 324. Reference numerals 326 and 327 denote signal lines through which test patterns for the scan paths 301 and 302 are propagated from the pattern generation circuit 317. The A input, B input, and C input of the selector 309 are respectively connected to the Q terminals of the scan FFs on the most scan-out side of the partial scan paths 305, 304, and 303. The D input of the selector 309 is connected to the signal line 327. The A input, B input, and C input of the selector 310 are connected to the Q terminals of the scan FFs on the most scan-out side of the partial scan paths 308, 307, and 306, respectively. The D input of the selector 310 is connected to the signal line 326.
[0052]
When {111110} is given to the partial scan path selection information 325, the values of the signal lines 322, 323, 324, 319, 320, and 321 are 1, 1, 1, 1, 1, and 0, respectively. The scan FF included in the partial scan path 305 corresponding to 0 ″ is bypassed from the scan path 301. The shift operation during the built-in self test is performed with the scan FF included in the partial scan path 305 being bypassed.
[0053]
By adopting such a configuration, even if a shift operation occurs in the scan FF included in the partial scan path 305 and an indefinite value is output, the indefinite value is not captured by the output compression circuit (MISR) 318. Self-embedding tests can be performed.
[0054]
Further, when {111101} is given to the partial scan path selection information 325, scan FFs included in all partial scan paths 304 and 305 on the scan-out side from the partial scan path 304 corresponding to the bit “0” are scanned. The shift operation is performed by bypassing from the campus 301.
[0055]
If {1111011} is given to the partial scan path selection information 325, the scan FFs included in all the partial scan paths 303, 304, and 305 on the scan-out side from the partial scan path 303 corresponding to the bit “0” among them. Are bypassed from the scan path 301 and the shift operation is performed.
[0056]
The above is the description of the operation on the scan path 301 side, but the same operation is performed on the scan path 302 side.
[0057]
In this configuration, the closer the malfunctioning scan FF is to the scan-out side on the scan chain, the smaller the number of bypass scan FFs and the lower the failure detection rate. Therefore, it is effective in avoiding a problem in the scan FF close to the scan-out side.
[0058]
(Embodiment 3)
FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to the third embodiment of the present invention.
[0059]
In FIG. 4, 401 and 402 are scan paths for testing a semiconductor integrated circuit. Reference numerals 403, 404, and 405 denote partial scan paths that constitute the scan path 401, and reference numerals 406, 407, and 408 denote partial scan paths that constitute the scan path 402. Each of the partial scan paths 403, 404, 405, 406, 407, and 408 is configured by serially connecting two scan FFs. The scan FF includes a data input terminal D from the combinational circuit, a data input terminal SI from the scan path, a data output terminal Q, an input terminal SE for switching between the data input terminal D and the data input terminal SI, and a clock terminal CK. have. Reference numerals 409, 410, 411, 412, 413, and 414 denote selectors. The selectors 409, 410, 411, 412, 413, 414 have two data input signals A, B, a data input selection signal S, and a data output signal Y. When S = 1, Y = A, and when S = 0, Y = B.
[0060]
The scan paths 401 and 402 are formed by alternately connecting partial scan paths and selectors configured by serially connecting two scan FFs. Reference numerals 415, 416, 417, 418, 419, and 420 denote combinational circuits that are scan test targets. Reference numeral 421 denotes a pattern generation circuit (PRPG) that supplies a test pattern to the scan paths 401 and 402. An output compression circuit (MISR) 422 compresses output responses from the scan paths 401 and 402. Reference numerals 423, 424, 425, 426, 427, and 428 are signal lines connected to the S inputs of the selectors 409, 410, 411, 412, 413, and 414, respectively. Reference numeral 429 denotes partial scan path selection information given to the signal lines 423, 424, 425, 426, 427, and 428. Reference numerals 430 and 431 denote signal lines through which test patterns for the scan paths 401 and 402 are propagated from the pattern generation circuit 421.
[0061]
The A inputs of the selectors 409, 410, 411, 412, 413, and 414 are connected to the Q terminals of the scan FFs on the most scan-out side of the partial scan paths 405, 404, 403, 408, 407, and 406, respectively. The B inputs of the selectors 409 and 412 are connected to the signal line 431 and the signal line 430, respectively. The B inputs of the selectors 410, 411, 413, and 414 are connected to the Y output of the selector 409, the Y output of the selector 410, the Y output of the selector 412, and the Y output of the selector 413, respectively.
[0062]
When {111101} is given to the partial scan path selection information 429, the values of the signal lines 428, 427, 426, 423, 424, and 425 are 1, 1, 1, 1, 0, and 1, respectively. The scan FF included in the partial scan path 404 corresponding to 0 ″ is bypassed from the scan path 401. The shift operation during the built-in self test is performed with the scan FF included in the partial scan path 404 being bypassed.
[0063]
By adopting such a configuration, even if a shift operation occurs in the scan FF included in the partial scan path 404 and an indefinite value is output, the indefinite value is not captured by the output compression circuit (MISR) 422. Self-embedding tests will be feasible.
[0064]
When {1111011} is given to the partial scan path selection information 429, the scan FF included in the partial scan path 405 corresponding to the bit “0” is bypassed from the scan path 401.
[0065]
When {111110} is given to the partial scan path selection information 429, the scan FF included in the partial scan path 403 corresponding to the bit “0” is bypassed from the scan path 401.
[0066]
The above is the description of the operation on the scan path 401 side, but the same operation is performed on the scan path 402 side.
[0067]
In this configuration, the number of scan FFs to be bypassed is small regardless of the position of the scan FF where the failure occurred on the scan path, and the failure detection rate is hardly lowered. Therefore, it is effective regardless of the location of the scan path.
[0068]
(Embodiment 4)
FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to the fourth embodiment of the present invention.
[0069]
In FIG. 5, reference numerals 509 and 510 denote scan paths for testing the semiconductor integrated circuit. Reference numerals 501 and 502 denote partial scan paths constituting the scan path 509, and reference numerals 503 and 504 denote partial scan paths constituting the scan path 510. Reference numerals 505, 506, 507, and 508 denote selectors. The scan paths 509 and 510 are formed by alternately connecting partial scan paths configured by serially connecting two scan FFs and selectors. Reference numeral 511 denotes a combinational circuit to be a scan test target. A pattern generation circuit 512 supplies a test pattern to the scan paths 509 and 510. Reference numeral 513 denotes an output compression circuit that compresses output responses from the scan paths 509 and 510. Reference numerals 519, 520, 521, and 522 denote AND gates. Reference numeral 523 denotes an external reset signal. AND gates 519, 520, 521, and 522 each have two input signals. The first input signal is an external reset signal common to all the AND gates 519, 520, 521, and 522. The second input signal is a signal line 517 for the AND gate 519, a signal line 518 for the AND gate 520, a signal line 515 for the AND gate 521, and a signal line 516 for the AND gate 522. It is. Reference numeral 514 denotes partial scan path selection information given to the signal line 515, the signal line 516, the signal line 517, and the signal line 518. Output signals of AND gates 519, 520, 521, and 522 are connected to selection signals of selectors 505, 506, 507, and 508, respectively.
[0070]
By providing {1101} as the partial scan path selection information 514 to the signal lines 515, 516, 517, and 518, the scan FFs constituting the partial scan path 501 are bypassed from the shift operation target. Thereby, even when a malfunction occurs in the scan operation due to the influence of the scan FF included in the partial scan path 501, the self-embedding test can be executed.
[0071]
This configuration is effective when there is a path from the bypassed scan FF to the non-bypassed scan FF. When the operation of the bypassed scan FF is unstable, an indefinite value may propagate from the bypassed scan FF to the combinational circuit, and the indefinite value may propagate to the scan target FF that is not bypassed. There is. In this embodiment, the reset is not canceled for the bypassed scan FF, and the output Q is fixed. As a result, the indefinite value is not propagated to the combinational circuit, and it is possible to avoid the indefinite value from being propagated to the scan target FF that is not bypassed.
[0072]
A similar effect can be obtained by masking and fixing the output value of the bypassed scan FF with an AND gate or the like.
[0073]
Further, a failure diagnosis method using the testability circuit of the semiconductor integrated circuit will be described. The flow of the failure diagnosis method shown in FIG. 6 is shown.
[0074]
Reference numeral 601 denotes a step of selecting a partial scan path. Reference numeral 602 denotes a step of executing a built-in self test by bypassing a partial scan path other than the partial scan path selected in step 601 from the scan path. Reference numeral 603 denotes a step in which it is determined in step 601 whether all partial scan paths have been selected. In order to make correspondence with the claims, step 601 is set as (a), step 602 is set as (b), and step 603 is set as (c).
[0075]
A processing procedure will be described. After step 601, step 602 is executed. If the test result of step 602 is Pass, step 603 is executed subsequently. If the test result in step 602 is Fail, the circuit block including the failure location is specified, and the flow ends.
[0076]
An example in which a circuit block including a fault location is specified in the circuit shown in FIG. The combinational circuit 511 in FIG. 5 has four blocks A, B, C, and D, and a failure exists in the block B.
[0077]
A case where the flow of FIG. 6 is executed for this circuit will be described. First, the partial scan path 501 is selected as the partial scan path to be applied with the scan pattern. In order to bypass all other partial scan paths except the partial scan path 501 from the scan path, partial scan path selection information {0010} is given to the signal lines 515, 516, 517, and 518. As a result, the test pattern is applied only to the scan FFs constituting the partial scan path 501. The other scan FFs constituting the partial scan path are reset, and the output Q is fixed to zero. A self-built test is then performed. As a result, only the partial circuit A in which the output signal propagates to the scan FFs constituting the partial scan path 501 is tested. Since there is no failure in the partial circuit A, the test result is Pass.
[0078]
Of the partial scan paths 502, 503, and 504 not selected as the scan pattern application target, the partial scan path 502 is selected as the partial scan path as the scan pattern application target. In order to bypass all the partial scan paths other than the partial scan path 502 from the scan path, partial scan path selection information {0001} is given to the signal lines 515, 516, 517, and 518. As a result, the test pattern is applied only to the scan FFs constituting the partial scan path 502. The other scan FFs constituting the partial scan path are reset, and the output Q is fixed to zero. A self-built test is then performed. As a result, only the partial circuit B in which the output signal propagates to the scan FFs constituting the partial scan path 502 is tested. Since there is a failure in the partial circuit B, the test result is Fail. As a result, B is specified as the fault circuit block.
[0079]
In the flow of FIG. 6, the failure block is specified by a method in which the divided circuit blocks A, B, C, and D are individually tested sequentially, but the binary search is performed as in the flow shown in FIG. 7. A technique may be used.
[0080]
In step (a), a plurality of partial scan paths in the circuit are divided into two groups A and B.
[0081]
Next, in step (b), the built-in self test is executed by bypassing the partial scan path included in group A from the scan path. If the test result is Fail, the process proceeds to step (c). If the test result is Pass, the process proceeds to step (e).
[0082]
In step (c), it is determined whether or not the group B includes two or more partial scan paths. When the determination result is Yes, the process proceeds to step (d). When the determination result is No, the faulty circuit block is specified.
[0083]
In step (d), the partial scan path included in group B is divided again into two groups A and B.
[0084]
In step (e), it is determined whether or not group A includes two or more partial scan paths. When the determination result is Yes, the process proceeds to step (f), and when the determination result is No, the process proceeds to step (g).
[0085]
In step (f), the partial scan path included in group A is divided again into two groups A and B.
[0086]
In step (g), all the partial scan paths except for the partial scan path included in the group A are bypassed from the scan path, and the self test is performed.
[0087]
According to this binary search method, each block is divided into two groups, and the blocks included in one of the groups are tested at the same time. Depending on the result, there is a possibility that this fault circuit block exists. A group is divided into two groups for testing, and the same is repeated according to the result.
[0088]
According to this, it is possible to narrow down fault circuit blocks. In this case, the time for narrowing down the faulty circuit blocks is considered to be faster than the sequential test method.
[0089]
(Embodiment 5)
FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to the fifth embodiment of the present invention.
[0090]
In FIG. 8, reference numeral 701 is the same as the configuration of FIG. Hereinafter, when the inside of 701 is described, the reference numerals used in FIG. 5 are referred to.
[0091]
In FIG. 8, reference numeral 702 denotes a mask release permission signal generation circuit. 703 is a shift counter, 704 is mask release time information, 705 is a comparator, 706 is a two-input OR gate, and 707 is an inverter. These reference numerals 703, 704, 705, 706, and 707 are components of the mask release permission signal generation circuit 702. Reference numeral 708 denotes a diagnostic mode signal, which is an input signal to the mask release permission signal generation circuit 702. Reference numeral 709 denotes a mask release permission signal, which is an output signal of the mask release permission signal generation circuit 702. Reference numeral 710 denotes a mask circuit for masking a signal from the scan path, and is composed of two 2-input AND gates. One input of these two-input AND gates is a mask release permission signal 709, and the other input is an output signal of the scan path.
[0092]
When the diagnostic mode signal 708 is “1” and the time set as the mask release time information 704 is compared with the value of the shift counter 703 by the comparator 705, the mask release permission signal generation circuit 702 matches the values. At this time, “1” is output from the mask release permission signal 709. The value that can be counted by the shift counter 703 is the same value as the number of scan path stages, and the mask release permission signal 709 becomes “1” only at a specific time in one shift period. When the value of the mask release permission signal 709 is “1”, one input of the AND gate configuring the mask circuit 710 is “1”, and the signal is not masked from the scan path which is the other input, and is sent to the output compression circuit 513. Propagated.
[0093]
With this configuration, it is possible to select a partial scan path to be excluded from the scan pattern application target on the scan path, and to apply the scan pattern by bypassing the scan FF constituting the selected partial scan path. In addition to the reset state of the scan FF that is reset, only the influence of the fault that has propagated to the specific scan FF during the self-embedding test can be propagated to the output compression circuit.
[0094]
Further, a failure diagnosis method using the testability circuit of the semiconductor integrated circuit will be described. Here, an example is shown in which a fault circuit block is first specified by the flow of the fault diagnosis method shown in FIG. 6, and a scan FF in which a fault is observed is specified according to the fault diagnosis flow shown in FIG.
[0095]
The description of FIG. 6 has been made in Embodiment 4 and is therefore omitted. First, the flow of FIG. 9 will be described. Reference numeral 804 denotes a step of selecting a time for canceling the mask. 805 is a step in which the signal from the scan path is passed to the output compression circuit 513 only at the mask release time selected in step 804, the diagnostic mode signal 708 is turned on, and the built-in self test is executed. Reference numeral 806 denotes a step of determining whether or not the mask is released at all times that can be selected in step 804. In order to make correspondence with the claims, step 804 is set as (d), step 805 is set as (e), and step 806 is set as (f).
[0096]
A processing procedure will be described. Following step 804, step 805 is executed. Thereafter, when the test result in Step 805 is Pass, Step 806 is subsequently executed. If the test result in Step 805 is Fail, the scan FF that detected the failure is specified, and the flow ends. After step 806, if the determination result in this step is Yes, that is, if mask removal is performed at all times that can be selected in step 804, the flow ends. If the determination result in step 806 is No, that is, if the mask is not released at all times selected in step 804, the process returns to step 804.
[0097]
An example in which a circuit block including a fault location is specified in the circuit shown in FIG. Here, a failure exists in the block B. The failure of block B propagates to scan FF1. After the flow shown in FIG. 6 is performed and the faulty circuit block is specified, an example in which the flow shown in FIG. 9 is executed and the FF in which the fault is observed is specified is shown. First, the partial scan path 501 is selected as the partial scan path to be applied with the scan pattern. In order to bypass all other partial scan paths except the partial scan path 501 from the scan path, partial scan path selection information {0010} is given to the signal lines 515, 516, 517, and 518. As a result, the test pattern is applied only to the scan FFs constituting the partial scan path 501. The other scan FFs constituting the partial scan path are reset, and the output Q is fixed to zero. A self-built test is then performed. As a result, only the partial circuit A in which the output signal propagates to the scan FFs constituting the partial scan path 501 is tested. Since there is no failure in the partial circuit A, the test result is Pass. Of the partial scan paths 502, 503, and 504 not selected as the scan pattern application target, the partial scan path 502 is selected as the partial scan path as the scan pattern application target. In order to bypass all the partial scan paths other than the partial scan path 502 from the scan path, partial scan path selection information {0001} is given to the signal lines 515, 516, 517, and 518. As a result, the test pattern is applied only to the scan FFs constituting the partial scan path 502. The other scan FFs constituting the partial scan path are reset, and the output Q is fixed to zero. A self-built test is then performed. As a result, only the partial circuit B in which the output signal propagates to the scan FFs constituting the partial scan path 502 is tested. Since there is a failure in the partial circuit B, the test result is Fail. As a result, B is specified as the fault circuit block.
[0098]
Next, it is specified which scan FF among the scan FFs constituting the partial scan path 502 has propagated the fault. The partial scan path 502 includes a scan FF1 and a scan FF2. The shift cycle is 1 cycle with 4 clock cycles. Therefore, the shift counter 703 is composed of 2 bits. The value captured by the scan FF 1 is propagated to the output compression circuit 513 in the first clock cycle of the shift. Further, the value captured by the scan FF 2 in the second clock cycle of the shift is propagated to the output compression circuit 513. In the third and fourth clock cycles of the shift, the value from the PRPG 512 is directly transmitted to the output compression circuit 513. The first clock cycle of the shift period is selected as the mask release time, and a 2-bit value “01” is given as the mask release time information 704. When the value of the shift counter 703 matches the value given as the mask release time information 704, the output mask release enable signal 709 from the mask release enable signal generation circuit 702 becomes “1”, and the mask for the scan path is released. The Here, all the partial scan paths other than the partial scan path 502 are bypassed from the scan path (that is, the partial scan path 502 is set as the scan pattern application target), and only the first clock cycle of the shift period is removed from the scan path. The signal is set to pass to the output compression circuit 513, the diagnostic mode signal 708 is set to “1”, and the built-in self test is executed. The failure propagates to scan FF1. The fault propagated to the scan FF 1 is propagated to the output compression circuit 513 in the first clock cycle of the shift. As a result, the test result is Fail, and the scan FF 1 is specified as the FF in which the failure is observed.
[0099]
【The invention's effect】
According to the present invention, even when a malfunction occurs in the shift operation of a part of the scan FFs in the scan chain, the influence of the indefinite value is reduced by bypassing the corresponding scan FF from the scan signal application target, The self-embedding test can be executed in a state where the decrease in detection rate is small.
[0100]
In addition, by locking the state of the scan FF or the output of the partial scan path removed from the scan chain by bypass, an indefinite value is propagated from the bypass partial scan path to the combinational circuit. As a result, it is possible to prevent the inconvenience that the indefinite value is propagated to the partial scan path to be tested that is not bypassed, and to further suppress the decrease in the failure detection rate in the built-in self test.
[0101]
Further, according to the fault diagnosis method for a semiconductor integrated circuit with a built-in self-test circuit in the present invention, a circuit block in which a fault exists can be specified, and only a specific scan FF value is propagated to the output compression circuit at the time of scan-out. By controlling, it is possible to further advantageously narrow down the failure location.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to a second embodiment of the present invention.
FIG. 3 is a circuit configuration diagram showing a detailed configuration of a selector in a semiconductor integrated circuit with a built-in self-test circuit according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to a third embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to a fourth embodiment of the present invention.
FIG. 6 is a flowchart showing a fault diagnosis method for specifying a fault circuit block in a semiconductor integrated circuit with a built-in self test circuit according to the fourth embodiment of the present invention;
FIG. 7 is a flowchart showing a fault diagnosis method for specifying a fault circuit block using a binary search method for a semiconductor integrated circuit with a built-in self-test circuit according to a fourth embodiment of the present invention;
FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self test circuit according to a fifth embodiment of the present invention.
FIG. 9 is a flowchart showing a failure diagnosis method for specifying a scan FF in which a failure is observed in a semiconductor integrated circuit with a built-in self test circuit according to a fifth embodiment of the present invention;
FIG. 10 is a block diagram showing a configuration of a semiconductor integrated circuit with a built-in self-test circuit in the prior art.
[Explanation of symbols]
201-202, 301-302, 401-402, 509-510 Scan campus
203 to 208, 303 to 308, 403 to 408, 501 to 504 Partial scan path
209-214, 309-310, 409-414, 505-508 selector
215 to 220, 311 to 316, 415 to 420, 511 combination circuit
221, 317, 421, 512 PRPG (pattern generation circuit)
222, 318, 422, 513 MISR (output compression circuit)
229, 325, 429, 514 Partial scan path selection information
519 to 522 AND gate
523 External reset signal
702 Mask release permission signal generation circuit
703 Shift counter
704 Mask release time information
705 comparator
706 OR gate
707 Inverter
708 Diagnostic mode signal
709 Mask release enable signal
710 Mask circuit

Claims (9)

A scan path for testing a semiconductor integrated circuit, a combinational circuit to be a scan test, a pattern generation circuit for supplying a test pattern to the scan path, and an output compression circuit for compressing an output response from the scan path The semiconductor integrated circuit with a built-in self-test circuit is provided, wherein the scan path is formed by alternately connecting partial scan paths and selectors configured by serially connecting one or more scan FFs. The shift operation is performed by bypassing scan FFs included in one or more partial scan paths counted from the scan-in side of the scan path according to partial scan path selection information given as a selection signal of the selector. A semiconductor integrated circuit with a built-in self-test circuit. A scan path for testing a semiconductor integrated circuit, a combinational circuit to be a scan test, a pattern generation circuit for supplying a test pattern to the scan path, and an output compression circuit for compressing an output response from the scan path A semiconductor integrated circuit with a built-in self-test circuit, wherein the scan path includes a serial scan path formed by serially connecting one or more scan FFs, and a selector connected to the final stage. The shift operation is performed by bypassing scan FFs included in one or more partial scan paths, counted from the scan-out side of the scan path, according to partial scan path selection information provided as a selection signal of the selector. A semiconductor integrated circuit with a built-in self-test circuit. A scan path for testing a semiconductor integrated circuit, a combinational circuit to be a scan test, a pattern generation circuit for supplying a test pattern to the scan path, and an output compression circuit for compressing an output response from the scan path The semiconductor integrated circuit with a built-in self-test circuit is provided, wherein the scan path is formed by alternately connecting partial scan paths and selectors configured by serially connecting one or more scan FFs. A semiconductor integrated circuit with a built-in self-test circuit, which performs a shift operation by bypassing a scan FF included in an arbitrary partial scan path according to partial scan path selection information given as a selection signal of the selector. 4. The semiconductor integrated circuit with a built-in self-test circuit according to claim 1, wherein an indefinite value is detected from a scan FF constituting the partial scan path bypassed from a scan pattern application target. A semiconductor integrated circuit with a built-in self-test circuit, wherein the reset or set of the scan FF of the bypassed partial scan path is not released so as not to propagate to a combinational circuit. 4. The semiconductor integrated circuit with a built-in self-test circuit according to claim 1, wherein an indefinite value is detected from a scan FF constituting the partial scan path bypassed from a scan pattern application target. A semiconductor integrated circuit with a built-in self-test circuit, wherein the data output of the scan FF of the bypassed partial scan path is fixed so as not to propagate to a combinational circuit. 6. The semiconductor integrated circuit with a built-in self-test circuit according to claim 1, wherein a signal from the scan path to the output compression circuit is passed at a selected time, and at other times. A mask circuit having a function of masking a signal from a scan path to the output compression circuit is built in, and means for propagating only the influence of a failure propagated to a specific scan FF during a self test to the output compression circuit is provided. A semiconductor integrated circuit with a built-in self-test circuit. A fault diagnosis method for a semiconductor integrated circuit with a built-in self-test circuit according to any one of claims 1 to 6,
Selecting a partial scan path (a);
Performing a self test by bypassing a partial scan path other than the partial scan path selected in step (a) from the scan path; and
And (c) determining whether all the partial scan paths are selected in the step (a),
The step (b) is executed after the step (a), and after the step (b), if the test result of the step (b) is successful, the step (c) is executed, and the step (b) A failure diagnosis method for a semiconductor integrated circuit with a built-in self-test circuit, wherein a circuit block including a failure portion is specified when the test result of b) fails. A fault diagnosis method for a semiconductor integrated circuit with a built-in self-test circuit according to any one of claims 1 to 6,
Dividing a plurality of partial scan paths in the circuit into two groups A and B;
Performing a built-in self-test by bypassing a partial scan path included in group A from the scan path; and
Determining whether group B includes more than one partial scan path (c);
Dividing the partial scan path included in group B into two groups A and B anew (d);
Determining whether group A includes two or more partial scan paths (e);
Dividing the partial scan path included in group A into two groups A and B anew (f);
A step (g) of performing a self-test by bypassing all the partial scan paths except the partial scan path included in the group A from the scan path,
First, the step (a) is executed, and then the step (b) is executed. If the test result of the step (b) is unsuccessful, then the step (c) is executed, and the step (b) If the test result of step (c) is successful, then step (e) is executed. If the determination result of step (c) is affirmative, step (d) is executed subsequently, and step (c) If the determination result is negative, the faulty circuit block is specified. If the determination result in step (e) is affirmative, step (f) is subsequently executed, and the determination result in step (e) is negative. In the case of the target, the fault diagnosis of the semiconductor integrated circuit with the built-in self-test circuit is characterized in that the step (g) is continuously executed and if the test result in the step (g) fails, the fault circuit block is specified. Method In a failure diagnosis method, the method according to claim 7 or claim 8 is applied to a semiconductor integrated circuit with a built-in self-test circuit according to claim 6.
A step (d) of selecting a time at which to unmask; and
(E) performing a built-in self-test by turning on the diagnostic mode signal so that the signal from the scan path is passed to the output compression circuit only at the mask release time selected in the step (d),
A step (f) of determining whether the mask release is performed at all times selectable in the step (e) is added;
After the faulty circuit block is identified, the step (d) is executed, the step (e) is executed after the step (d), and the test result of the step (e) is successful after the step (e). In the case of step (f), if the test result in step (e) is unsuccessful, the fault diagnosing method for a semiconductor integrated circuit with a built-in self-test circuit is characterized in that the scan FF that detects the failure is specified .

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