JP4031954B2 - Integrated circuit diagnostic device and diagnostic method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an apparatus and a diagnostic method for detecting a manufacturing failure (fault) of an integrated circuit such as an LSI (Large Scale Integration) and performing a fault diagnosis capable of specifying the occurrence position.To the lawRelated.
[0002]
[Prior art]
Detection of a manufacturing failure of an integrated circuit such as an LSI is performed by applying an appropriate signal value to an LSI input pin using a tester (ATE; Automatic Test Equipment) and comparing the signal value appearing at the output pin with an expected result. It is done by doing. The signal value applied to the input pin and the expected value that should appear at the output pin are collectively called a test pattern (test pattern).
[0003]
Defects that occur in the LSI due to LSI manufacturing defects are called failures, and many test patterns are required to verify all possible failures within the LSI. The ratio of the number of faults that can be verified by a certain test pattern to the total number of faults assumed inside the LSI is called a diagnostic rate (or detection rate), and is used as a measure for measuring the quality of the test pattern. Yes. When an LSI includes sequential circuit elements [flip-flop (F / F), latch, and RAM (Random Access Memory)], the complexity of test pattern creation increases dramatically.
[0004]
Therefore, in LSI, scan design is generally performed. In a scan-designed LSI, a shift register (referred to as a scan path) is formed using sequential circuit elements (mainly F / F) inside the LSI, and a desired value is stored in the shift register during testing. Are shifted in, and the value of the shift register is read out after the clock is applied.
[0005]
In such a circuit, a deterministic stored pattern test (hereinafter referred to as DSPT (Deterministic Stored Pattern Test)) is widely adopted. The DSPT is performed by storing a test pattern created by an automatic test pattern generator (hereinafter referred to as ATPG (Automatic Test Pattern Generator)) in a tester (ATE).
[0006]
FIG. 6 is a diagram for explaining the conventional scan design. In FIG. 6, the concept of the scan design is shown as a block diagram. As shown in FIG. 6, in an LSI for which scan design has been performed, a plurality of scan paths (shift registers), which are paths for testing the LSI, are formed. Each scan path is formed using a plurality of F / Fs which are storage elements. Then, the test pattern is shifted in from one end side (left side in FIG. 6) of each scan path, and the test result is output from the other end side (right side in FIG. 6). In FIG. 6, four scan paths are illustrated, and each scan path is formed by connecting eight F / Fs in series.
[0007]
However, since the number of sequential circuit elements included therein has increased greatly with the increase in the degree of integration of LSIs in recent years, all the sequential circuit elements that constitute a scan path by DSPT as described above are used. If setting and reading are repeatedly executed for each test pattern, not only the test time increases, but also the tester memory capacity increases due to an increase in test data amount. Therefore, execution of tests by DSPT has become difficult. In particular, a tight tester memory capacity due to an increase in the amount of test data significantly increases test costs such as memory expansion and tester upgrades.
[0008]
In order to solve such a problem, a built-in self test (hereinafter referred to as BIST (Built-In Self Test)) has been performed. In BIST, as shown in FIG. 7, the pattern generated by the pseudo-random pattern generator 2 is applied to the internal circuit (scan path) of the LSI, and the output result from the internal circuit is verified and stored by the output verifier 7. Is done. As the pseudorandom pattern generator 2 and the output verifier 7, a linear feedback shift register (hereinafter referred to as LFSR) is often used. In particular, the output verifier 7 compresses and stores the output result as a signature. This is called a multi-input signature register (hereinafter referred to as MISR). FIG. 7 is a diagram for explaining a conventional BIST circuit. Further, in FIG. 7, eight scan paths are illustrated between the pseudorandom pattern generator 2 and the output verifier 7, and each scan path is formed by connecting four F / Fs in series. .
[0009]
In the BIST circuit, since a pseudo random number pattern generator is mounted inside the LSI, an extremely large number of test patterns can be generated in a short time, and it is not necessary to store input test patterns in an external tester. In addition, since the test results are compressed and stored by MISR, the amount of data loaded to the tester can be greatly reduced. Furthermore, in the BIST circuit, the number of scan paths can be increased to speed up the shift-in / shift-out operations to the scan paths, thereby shortening the test time.
[0010]
[Problems to be solved by the invention]
By adopting BIST as described above, the problems of DSPT can be improved, but there are some problems.
In other words, since BIST uses a pseudo-random pattern, there is a problem in test quality (diagnosis rate, failure detection rate). In order to increase the diagnosis rate, it is necessary to apply DSPT as an additional test, or to insert test points that increase controllability and observability in the circuits inside the LSI.
[0011]
In BIST, since output data is compressed and stored in MISR, if an indefinite value (X value) is captured even once, all registers in MISR become indeterminate and are held in registers. The value that was being used will be destroyed, making it impossible to test.
[0012]
In general, the sequential circuit elements including the RAM in the LSI are in an indefinite state when the power is turned on. Therefore, a pattern for initializing these sequential circuit elements is applied in advance, or a circuit is provided so that the indefinite state does not propagate to the MISR. It was necessary to devise. In addition to this, a strict design constraint is imposed on the designer in order to apply BIST to an actual circuit, such as preventing a bus conflict or a floating state from occurring due to a random number pattern at the time of bus design. In addition to this, the insertion of the BIST additional circuit and the test point causes problems of circuit area overhead and performance degradation.
[0013]
Therefore, the inventors of the present application have solved the problems of DSPT and BIST described above in Japanese Patent Application No. 2000-372231, and have achieved a reduction in test time and a reduction in the amount of test data, as well as a high quality test (diagnosis rate). This is a technology that enables high- FIG. 8 (block diagram) shows the configuration of a test circuit to which the technology is applied.
[0014]
The test circuit shown in FIG. 8 is based on a BIST circuit similar to that shown in FIG. 7 on the LSI, and further includes a pattern corrector 4 and an indeterminate mask device 5 added to the BIST circuit. Then, the pattern generated by the pseudo random pattern generator (LFSR) 2 is corrected to a pattern equivalent to ATPG by the pattern corrector 4 and then shifted into the scan path. After the test clock is applied, the output from the scan path is compressed and stored in the MISR in the output verifier 7 via the indeterminate mask unit 5, but the indefinite value (X value) in the output is indefinite. Mask processing is performed by the mask device 5. In FIG. 8, eight scan paths are illustrated between the pattern corrector 4 and the indeterminate mask unit 5, and each scan path is formed by connecting four F / Fs in series.
[0015]
When a test created by shifting a pattern created by ATPG into a scan path, the number of F / Fs explicitly set to a value (1 or 0) based on the pattern is the total number of F / Fs Is very small (several percent). Therefore, in the test circuit shown in FIG. 8, only the value to be explicitly set to the F / F as described above is given to the pattern corrector 4 from the external tester using the control signal, and this pattern corrector 4 Thus, the pseudo random number pattern from the pseudo random number pattern generator 2 can be changed to a high quality pattern equivalent to ATPG. In addition, by blocking ingestion of indefinite values into the MISR with the indeterminate mask unit 5, the design can be performed so that one of the BIST design constraints can be satisfied easily and reliably, greatly reducing the burden on the designer. Is done.
[0016]
By the way, in the LSI test method in which the output result is compressed and stored in the MISR as in the BIST circuit shown in FIG. 7 or the test circuit shown in FIG. 8, the main purpose is to determine whether the LSI to be tested is good or bad. However, in an actual LSI manufacturing site, it is sometimes necessary to investigate the cause of the failure of an LSI that has been determined to be defective in order to solve problems in the LSI manufacturing process and improve yield. In that case, it is necessary to specify where the defect exists in the LSI.
[0017]
In general, failure diagnosis refers to specifying a failure location based on a test pattern given by a tester and information on a portion where the observed value and the expected value by the tester do not match. In DSPT, since the output can be observed for each test pattern, failure diagnosis can be performed relatively easily. Faults that can be detected by each DSPT test pattern and the detection location (F / F) can be found by performing a fault simulation, so that it is possible to narrow down candidate faults based on the mismatch information of the tester. .
[0018]
On the other hand, in the BIST circuit shown in FIG. 7 and the test circuit shown in FIG. 8, the output result is compressed and stored in the MISR of the output verifier 7, and the MISR value is read out after the test is completed. Become. That is, since the output result is compressed, the failure location cannot be specified even if the presence or absence of the failure can be determined. Furthermore, in tests such as BIST, the speed of the test is increased by increasing the number of scan paths. Observing the output of all scan paths with external pins is not possible due to the limitation of the number of LSI pins. It is possible, that is, failure diagnosis is impossible.
[0019]
  The present invention has been devised in view of such problems, and detects manufacturing defects (failures) in integrated circuits even when the output from the scan path is compressed and stored or when the number of scan paths is large. Integrated circuit diagnostic device and diagnostic method that enable identification of the location of the occurrenceThe lawThe purpose is to provide.
[0020]
[Means for Solving the Problems]
  In order to achieve the above object, an integrated circuit diagnostic apparatus according to the present invention (Claim 1) includes a pattern generator incorporated in an integrated circuit to generate a test pattern and a sequential circuit element in the integrated circuit in parallel. And a plurality of shift registers, each of which is shifted in the test pattern generated by the pattern generator, and a plurality of outputs each shifted out from the plurality of shift registers are compressed as a signature and integrated. An output verifier that outputs to the outside of the circuit; and an output compressor that compresses a plurality of outputs shifted out from the plurality of shift registers into Hamming code check bits and outputs the compressed bits to the outside of the integrated circuit;A diagnostic means for performing failure diagnosis by comparing the output expected value obtained in advance with the output from the output compressor, and the diagnostic means performs an exclusive OR operation between the output expected value and the check bit. Is calculated and the syndrome is acquired, and when there is one failure location, the shift register in which the failure exists is specified based on the syndrome and the error vector corresponding to the syndrome obtained in advance.It is characterized by that.
[0022]
  In addition, the integrated circuit diagnosis method of the present invention (claims)3) Generates a test pattern with a pattern generator incorporated in the integrated circuit, and the test pattern generated by the pattern generator is shifted in parallel by sequential circuit elements inside the integrated circuit. A plurality of outputs respectively shifted into and out of the plurality of shift registers are compressed as signatures and output to the outside of the integrated circuit, and shifted out from the plurality of shift registers, respectively. Multiple outputs are compressed into Hamming code check bits and output to the outside of the integrated circuit, the expected output value obtained in advance and the integrated circuitA syndrome is obtained by calculating an exclusive OR with the output check bit, and based on the syndromePerform fault diagnosisAt the same time, as a result of the failure diagnosis, if there is one failure location, the shift register in which the failure exists is specified based on the syndrome and the error vector corresponding to the syndrome obtained in advance.It is characterized byThe
[0023]
  On the other hand, the integrated circuit diagnostic device of the present invention (claims)2) Includes at least one EOR having a pattern generator and a plurality of shift registers similar to those described above, and compressing and outputting a plurality of outputs shifted out from the plurality of shift registers to the outside of the integrated circuit. A (exclusive OR) tree circuit and a control circuit capable of enabling one of the plurality of outputs input to the EOR tree circuit;A diagnostic means for performing failure diagnosis by comparing an expected output value obtained in advance with an output from the EOR tree circuit, and the control circuit validates the plurality of outputs one by one, and the EOR tree A circuit compresses the output validated by the control circuit and sequentially outputs the compressed output to the outside of the integrated circuit, and the diagnostic means determines the fault in the plurality of shift registers based on the output from the EOR tree circuit. Diagnose one by one and identify the shift register where the fault existsIt is characterized by that.
[0025]
  In addition, the integrated circuit diagnosis method of the present invention (claims)4) Generates a test pattern with a pattern generator incorporated in the integrated circuit, and the test pattern generated by the pattern generator is shifted in parallel by sequential circuit elements inside the integrated circuit. Each of the plurality of outputs shifted in and out of the plurality of shift registers is validated one by one, and the validated output is compressed by an EOR (exclusive OR) tree circuit. Output sequentially to the outside of the integrated circuit, compare the expected output value obtained in advance with the output from the EOR tree circuit, and perform fault diagnosisStep by step to identify the shift register where the fault existsIt is characterized by doingThe
[0026]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[1] Description of the first embodiment
In order to perform fault diagnosis, as with DSPT, match / mismatch information for each test pattern (information on whether the scan path output corresponding to each test pattern matches the expected value) is required. In BIST, since the test path does not compare the scan path output with the expected value for each test pattern, it is necessary to read out the F / F value for each test pattern. However, as described above, in BIST, the parallelism of internal scan paths is increased in order to perform high-speed tests, and external output pins for all scan paths are prepared by limiting the number of input / output pins of the LSI. It is impossible. Therefore, a mechanism for compressing information of a large number of scan paths and observing with a small number of external output pins is required. The first embodiment of the present invention provides such a mechanism.
[0027]
FIG. 1 is a block diagram showing the configuration of an integrated circuit diagnostic apparatus according to a first embodiment of the present invention. As shown in FIG. 1, the diagnostic apparatus according to the first embodiment includes a pseudo-random pattern generator ( A pattern generator (LFSR) 2, a plurality of scan paths, an output verifier (MISR) 7 and an output compressor 10 are provided. This diagnostic apparatus is incorporated in an LSI 1A that is an integrated circuit to be tested.
[0028]
The LSI 1A includes a plurality of F / Fs (sequential circuit elements). In the LSI 1A, a plurality of scan paths (shift registers) are formed in parallel by these F / Fs. . In the example shown in FIG. 1, eight scan paths are formed in parallel, and each scan path is formed by connecting four F / Fs in series.
[0029]
Also in the diagnosis apparatus of the first embodiment, the patterns generated by the pseudorandom pattern generator 2 are shifted into the scan paths, and the output results from the scan paths are compressed and stored by the output verifier 7. It is like that. The output verifier 7 is composed of a plurality of exclusive OR (EOR) circuits and a plurality of registers, and the output results from each scan path are compressed (encoded) and stored as signatures, and a predetermined test pattern is stored. The output result for is finally output as an 8-bit encoded value.
[0030]
As shown in FIG. 1, the output compressor 10 includes exclusive OR circuits (EOR circuits) 11 to 21, and a plurality of outputs (8-bit data in FIG. 1) shifted out from a plurality of scan paths, respectively. ) Are compressed using the Hamming code check bits (4 bits in FIG. 1) and output to the outside of the LSI 1A. That is, the output compressor 10 corresponds to a check bit of the Hamming code, and is configured by EOR circuits 11 to 21 that realize the check bit of the Hamming code.
[0031]
The Hamming code is a kind of error correction code, and can correct a 1-bit error. In the Hamming code, error correction is performed by adding check bits to actual information bits. When the information bits are 4 bits (x1, x2, x3, x4), 3 bits (y1, y2, y3) are required as check bits, and an example of error correction in this case is shown in FIG. FIG. 2 is a diagram for explaining a compression method (an example of error correction using a Hamming code) using check bits of a Hamming code in the first embodiment.
[0032]
In the example shown in FIG. 2, as described above, the information bits are 4 bits (x1, x2, x3, x4), the check bits are 3 bits (y1, y2, y3), and the check bits (y1, y2, y3) Is calculated from the information bits (x1, x2, x3, x4) based on the formula shown in FIG. In this case, as shown in FIG. 2, the syndrome is 3 bits (z1, z2, z3), and an error vector corresponding to the syndrome is given in advance.
[0033]
At this time, if the original data is (0,1,0,0), (1,0,1) should be obtained as the check bit. That is, when (0,1,0,0) is expected as a scan path output by a certain test pattern, (1,0,1) should be output as a check bit output from the output compressor 10. Therefore, (1,0,1) is obtained in advance as the expected output value.
[0034]
Thus, when (0,1,0,0) is expected as the scan path output, an error is mixed due to a failure, for example, x3 becomes “1”, and (0,1,1,0, 0) ) Is obtained. In this case, (0,1,1) is obtained as the check bit (output of the output compressor 10), and this check bit (0,1,1) is exclusive of the expected output value (1,0,1). Syndrome (1,1,0) is obtained by calculating the logical OR (EOR).
[0035]
The error vector (x1, x2, x3, x4, y1, y2, y3) corresponding to the obtained syndrome (1,1,0) is (0,0,1,0,0) as shown in FIG. , 0,0), and in Hamming code, by calculating the exclusive logic of (x1, x2, x3, x4) in this error vector and the scan path output (0,1,1,0), The original data can be restored.
However, in the first embodiment, it is not necessary to restore the original data, and when a syndrome is calculated, a bit with an error, that is, a scan path in which a fault location exists is specified.
[0036]
In the example shown in FIG. 1, the information bits are 8 bits (x1, x2,..., X8). In this case, the check bits are 4 bits (y1, y2, y3, y4). The above-described method is extended and applied. That is, the 8-bit scan path output (x1, x2,..., X8) is generated by the output compressor 10 (EOR circuits 11 to 21) by the 4-bit Hamming code check bit data (y1, y2, y3,. y4) and output to the outside of the LSI 1A.
[0037]
In the first embodiment, a tester (diagnostic means) (not shown) is provided, and the output (check bit data (y1, y2, y3, y4)) from the output compressor 10 is input to this tester. It has become. In the tester, inspection bit data to be obtained when there is no failure (error) is stored in advance as an expected output value, and the tester outputs the expected output value and the output from the output compressor 10 (inspection bit data). Compare and perform fault diagnosis.
[0038]
Specifically, as described above, an exclusive OR of the output expected value and the check bit data from the output compressor 10 is calculated to obtain a syndrome, and a failure location is determined based on the syndrome. If there is no failure, the expected output value matches the check bit data from the output compressor 10, and each bit of the syndrome becomes “0”. When a failure exists in one of the plurality of scan paths, the output expected value and the check bit data from the output compressor 10 are inconsistent, and based on the error vector corresponding to the obtained syndrome, 8 It is possible to specify an error of one bit in the scan path output (x1, x2,..., X8) for bits. That is, it is possible to specify one scan path (failure location) where a failure exists.
[0039]
If a failure occurs simultaneously in two or three scan paths, the output result of the output compressor 10 does not match the expected value of the tester, as in the case where a failure occurs in one scan path. Therefore, it is not always true that a failure exists in the scan path obtained by the above method, and the failure location (scan path where the failure exists) cannot be specified. In this case, it is only possible to point out the presence of a failure. Furthermore, when failures occur at four or more locations at the same time, the output result of the output compressor 10 may coincide with the expected value of the tester despite the presence of the failure, and the presence or absence of the failure cannot be pointed out correctly. Sometimes.
[0040]
As described above, according to the first embodiment of the present invention, the plurality of outputs shifted out from the plurality of scan paths by the output compressor 10 are compressed and encoded into the check bits of the Hamming code, and then the LSI 1A Since the data is output to the outside, it is possible to observe information on a large number of scan paths with a small number of external output pins (four in the example of FIG. 1). Accordingly, diagnosis of the LSI 1A to which a test such as BIST is applied can be realized with a small circuit overhead.
[0041]
In failure diagnosis, it is necessary to compare expected values for each test pattern with a tester. However, since information on a large number of scan paths is compressed and encoded, diagnosis faster than DSPT is possible. Even when the output from the scan path is compressed and stored or when the number of scan paths is large, not only the manufacturing failure (failure) of the LSI 1A is detected, but if the failure location is one location, The generation position (scan path) can be specified. Furthermore, in the first embodiment, when a failure occurs in two or three scan paths, only the presence of the failure is pointed out. However, for the LSI 1A in the mass production stage, the presence of the failure is indicated. It is considered that a very effective effect can be obtained even if only the indication is made.
[0042]
As indicated by a two-dot chain line in FIG. 1, a plurality of test patterns generated by the pseudo random number pattern generator 2 are corrected in the LSI 1A by external input, as in the test apparatus described above with reference to FIG. Pattern corrector 4 that is input to the scan path (shift register) and an indeterminate mask that is output to output verifier 7 and output compressor 10 after masking indeterminate values (X values) being output from a plurality of scan paths. A vessel 5 may be further incorporated.
[0043]
At this time, the test pattern generated by the pseudo random number pattern generator 2 is input to the pattern corrector 4. A control signal from a tester (not shown) is input to the pattern corrector 4 through a control input pin or the like, and this pattern corrector 4 is for an F / F that needs to set a value according to the control signal. Only the value is corrected, and the value is input / set to the head F / F of each scan path.
[0044]
The indeterminate mask device 5 masks the indefinite value (X value) of the final F / F values of each scan path according to a control signal input from a control input pin or the like, thereby bringing the indeterminate state into a specified state. After the conversion, the final F / F value of each scan path is input to the output verifier 7 and the output compressor 10.
As described above, the test pattern generated by the pseudo random number pattern generator 2 is corrected by the pattern corrector 4 and input to a plurality of scan paths, thereby increasing the number of scan paths and the number of scan path stages (F / F in each scan path). The test time of the LSI 1A can be greatly shortened.
[0045]
In addition, the problems of DSPT and BIST are solved, and a test pattern that enables a high-quality test that takes advantage of both of them in a short time can be generated. At that time, only the meaningful data part (F / F information whose value needs to be set) is supplied and corrected from the tester (external input), so the amount of data stored in the tester is greatly reduced. You can also. Therefore, a high quality test can be performed without imposing strict design rules on the designer and without requiring an expensive tester.
[0046]
Further, the indeterminate value (X value) in the output from the plurality of scan paths formed by the F / F in the LSI 1A is masked by the indeterminate mask unit 5, and the masked output result is verified by the output verifier 7. Even if the output result from the F / F is compressed and read to the outside, the indefinite value does not ruin the compression result.
[0047]
[2] Description of the second embodiment
In the first embodiment described above, when a plurality of failures occur simultaneously, the failure location cannot be specified. This is likely to occur at the start of a new manufacturing process and there is a high need for fault diagnosis. Therefore, in the second embodiment and the third embodiment, all the scan paths in which a failure exists can be correctly specified according to the necessity.
[0048]
FIG. 3 is a block diagram showing the configuration of the integrated circuit diagnostic apparatus according to the second embodiment of the present invention. As shown in FIG. 3, the diagnostic apparatus according to the second embodiment is similar to the first embodiment. Are provided with a pseudo random number pattern generator 2, a plurality of scan paths and an output verifier 7, and an output selector 30 instead of the output compressor 10. This diagnostic apparatus is incorporated in the LSI 1B which is an integrated circuit to be tested.
[0049]
Similar to the LSI 1A of the first embodiment, the LSI 1B includes a plurality of F / Fs (sequential circuit elements). In the LSI 1B, a plurality of scan paths (shift registers) are generated by these F / Fs. ) Are formed in parallel. In the example shown in FIG. 3 as well, eight scan paths are formed in parallel, and each scan path is formed by connecting four F / Fs in series.
[0050]
Also in the diagnostic apparatus of the second embodiment, the patterns generated by the pseudorandom pattern generator 2 are shifted into the scan paths, and the output results from the scan paths are compressed and stored by the output verifier 7. It is like that. This output verifier 7 is composed of a plurality of EOR circuits and a plurality of registers, compresses (encodes) and stores the output results from each scan path as signatures, and outputs the output results for a predetermined test pattern as final Thus, it is output as an 8-bit encoded value.
[0051]
  The output selector 30 is3As shown in FIG. 4, the EOR (exclusive OR) tree circuits 31 and 32 and the control circuit 40 are included.
  Here, the EOR tree circuit 31 includes three exclusive OR circuits (EOR circuits) 33, 34, and 35, and compresses the outputs shifted out from the upper four scan paths shown in FIG. Similarly, the EOR tree circuit 32 is constituted by three exclusive OR circuits (EOR circuits) 36, 37, and 38, and the lower four scan paths shown in FIG. The output shifted out from each of the signals is compressed and output to the outside of the LSI 1B.
[0052]
The control circuit 40 includes a decoder 41 and eight OR circuits (OR circuits) 42 to 49, and outputs a plurality (four in this case) of outputs to the EOR tree circuits 31 and 32. It is to activate one of them.
[0053]
Each of the OR circuits 42 and 43 inputs the logical sum of the outputs of the first and second scan paths from the top shown in FIG. 3 and the selection signal from the decoder 41 to the two input terminals of the EOR circuit 33. is there. Similarly, each of the OR circuits 44 and 45 inputs the logical sum of the outputs of the third and fourth scan paths from the top shown in FIG. 3 and the selection signal from the decoder 41 to the two input terminals of the EOR circuit 34. Each of the OR circuits 46 and 47 outputs the logical sum of the outputs of the fifth and sixth scan paths from the top shown in FIG. 3 and the selection signal from the decoder 41 to two input terminals of the EOR circuit 36, respectively. OR circuits 48 and 49 respectively output the logical sum of the outputs of the seventh and eighth scan paths from the top and the selection signal from the decoder 41 shown in FIG. Input to the input terminal.
[0054]
The decoder 41 gives selection signals corresponding to the control signal from the outside of the LSI 1B to the OR circuits 42 to 49 so that only the output of the scan path to be validated is inputted to the EOR tree circuits 31 and 32.
[0055]
In the second embodiment, only one of the outputs of the upper four scan paths input to the EOR tree circuit 31 is validated, and at the same time, the output of the lower four scan paths input to the EOR tree circuit 32 is output. In order to validate only one, the decoder 41 outputs only one of the selection signals input to the upper four OR circuits 42 to 45 from “1” to “0” in accordance with a control signal from the outside of the LSI 1B. In addition, only one of the selection signals input to the lower four OR circuits 46 to 49 is changed from “1” to “0”. The OR circuits 42 to 49 to which the selection signal “0” is input from the decoder 41 allow passage of the scan path output input to the OR circuits 42 to 49, and pass the scan path output to the EOR tree circuit 31 or 32. Will be input. The outputs of the OR circuits 42 to 49 to which the selection signal “1” is input are always “1”, and the scan path output cannot pass through the OR circuits 42 to 49.
[0056]
Therefore, in the second embodiment, in one test, two outputs are selected and validated from the outputs of the eight scan paths, and are externally connected to the LSI 1B from the two external output pins through the EOR tree circuits 31 and 32, respectively. Will be output. That is, if the test is repeated four times, the test for all eight scan paths can be completed.
[0057]
Also in the second embodiment, a tester (diagnosis means) (not shown) is provided, and the output from the output selector 30 is input to this tester. The tester stores in advance an expected output value that should be obtained when there is no failure (error), and the tester compares the expected output value with the output from the output selector 30 to perform failure diagnosis.
[0058]
With the above configuration, in the second embodiment, when diagnosing the LSI 1B to which a test such as BIST is applied, the control circuit 40 is input to the EOR tree circuits 31 and 32 regardless of the presence or absence of simultaneous failure. Each of the EOR tree circuits 31 and 32 compresses the output validated by the control circuit 40 and sequentially outputs it to the outside of the LSI 1B. The tester outputs the expected output value. Are compared with the outputs from the EOR tree circuits 31 and 32, and a fault diagnosis is performed. An output scan path that does not match the expected output value is identified as a scan path in which a fault exists.
[0059]
By repeating such processing a plurality of times (four times in the LSI 1B of the second embodiment shown in FIG. 3), diagnosis is performed for all scan paths, and all fault locations (scan paths where a fault has occurred) are specified. It becomes possible to do. That is, in the first test, the selection signal of the decoder 41 is set so as to enable only the first scan path connected to each EOR tree circuit 31, 32, and the test for the first scan path is performed. Done. Then, a scan path in which a fault exists is specified based on the mismatch information in the tester of each test pattern.
[0060]
At this time, the group to which the scan path belongs (the group of the EOR tree circuit 31 or the group of the EOR tree circuit 32) is specified based on the mismatch information from the two external output pins provided corresponding to the EOR tree circuits 31 and 32. Further, since it can be recognized from the selection signal from the decoder 41 that the first scan path of each group is validated, the scan path where the fault exists can be specified.
[0061]
By repeating the same test n times (n = 4 in the second embodiment) until the nth scan path connected to each EOR tree circuit 31, 32, all the scan paths in which a fault exists are specified. It becomes possible to do.
It should be noted that the expected output value of n tests needs to be recalculated according to the setting of the diagnostic mask device.
[0062]
As described above, according to the second embodiment of the present invention, the control circuit 40 validates the outputs input to the EOR tree circuits 31 and 32 from the plurality of scan paths one by one, and the validated output. Are compressed by the EOR tree circuits 31 and 32 and sequentially output to the outside of the LSI 1B. Therefore, it is possible to correctly specify all the scan paths in which a failure exists in the failure diagnosis of the LSI to which a test such as BIST is applied. it can. Therefore, even when a large number of failures exist at the same time when a new manufacturing process is started, it is possible to correctly and reliably perform failure diagnosis.
[0063]
[3] Description of the third embodiment
FIG. 4 is a block diagram showing the configuration of an integrated circuit diagnostic apparatus according to a third embodiment of the present invention. As shown in FIG. 4, the diagnostic apparatus according to the third embodiment includes the first embodiment and the first embodiment. A pseudo-random pattern generator (LFSR) 2, a plurality of scan paths (shift registers) and an output verifier (MISR) 7 similar to those of the second embodiment are provided, and a pseudo-random pattern generator 2 and a plurality of scan paths A pattern corrector 4 similar to that of the first embodiment is provided therebetween, and an indeterminate mask device 5 similar to that of the first embodiment is provided between the plurality of scan paths and the output verifier 7. This diagnostic apparatus is incorporated in the LSI 1C which is an integrated circuit to be tested.
[0064]
Similar to the LSI 1A of the first embodiment, the LSI 1C includes a plurality of F / Fs (sequential circuit elements). In the LSI 1C, a plurality of scan paths (shift registers) are generated by these F / Fs. ) Are formed in parallel. Also in the example shown in FIG. 4, eight scan paths are formed in parallel, and each scan path is formed by connecting four F / Fs in series.
[0065]
In the diagnostic apparatus according to the third embodiment, the test pattern generated by the pseudorandom pattern generator 2 is input to the pattern corrector 4. A control signal from a tester (not shown) is input to the pattern corrector 4 through a control input pin or the like, and this pattern corrector 4 is for an F / F that needs to set a value according to the control signal. Only the value is corrected, and the value is input / set to the head F / F of each scan path.
[0066]
The test pattern corrected in this way is shifted into the scan path, and the output result from each scan path is input to the indeterminate mask unit 5, and is input from the control input pin or the like in the indeterminate mask unit 5. According to the control signal, the indefinite state (X value) of the final F / F values of each scan path is masked to convert the indefinite state into a specified state, and then the final F / F of each scan path is changed. The value is input to the output verifier 7 and compressed and stored in the output verifier 7. As described above, the output verifier 7 includes a plurality of EOR circuits and a plurality of registers, and compresses (encodes) the output result from each scan path and stores it as a signature. The output result is finally output as an 8-bit encoded value.
[0067]
The indeterminate mask unit 5 includes a decoder 51, OR circuits (OR circuits) 52, 53, and 54, and an AND circuit (AND circuit) in order to mask indefinite values (X values) in outputs from a plurality of scan paths. 55 and a flip-flop (F / F) 62 are provided. In addition to receiving control signals (Control Signals) through the eight control input pins (b1 to b8), the indeterminate mask device 5 and the final F / of the eight scan paths # 0, # 1,. The output from F is input.
[0068]
The indeterminate mask unit 5 also controls the shift clock to the output verifier 7 (and the pseudorandom pattern generator 2) and the shift clock to the F / F on the scan path. When masking the indefinite state, the F / F on the scan path and the shift clock for the output verifier 7 (and the pseudo random number pattern generator 2) are suppressed, and the F provided after the final F / F on the scan path is suppressed. Only the shift clock for / F62 is applied.
[0069]
This F / F 62 holds the inverted state independently of the final F / F on the scan path. By adopting such a configuration, the overhead of the circuit slightly increases, but it becomes easy to completely separate the output verifier 7 and the scan paths # 0 to # 7 into a module. Thus, a reordering process for optimally changing the order of the scan F / F is possible in the layout for performing physical placement and routing.
[0070]
Further, the indeterminate mask device 5 has a decoder 51 that enables mask operation with the most significant bit (b1) of the control input and receives the lower 7 bits (b2 to b8) of the control input. Depending on the result of decoding by the decoder circuit 51, an indefinite value (X value) input from a specific one of the eight scan paths is converted into a “1” state value (or “0” state by the OR circuit 52). Value) and the indeterminate value is masked.
[0071]
That is, when “1” is input to the control input pin b1, the output of the OR circuit 53 becomes “1”, and therefore to the F / F on the scan path and the output verifier 7 (and the pseudo random number pattern generator 2). The shift clock (negative clock; Scan Clock) is suppressed, and the AND circuit 55 enters the through state by “1” of the control input pin b1. As a result, the logical sum of the output of the F / F 62 and the selection signal from the decoder 51 (the output of the OR circuit 54) is input to the OR circuit 52, and at the same time passes through the AND circuit 55 and is input to the F / F 62. Is done.
[0072]
Therefore, “1” is output from the decoder 51, and an indefinite value (X value) input to a specific one of the eight scan paths is converted into a “1” state value by the OR circuit 52. Indeterminate values can be masked. At the same time, if the F / F of another scan path also has an indefinite value, the output (undefined value) from that F / F is masked by the next shift clock. The pattern generation part and the output verification part are basically independent, but when both circuits are applied together, the lower 7 bits of the control input can be shared.
[0073]
In the third embodiment, the output verifier 7 performs the same function as the EOR tree circuits 31 and 32 described in the second embodiment, and the scan paths # 0 to # 7 (OR circuit 52) Each of the plurality of outputs shifted out is compressed and output to the outside of the LSI 1C.
[0074]
In addition, a function as a control circuit that can validate one of the outputs from the scan paths # 0 to # 7 input to the output verifier 7 and generation of a pseudo random number pattern in order to narrow down a pattern number in which a failure has occurred. In order to realize a function as a control circuit that validates the outputs from the scan paths # 0 to # 7 corresponding to the pattern numbers in a predetermined range generated by the device 2, the indefinite mask device 5 includes A flip-flop (initialization setting F / F) 57, an OR circuit (OR circuit) 61 and a multiplexer 56 are provided for each scan path, and a start counter 58, an end counter 59 and a NAND circuit 60 are provided. In the third embodiment, the same function as the output selector 30 described in the second embodiment is realized from the control circuit configured by these elements 57 to 61 and the output verifier 7 functioning as an EOR tree circuit. Has been.
[0075]
The initialization setting F / F 57 forms a scan path together with the F / F 57 for other scan paths, and is set to “0” or “1” by scan-in at the start of the test. At this time, “0” is set in the F / F 57 for the scan path to be validated, and “1” is set in the F / F 57 for the other scan paths.
[0076]
The start counter 58 is used together with the end counter 59 and the NAND circuit 60 to validate an output corresponding to a pattern number in a predetermined range. The first pattern number in the predetermined range is set, and the scan clock is set at the start of the test. And the output signal is switched from “0” to “1” when the counted value reaches the first pattern number as shown in FIG.
[0077]
The end counter 59 is used together with the start counter 58 and the NAND circuit 60 to validate an output corresponding to a predetermined range of pattern numbers. The “last pattern number + 1” in the predetermined range is set and the test is started. At the same time, the scan clock is counted, and as shown in FIG. 5, when the count value becomes “final pattern number + 1”, the output signal is switched from “1” to “0”.
[0078]
The NAND circuit 60 outputs a negative logical product of the output signal from the start counter 58 and the output signal from the end counter 59. As shown in FIG. 5, the output corresponding to the pattern number within a predetermined range is the scan path. Is output from the scan path, the output from the scan path is validated.
[0079]
Therefore, for example, when the outputs corresponding to all the test patterns are validated, zero is set in the start counter 58 and “maximum value of pattern number + 1” is set in the end counter 59. For example, when only the output corresponding to one test pattern is validated, the test pattern number is set in the start counter 58 and “the test pattern number + 1” is set in the end counter 59.
[0080]
  The OR circuit 61 includes an output signal from the initialization setting F / F 57 and a NAND circuit.60Outputs a logical sum with the output signal from, the initialization setting F / F 57 is set to “0”, and the NAND circuit60Only when the output signal from “0” is “0” (that is, when the pattern number is within a predetermined range), the logic is fed to the F / F 62 through the multiplexer 56.sumThe result “0” is output to validate the scan path. The multiplexer 56 selectively switches one of the output signal from the AND circuit 55 and the output signal from the OR circuit 61 according to the initialization signal Init, and outputs it to the F / F 62.
[0081]
Also in the third embodiment, a tester (diagnostic means) (not shown) is provided, and the output from the output verifier 7 is input to this tester. The tester stores in advance the expected output value that should be obtained when there is no failure (error), and the tester compares the expected output value with the output from the output verifier 7 to perform failure diagnosis.
[0082]
With the above-described configuration, in the third embodiment, when diagnosing the LSI 1C to which a test such as BIST is applied, scan-in scanning with respect to the initialization setting F / F 57 is performed regardless of the presence or absence of simultaneous failure. By setting “0” in the initialization setting F / F 57 corresponding to the power scan path, the output of the scan path is validated one by one, and the output verifier 7 compresses the validated output and the LSI 1C The output is sequentially output to the outside, and the tester compares the expected output value with the output from the output verifier 7 to perform failure diagnosis. An output scan path that does not match the expected output value is determined as a scan path where a fault exists. Identify.
[0083]
By repeating such processing a plurality of times (eight times in the LSI 1C of the third embodiment shown in FIG. 4), diagnosis is performed for all scan paths, and all fault positions (scan paths where a fault has occurred) are specified. It becomes possible to do.
That is, in the first test, “0” is set in the initial value setting F / F 57 corresponding to the scan path so as to validate only the first scan path connected to the output verifier 7. The scan path is tested.
[0084]
At this time, first, the values of the start counter 58 and the end counter 59 are set so as to validate the outputs corresponding to all the test patterns. As a result of the test using all the test patterns, when the tester finds that a failure exists in the scan path, the values of the start counter 58 and the end counter 59 are appropriately changed, and the output should be validated. Select the number range and test. By repeating such processing, the pattern numbers (pattern numbers where the failure has occurred) of the test pattern related to the occurrence of the failure are narrowed down, and the failure location on the scan path can be identified.
[0085]
By repeating the same test n times (n = 8 in the third embodiment) until the n-th scan path connected to the output verifier 7, all the scan paths in which a fault exists can be specified. In addition, the failure location on the scan path can be specified.
[0086]
As described above, according to the third embodiment of the present invention, as in the second embodiment, the outputs inputted to the output verifier 7 from the plurality of scan paths are validated one by one, and the validated outputs are obtained. Since the data is compressed by the output verifier 7 and sequentially output to the outside of the LSI 1C, it is possible to correctly specify all the scan paths in which a failure exists in the failure diagnosis of the LSI to which a test such as BIST is applied. Therefore, even when a large number of failures exist at the same time when a new manufacturing process is started, it is possible to correctly and reliably perform failure diagnosis.
[0087]
In the third embodiment, the scan path corresponding to the pattern number pattern within a predetermined range generated by the pseudo random number pattern generator 2 using the start counter 58, the end counter 59, the NAND circuit 60, and the OR circuit 61 is used. The output from can be validated to perform fault diagnosis. As a result, it is possible to narrow down the pattern numbers where the failure has occurred and specify the failure location on the scan path.
[0088]
On the other hand, in the third embodiment, a deterministic test pattern in which ATPG is generated by correcting the test pattern generated by the pseudorandom pattern generator 2 by the pattern corrector 4 and inputting it to a plurality of scan paths, It can be applied to the LSI 1C in a short time. Specifically, if the number of internal scan paths is increased k times, the test time can be reduced to approximately 1 / k. At the same time, the amount of pattern data stored in the tester can be reduced. Specifically, if the number of internal scan paths is increased by k times, the amount of memory can be reduced to approximately 1 / k.
[0089]
In the third embodiment, the pseudo random pattern generator (LFSR or the like) 2 used in the BIST is used. However, since a deterministic pattern is applied to the inside, a special control circuit for the bus circuit, It does not impose strict design constraints on the designer, such as inserting test point circuits to improve the diagnostic rate. In addition, a pattern compressor (MISR or the like) used in BIST can be used. By using the indeterminate mask unit 5, an indefinite state in the circuit propagates to the output verifier (MISR) 7 and cannot be verified. It can also be prevented.
[0090]
Therefore, also in the third embodiment, the test pattern generated by the pseudorandom pattern generator 2 is corrected by the pattern corrector 4 and input to a plurality of scan paths, thereby increasing the number of scan paths and the number of scan path stages (each scan path). The number of F / Fs on the campus can be reduced, and the test time of the LSI 1C can be greatly shortened. In addition, high-quality tests can be performed without imposing strict design rules on the designer and without requiring an expensive tester. Further, the indeterminate value (X value) in the output from the plurality of scan paths formed by the F / F in the LSI 1C is masked by the indeterminate mask unit 5, and the masked output result is verified by the output verifier 7. Even if the output result from the F / F is compressed and read to the outside, the indefinite value does not ruin the compression result.
[0091]
[4] Other
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the embodiment described above, a case is described in which eight scan paths are formed in parallel in each of the LSIs 1A, 1B, and 1C, and each scan path is formed by connecting four F / Fs in series. However, the present invention is not limited to this.
[0092]
[5] Appendix
(Appendix 1) A pattern generator that is incorporated into an integrated circuit to generate a test pattern;
A plurality of shift registers formed in parallel by sequential circuit elements within the integrated circuit, each of which shifts in a test pattern generated by the pattern generator;
An output compressor that compresses a plurality of outputs shifted out from the plurality of shift registers using a check bit of a Hamming code and outputs the compressed output to the outside of the integrated circuit is provided. , Integrated circuit diagnostic equipment.
[0093]
(Supplementary note 2) The integrated circuit according to Supplementary note 1, further comprising diagnostic means for comparing the expected output value obtained in advance with the output from the output compressor to perform fault diagnosis. Diagnostic device.
(Supplementary note 3) When the diagnosis means diagnoses that there is only one failure location as a result of the comparison, the shift means in which the failure exists is specified. Diagnostic device.
[0094]
(Supplementary note 4) The accumulation according to Supplementary note 2 or Supplementary note 3, wherein, when the diagnosis means diagnoses that there are two or three failure locations as a result of the comparison, the presence of the failure is pointed out. Circuit diagnostic device.
(Supplementary note 5) The supplementary note 1 to the supplementary note, further comprising a pattern corrector that corrects the test pattern generated by the pattern generator by external input and then inputs it to the plurality of shift registers. 5. The integrated circuit diagnostic apparatus according to any one of 4 above.
[0095]
(Supplementary Note 6) An indeterminate mask device that masks indeterminate values in the output from the plurality of shift registers;
An output verifier for verifying the output result masked by the indeterminate mask device,
6. The integrated circuit diagnostic apparatus according to any one of appendices 1 to 5, wherein an output of the indefinite mask device is input to the output compressor.
[0096]
(Appendix 7) A pattern generator that is incorporated in an integrated circuit to generate a test pattern;
A plurality of shift registers formed in parallel by sequential circuit elements within the integrated circuit, each of which shifts in a test pattern generated by the pattern generator;
At least one EOR (exclusive OR) tree circuit for compressing and outputting a plurality of outputs shifted out from the plurality of shift registers to the outside of the integrated circuit;
An integrated circuit diagnostic apparatus comprising: a control circuit capable of enabling one of the plurality of outputs input to the EOR tree circuit.
[0097]
(Supplementary note 8) The integrated circuit according to supplementary note 7, further comprising diagnostic means for comparing the expected output value obtained in advance with the output from the EOR tree circuit to perform fault diagnosis. Diagnostic device.
(Supplementary Note 9) The control circuit enables the plurality of outputs one by one,
The EOR tree circuit compresses the output validated by the control circuit and sequentially outputs it to the outside of the integrated circuit;
9. The appendix according to claim 8, wherein the diagnostic means performs the fault diagnosis in the plurality of shift registers one by one based on an output from the EOR tree circuit, and identifies a shift register in which a fault exists. Integrated circuit diagnostic device.
[0098]
(Supplementary Note 10) The control circuit enables the output from the shift register corresponding to the pattern of the pattern number within a predetermined range generated by the pattern generator to narrow down the pattern number where the failure has occurred. The integrated circuit diagnostic device according to any one of appendix 7 to appendix 9, which is characterized in that it is characterized in that:
(Supplementary note 11) Supplementary notes 7 to Supplementary notes, further comprising a pattern correction unit for correcting the test pattern generated by the pattern generator by external input and then inputting it to the plurality of shift registers. The integrated circuit diagnostic apparatus according to any one of 10.
[0099]
(Supplementary Note 12) An indeterminate mask device that masks indeterminate values in the output from the plurality of shift registers;
An output verifier for verifying the output result masked by the indeterminate mask device,
12. The integrated circuit diagnostic device according to any one of appendix 7 to appendix 11, wherein the output verifier functions as the EOR tree circuit.
[0100]
(Supplementary note 13) A test pattern is generated by a pattern generator incorporated in an integrated circuit.
The test pattern generated by the pattern generator is shifted in each of a plurality of shift registers formed in parallel by sequential circuit elements inside the integrated circuit,
A plurality of outputs each shifted out from the plurality of shift registers are compressed using a check bit of a Hamming code and output to the outside of the integrated circuit,
A diagnostic method for an integrated circuit, wherein failure diagnosis is performed by comparing an expected output value obtained in advance with an output from the integrated circuit.
[0101]
(Supplementary note 14) The integrated circuit diagnosis method according to supplementary note 13, wherein, as a result of the comparison, when it is diagnosed that there is only one failure location, the shift register in which the failure exists is specified.
(Supplementary note 15) The integrated circuit diagnosis method according to supplementary note 13 or supplementary note 14, wherein the presence of the failure is pointed out when it is diagnosed that there are two or three failure locations as a result of the comparison.
[0102]
(Supplementary Note 16) A test pattern is generated by a pattern generator incorporated in an integrated circuit.
The test pattern generated by the pattern generator is shifted in each of a plurality of shift registers formed in parallel by sequential circuit elements inside the integrated circuit,
Enabling a plurality of outputs each shifted out from the plurality of shift registers, one by one;
The validated output is compressed by an EOR (exclusive OR) tree circuit and sequentially output to the outside of the integrated circuit,
A method for diagnosing an integrated circuit, wherein failure diagnosis is performed by comparing an output expected value obtained in advance with an output from the EOR tree circuit.
[0103]
(Supplementary note 17) The integrated circuit according to supplementary note 16, characterized in that, based on an output from the EOR tree circuit, the fault diagnosis in the plurality of shift registers is performed one by one to identify a shift register in which a fault exists. Circuit diagnostic method.
(Supplementary note 18) The output from the shift register corresponding to a pattern having a pattern number in a predetermined range generated by the pattern generator is validated to narrow down the pattern number in which a failure has occurred. Or the integrated circuit diagnostic method according to appendix 17.
[0104]
(Supplementary note 19) An integrated circuit including a sequential circuit element,
A pattern generator for generating test patterns;
A plurality of shift registers formed in parallel by the sequential circuit elements, each of which shifts in a test pattern generated by the pattern generator;
An integrated output compressor that incorporates an output compressor that compresses a plurality of outputs shifted out of the plurality of shift registers using a check bit of a Hamming code and outputs the compressed output to the outside of the integrated circuit. circuit.
[0105]
(Supplementary note 20) The integrated circuit according to supplementary note 19, further comprising a pattern corrector that corrects a test pattern generated by the pattern generator by external input and then inputs the test pattern to the plurality of shift registers. .
(Supplementary note 21) An indeterminate mask device for masking indeterminate values in the output from the plurality of shift registers;
An output verifier for verifying the output result masked by the indeterminate mask device;
The integrated circuit according to appendix 19 or appendix 20, wherein the output of the indefinite mask device is input to the output compressor.
[0106]
(Supplementary note 22) An integrated circuit including a sequential circuit element,
A pattern generator for generating test patterns;
A plurality of shift registers formed in parallel by the sequential circuit elements, each of which shifts in a test pattern generated by the pattern generator;
At least one EOR (exclusive OR) tree circuit for compressing and outputting a plurality of outputs shifted out from the plurality of shift registers to the outside of the integrated circuit;
An integrated circuit comprising a control circuit capable of enabling one of the plurality of outputs input to the EOR tree circuit.
[0107]
(Supplementary note 23) The control circuit enables the output from the shift register corresponding to the pattern of the pattern number within a predetermined range generated by the pattern generator to narrow down the pattern number where the failure has occurred. The integrated circuit according to appendix 22, wherein the integrated circuit is characterized.
(Supplementary note 24) The supplementary note 22 or the supplementary note 23 is characterized in that a pattern correction unit that further corrects a test pattern generated by the pattern generator by external input and then inputs the test pattern to the plurality of shift registers is further incorporated. An integrated circuit as described.
[0108]
(Supplementary Note 25) An indeterminate mask device that masks indeterminate values in the output from the plurality of shift registers;
An output verifier for verifying the output result masked by the indeterminate mask device;
25. The integrated circuit according to any one of appendices 22 to 24, wherein the output verifier functions as the EOR tree circuit.
[0109]
【The invention's effect】
  As described above in detail, the integrated circuit diagnosis device and diagnosis method of the present inventionTo the lawAccording to the present invention, a plurality of outputs shifted out from a plurality of shift registers are compressed as signatures and output to the outside of the integrated circuit, and are compressed into hamming code check bits and output to the outside. It is possible to provide a mechanism for observing the scan path information with a small number of external output pins, and to realize LSI diagnosis using a test such as BIST with little circuit overhead. In failure diagnosis, it is necessary to compare expected values for each test pattern with a tester. However, since information on a large number of scan paths is compressed and encoded, diagnosis faster than DSPT is possible. Even when the output from the scan path is compressed and stored or when the number of scan paths is large, it is possible not only to detect a manufacturing failure (failure) of the integrated circuit but also to identify the occurrence position. (Claim 1, 3).
[0110]
  In addition, a plurality of outputs shifted out from a plurality of shift registers are validated one by one, and the validated outputs are compressed by an EOR (exclusive OR) tree circuit and sequentially output to the outside. In the failure diagnosis of an LSI to which a test such as BIST is applied, it is possible to correctly specify all scan paths in which a failure exists. Therefore, even when a large number of failures exist at the same time when a new manufacturing process is started, it is possible to perform a correct and reliable failure diagnosis (claims).2, 4).
[0111]
At this time, by enabling the output from the shift register corresponding to the pattern of the pattern number in the predetermined range generated by the pattern generator and performing fault diagnosis, the pattern number where the fault occurred is narrowed down and It is also possible to specify the fault location.
[0112]
In addition, the test pattern generated by the pattern generator is corrected by the pattern corrector and input to multiple shift registers (scan paths), thereby increasing the number of scan paths and reducing the number of scan path stages, thereby reducing the test time of the integrated circuit. Can be greatly shortened. In addition, the problems of DSPT and BIST are solved, and a test pattern that enables a high-quality test that takes advantage of both of them in a short time can be generated. At that time, only the meaningful data part (F / F information whose value needs to be set) is supplied and corrected from the tester (external input), so the amount of data stored in the tester is greatly reduced. You can also. Therefore, a high quality test can be performed without imposing strict design rules on the designer and without requiring an expensive tester.
[0113]
In addition, by masking indeterminate values in the output from a plurality of shift registers formed by sequential circuit elements inside the integrated circuit and verifying the masked output result by an output verifier, the output result from the sequential circuit element is obtained. Even if compressed and read out, the indefinite state will not ruin the compression result.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the configuration of an integrated circuit diagnostic apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a compression method (an example of error correction using a Hamming code) using check bits of a Hamming code in the first embodiment.
FIG. 3 is a block diagram showing a configuration of an integrated circuit diagnostic apparatus according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing the configuration of an integrated circuit diagnostic apparatus according to a third embodiment of the present invention.
FIG. 5 is a time chart for explaining the operation of the third embodiment.
FIG. 6 is a diagram for explaining a conventional scan design (DSPT).
FIG. 7 is a diagram for explaining a conventional BIST circuit;
FIG. 8 is a block diagram showing a configuration of an integrated circuit test circuit including a pattern corrector and an indeterminate mask device;
[Explanation of symbols]
1A, 1B, 1C LSI (integrated circuit)
2 Pseudo random number pattern generator (pattern generator, LFSR)
4 Pattern corrector
5 Undefined mask device
7 Output verifier (MISR)
10 Output compressor
11-21 Exclusive OR circuit (EOR circuit)
30 Output selector
31, 32 EOR (exclusive OR) tree circuit
33-38 Exclusive OR circuit (EOR circuit)
40 Control circuit
41 Decoder
42 to 49 OR circuit (OR circuit)
51 decoder
52, 53, 54 OR circuit (OR circuit)
55 AND circuit (AND circuit)
56 Multiplexer (control circuit)
57 Flip-flop (initialization setting F / F, control circuit)
58 Start counter (control circuit)
59 End counter (control circuit)
60 NAND circuit (NAND circuit, control circuit)
61 OR circuit (OR circuit, control circuit)
62 Flip-flop (F / F)
F / F flip-flop (sequential circuit element)

Claims (4)

A pattern generator incorporated in an integrated circuit to generate a test pattern;
A plurality of shift registers formed in parallel by sequential circuit elements within the integrated circuit, each of which shifts in a test pattern generated by the pattern generator;
An output verifier that compresses a plurality of outputs shifted out from the plurality of shift registers as a signature and outputs the compressed output to the outside of the integrated circuit;
An output compressor that compresses a plurality of outputs shifted out from the plurality of shift registers into Hamming code check bits and outputs the compressed bits to the outside of the integrated circuit ;
A diagnostic means for performing a fault diagnosis by comparing an output expected value obtained in advance with an output from the output compressor;
The diagnostic means obtains a syndrome by calculating an exclusive OR of the output expected value and the check bit, and corresponds to the syndrome and the syndrome obtained in advance when there is one failure location. An integrated circuit diagnostic apparatus , wherein a shift register in which the fault exists is specified based on an error vector . A pattern generator incorporated in an integrated circuit to generate a test pattern;
A plurality of shift registers formed in parallel by sequential circuit elements within the integrated circuit, each of which shifts in a test pattern generated by the pattern generator;
At least one EOR (exclusive OR) tree circuit for compressing and outputting a plurality of outputs shifted out from the plurality of shift registers to the outside of the integrated circuit;
A control circuit capable of enabling one of the plurality of outputs input to the EOR tree circuit ;
A diagnostic means for performing failure diagnosis by comparing an output expected value obtained in advance with an output from the EOR tree circuit;
The control circuit enables the plurality of outputs one by one;
The EOR tree circuit compresses the output validated by the control circuit and sequentially outputs it to the outside of the integrated circuit;
The diagnostic means diagnoses the integrated circuit by performing the fault diagnosis in the plurality of shift registers one by one based on the output from the EOR tree circuit and identifying the shift register in which the fault exists. apparatus. Generate a test pattern with a pattern generator built into the integrated circuit,
The test pattern generated by the pattern generator is shifted in each of a plurality of shift registers formed in parallel by sequential circuit elements inside the integrated circuit,
A plurality of outputs shifted out from the plurality of shift registers are compressed as signatures and output to the outside of the integrated circuit, and
A plurality of outputs shifted out from the plurality of shift registers are compressed into check bits of a Hamming code and output to the outside of the integrated circuit,
Calculating an exclusive OR of the expected output value obtained in advance and the check bit output from the integrated circuit to obtain a syndrome, performing failure diagnosis based on the syndrome ,
As a result of the failure diagnosis, when there is one failure location, a shift register in which the failure exists is specified based on the syndrome and an error vector corresponding to the syndrome obtained in advance. , Integrated circuit diagnostic method. Generate a test pattern with a pattern generator built into the integrated circuit,
The test pattern generated by the pattern generator is shifted in each of a plurality of shift registers formed in parallel by sequential circuit elements inside the integrated circuit,
Enabling a plurality of outputs each shifted out from the plurality of shift registers, one by one;
The validated output is compressed by an EOR (exclusive OR) tree circuit and sequentially output to the outside of the integrated circuit,
A diagnostic method for an integrated circuit, comprising comparing an expected output value obtained in advance with an output from the EOR tree circuit to perform fault diagnosis one by one to identify a shift register in which a fault exists .

Images