JP2012216188A - Storage control device, storage control method, and storage control program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure normal access control for a storage part even when change occurs in characteristics of the storage part.SOLUTION: The storage control device includes: a memory 20 for storing multiple configuration information which relates to an FPGA 3 for performing access control of a storage part 4 and is appropriate to characteristics of the access control of the storage part 4; and a configuration control part 40 for setting the configuration information on the FPGA 3. When the configuration control part 40 detects a memory NG signal of an H level of the storage part 4 after setting one configuration information stored in the memory 20 on the FPGA 3, the configuration control part 40 switches the configuration information to different configuration information stored in the memory 20, and then sets the switched configuration information on the FPGA 3.

Description

  The present invention relates to a storage control device, a storage control method, and a storage control program.

  For example, an information processing apparatus such as a communication device or a computer has a storage unit that stores various types of information. FIG. 11 is a block diagram illustrating an example of the inside of the information processing apparatus. For example, the information processing apparatus 100A such as a communication device includes a central processing unit (CPU) 101, a field programmable gate array (FPGA) 102, a storage unit 103, and a storage control unit 104. The CPU 101 controls writing and reading of data with respect to the storage unit 103 through the FPGA 102. The FPGA 102 controls access to the storage unit 103 based on configuration information being set which will be described later. The flash memory 111 stores configuration information corresponding to alternating current (AC) characteristics of the storage unit 103. The configuration information is information for controlling timing of various control signals for the storage unit 103 when the FPGA 102 controls access to the storage unit 103, for example.

  The FPGA 102 includes a CPU interface 102A, a memory interface 102B, and a memory controller 102C. The CPU interface 102A is an interface that connects the CPU 101 and the memory controller 102C. The memory interface 102B is an interface that connects the memory controller 102C and the storage unit 103. The memory controller 102C controls access to the storage unit 103 based on the configuration information being set. The storage unit 103 is, for example, a memory device such as EAROM (Electrically Alterable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory, FeRAM (Ferroelectric RAM), or MRAM (Magnetic RAM).

  The storage control unit 104 includes a flash memory 111 and a configuration control unit 112. When the configuration control unit 112 detects the power activation of the information processing apparatus 100 </ b> A, the configuration control unit 112 reads the initial configuration information stored in the flash memory 111. Further, the configuration control unit 112 notifies the FPGA 102 of configuration information and a configuration signal (hereinafter referred to as a configuration signal). The memory controller 102 </ b> C in the FPGA 102 sets configuration information in the FPGA 102 in accordance with a configuration signal from the configuration control unit 112.

  The memory controller 102C controls access to the storage unit 103 with the storage unit 103 using control signals such as an address signal, a chip select signal, a write enable signal, and an output enable signal. The address signal is a signal that designates an address in the storage unit 103. The chip select signal is a signal that designates a chip in the storage unit 103. The write enable signal is a signal for instructing data writing in the storage unit 103. The output enable signal is a signal for instructing data reading in the storage unit 103.

  The configuration information is information for setting, for example, a predetermined setup time and hold time when the memory controller 102C normally controls access to the storage unit 103. The setup time is the minimum time for determining and holding data prior to the timing signal. The hold time is a time for holding data even after the timing signal is detected. That is, the memory controller 102C can perform access control at a normal timing between the control signals with the storage unit 103 by satisfying the setup time and hold time conditions.

JP 2010-122842 A International Publication No. 2004/102389 JP 2006-99597 A JP 2006-65470 A JP 2007-87284 A JP 2004-246699 A Japanese Patent Laid-Open No. 2001-136058

  However, the FPGA 102 determines whether the control signal between the storage unit 103 and the storage unit 103 changes when the AC characteristics of the storage unit 103 change due to environmental changes such as aging or temperature change of the storage unit 103 while setting the initial configuration information. Causes a timing error. Therefore, in the FPGA 102, when a timing error occurs between the control signals with the storage unit 103, the data cannot be determined and held by, for example, the setup time determined by the initial configuration information. As a result, the FPGA 102 cannot ensure normal access control for the storage unit 103 with the initial configuration information due to a change in characteristics of the storage unit 103 or the like.

  Therefore, the storage control unit 104 includes a timing adjustment circuit that adjusts the timing for each control signal such as a chip select signal, an address signal, a write enable signal, and an output enable signal, for example, and eliminates a timing error between the control signals. It is possible. However, each timing adjustment circuit requires a plurality of stages of flip-flop circuits in order to adjust the timing of the control signal with high accuracy. Therefore, the storage control unit 104 requires a timing adjustment circuit including a plurality of flip-flop circuits for each control signal, so that the circuit scale becomes large and the power consumption increases.

  An object of one aspect is to provide a storage control device, a storage control method, and a storage control program that can ensure normal access control for a storage unit even when the characteristics of the storage unit change.

  In one aspect, the disclosed apparatus relates to a control unit that controls access to a storage unit, the configuration storage unit that stores a plurality of configuration information corresponding to the access control characteristics of the storage unit, and the control of the configuration information A setting unit to be set in the unit. Further, the setting unit of the disclosed apparatus sets one configuration information stored in the configuration storage unit in the control unit, and then detects a control error in the storage unit, stores the configuration information in the configuration storage unit. Switch to different configuration information and set the switched configuration information in the control unit.

  Even when a change occurs in the characteristics of the storage unit, normal access control can be ensured for the storage unit.

FIG. 1 is a block diagram illustrating an example of the inside of the information processing apparatus according to the first embodiment. FIG. 2 is a block diagram illustrating an example of the inside of the generation unit. FIG. 3 is an explanatory diagram showing generation timing of the reconfiguration signal inside the generation unit. FIG. 4 is an explanatory diagram illustrating operation timings from the occurrence of a timing error to the elimination of the timing error in the storage unit related to the FPGA and the selection unit. FIG. 5 is a flowchart illustrating an example of processing operations of the FPGA and the configuration control unit related to the configuration control process. FIG. 6 is a block diagram illustrating an example of the inside of the information processing apparatus according to the second embodiment. FIG. 7 is an explanatory diagram showing an example of the bank configuration of the FPGA. FIG. 8 is a flowchart illustrating an example of processing operations of the FPGA and the configuration control unit related to the configuration control process. FIG. 9 is a flowchart illustrating an example of a processing operation of the failure determination unit related to the failure determination processing. FIG. 10 is an explanatory diagram of a computer that executes a storage control program. FIG. 11 is a block diagram illustrating an example of the inside of the information processing apparatus.

  Hereinafter, embodiments of a storage control device, a storage control method, and a storage control program disclosed in the present application will be described in detail with reference to the drawings. The disclosed technology is not limited by the present embodiment.

  FIG. 1 is a block diagram illustrating an example of the inside of the information processing apparatus according to the first embodiment. An information processing apparatus 1 illustrated in FIG. 1 corresponds to, for example, a communication device or a computer, and includes a CPU 2, an FPGA 3, a storage unit 4, and a storage control unit 5. The CPU 2 controls the entire information processing apparatus 1 and controls access to the storage unit 4 via the FPGA 3. The FPGA 3 is disposed between the CPU 2 and the storage unit 4 and controls access to the storage unit 4. The FPGA 3 includes a CPU interface 11, a memory interface 12, and a memory controller 13. The CPU interface 11 is an interface that connects the CPU 2 and the memory controller 13. The memory interface 12 is an interface that connects the memory controller 13 and the storage unit 4. The memory controller 13 controls access to the storage unit 4 on the basis of configuration information being set which will be described later. Further, the memory controller 13 includes a check unit 13A that performs a state of the storage unit 4, for example, ECC (Error Check and Correct) and parity check. When the check unit 13A detects a timing error between the control signals of the storage unit 4 when the AC characteristics of the storage unit 4 change due to environmental changes such as aging or temperature change of the storage unit 4, for example, the check unit 13A outputs a memory NG signal. Output.

  The storage unit 4 is, for example, a memory device such as EAROM (Electrically Alterable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory, FeRAM (Ferroelectric RAM), or MRAM (Magnetic RAM). The storage unit 4 is, for example, a memory device such as PRAM (Pseudo RAM), ReRAM (Resistance RAM), DRAM (Dynamic RAM), or SRAM (Static RAM).

  The storage control unit 5 includes a memory 20, an instruction unit 30, and a configuration control unit 40. The memory 20 is a memory device such as a flash memory, EAROM, or EEPROM. The memory 20 stores a plurality of pieces of configuration information corresponding to different AC characteristics of the storage unit 4. In the memory 20, for example, initial configuration information “A” is stored in a storage area of addresses “0000” to “0FFF”. Further, the memory 20 stores configuration information “B” corresponding to other AC characteristics in the storage area of addresses “1000” to “1FFF”. Further, the memory 20 stores configuration information “C” corresponding to other AC characteristics in the storage area of addresses “2000” to “2FFF”. These three types of configuration information “A” to “C” are merely examples, and two or more types of configuration information may be stored in the memory 20.

  The instruction unit 30 includes a selection unit 31 and a generation unit 32. When the selection unit 31 detects an “H” level memory NG signal from the memory controller 13, the selection unit 31 outputs a selection signal for selecting the configuration information of the switching destination among the configuration information stored in the memory 20. When the generation unit 32 detects the memory NG signal at the “H” level, the generation unit 32 generates a reconfiguration signal based on the timing of the memory NG signal at the “H” level.

  FIG. 2 is a block diagram illustrating an example of the inside of the generation unit 32. FIG. 3 is an explanatory diagram showing the generation timing of the reconfiguration signal inside the generation unit 32. The generation unit 32 includes a flip-flop circuit (hereinafter simply referred to as FF circuit) 32A, a NOT circuit 32B, an AND circuit 32C, and an FF circuit 32D. In FIG. 3, when the rising edge of the memory NG signal at the “H” level is detected, the FF circuit 32A outputs a signal obtained by delaying the memory NG signal by one clock (CLK) to the NOT circuit 32B. The NOT circuit 32B inverts the output signal of the FF circuit 32A and outputs the inverted signal to the AND circuit 32C. The AND circuit 32C outputs a signal based on the logical product of the output signal of the NOT circuit 32B and the “NG” level memory NG signal. The FF circuit 32D outputs a reconfiguration signal by delaying the output signal of the AND circuit 32C by one clock. The reconfiguration signal is used to generate a configuration signal when other configuration information is reset in the FPGA 3.

  When the configuration control unit 40 detects a selection signal for selecting the configuration information of the switching destination from the selection unit 31, the configuration control unit 40 reads the configuration information specified by the selection signal from the memory 20.

  The configuration control unit 40 includes an upper designation unit 41, a lower designation unit 42, and a bit combination unit 43. Upon detecting the selection signal from the selection unit 31, the upper specification unit 41 specifies the upper bits of the address of the storage area in the memory 20 that stores the configuration information. The lower designation unit 42 designates the lower bits of the address of the storage area. For example, when the head address of the storage area for the configuration information “B” is “1000”, the upper bit is “1” and the lower bit is “000”. The bit combining unit 43 combines the upper bit specified by the upper specifying unit 41 and the lower bit specified by the lower specifying unit 42 to generate the address of the configuration information to be read. When the upper bit is “1” and the lower bit is “000”, the bit combination unit 43 combines “1” and “000” into an address signal “1000”. The configuration control unit 40 reads configuration information from the memory 20 based on the address signal output from the bit combination unit 43. Further, when the configuration control unit 40 detects the reconfiguration signal from the generation unit 32, the configuration control unit 40 outputs a configuration signal for setting the read designated configuration information in the FPGA 3 to the FPGA 3. When the FPGA 3 detects the configuration signal, the FPGA 3 sets the configuration information.

  Next, the operation of the information processing apparatus 1 according to the first embodiment will be described. FIG. 4 is an explanatory diagram showing operation timings from the generation of the timing error of the storage unit 4 related to the FPGA 3 and the selection unit 31 to the resolution of the timing error. In FIG. 4, AC characteristics change due to environmental changes such as aging and temperature changes in the storage unit 4. For example, the timing error occurs because the data cannot be determined and held before the setup time of the configuration information “A” of the initial setting. Suppose that occurs. The initial configuration information “A” is set to, for example, 5 n seconds between the setup time Tsu and the hold time Th. At this time, when the check unit 13A of the memory controller 13 detects a timing error of the configuration information “A”, it outputs a memory NG signal of “H” level. When the selection unit 31 in the instruction unit 30 detects the memory NG signal of “H” level from the memory controller 13, the selection unit 31 sends a selection signal for selecting the configuration information “B” of the switching destination from the configuration information “A”. Output to 40. Further, the generation unit 32 in the instruction unit 30 generates a reconfiguration signal based on the timing of the “H” level memory NG signal. Then, the generation unit 32 outputs a reconfiguration signal to the configuration control unit 40.

  When receiving the selection signal, the configuration control unit 40 generates an address signal for the storage area of the configuration information “B” through the upper designation unit 41, the lower designation unit 42, and the bit combination unit 43. Further, the configuration control unit 40 reads the designated configuration information “B” from the storage area of the memory 20 based on the address signal. Further, the configuration control unit 40 outputs the configuration information “B” to the memory controller 13 in the FPGA 3. Further, when detecting the reconfiguration signal from the instruction unit 30, the configuration control unit 40 outputs a configuration signal for setting the configuration information “B” in the FPGA 3 based on the reconfiguration signal. When the FPGA 3 detects the configuration signal, the configuration information “B” is set, so that the interval between the setup time Tsu1 and the hold time Th1 of the configuration information “B” is, for example, 3 n seconds. As a result, the FPGA 3 can determine and hold data at the setup time Tsu1 or before the setup time Tsu1 by changing the setup time from Tsu to Tsu1. Therefore, the FPGA 3 can eliminate the timing error in the storage unit 4 by setting the configuration information “B”. That is, in the example of FIG. 4, it is possible to eliminate the timing error in the storage unit 4 by switching the configuration information “A” to the configuration information “B” and changing the setup time.

  FIG. 5 is a flowchart illustrating an example of processing operations of the FPGA 3 and the configuration control unit 40 related to the configuration control process. In FIG. 5, the configuration control unit 40 sets initial configuration information “A” stored in the memory 20 when the information processing apparatus 1 is powered on in the FPGA 3 (step S11). The FPGA 3 reads, for example, data written in the storage unit 4 during normal operation (step S12). The check unit 13A of the memory controller 13 of the FPGA 3 determines whether or not the check result of the storage unit 4 is in an OK state (step S13). The check unit 13A determines, for example, whether or not the normal conditions for the setup time and the hold time are satisfied. If the normal conditions are satisfied, the check result is set to an OK state, and if the normal conditions are not satisfied, the check result is determined. Is not in the OK state and is in the NG state. If the check result is OK (Yes at Step S13), the check unit 13A proceeds to Step S12 so as to read the data written in the storage unit 4.

  If the check result is not in the OK state (No at Step S13), the check unit 13A outputs an “H” level memory NG signal to the selection unit 31 (Step S14). When detecting the “H” level memory NG signal, the selection unit 31 outputs a selection signal for selecting the configuration information of the switching destination to the configuration control unit 40 (step S15). Furthermore, when detecting the “NG” level memory NG signal, the generation unit 32 outputs a reconfiguration signal to the configuration control unit 40 based on the timing of the memory NG signal (step S16).

  The configuration control unit 40 determines whether or not the configuration information currently set in the FPGA 3 is “C” (step S17). When the configuration information currently set in the FPGA 3 is not “C” (No in step S17), the configuration control unit 40 outputs the configuration signal to the FPGA 3 when detecting the reconfiguration signal. Then, when detecting the configuration signal, the FPGA 3 resets the configuration information of the switching destination to the FPGA 3 (step S18). The memory controller 13 in the FPGA 3 sets the initial configuration information “A” when the information processing apparatus 1 is powered on, and detects the “H” level memory NG signal each time the configuration information “B” → configuration. Switch to information “C”. When the configuration control unit 40 resets the configuration information in the memory controller 13 of the FPGA 3 by the configuration signal, the configuration control unit 40 proceeds to step S12.

  In addition, when the configuration information currently set in the FPGA 3 is “C” (Yes at Step S17), the configuration control unit 40 is in the NG state even if all the configuration information in the memory 20 is set. Judge. As a result, the configuration control unit 40 notifies the failure of the storage unit 4 to the outside (step S19). Note that the user on the information processing apparatus 1 side can recognize the failure of the storage unit 4 by an external notification such as a sound output or a lighting output of a failure alarm. Furthermore, when the configuration control unit 40 notifies the failure of the storage unit 4 to the outside, the configuration control unit 40 stops the operation of the storage unit 4 (step S20) and ends the processing operation illustrated in FIG.

  In the configuration control process shown in FIG. 5, when an “H” level memory NG signal is detected by the characteristic change of the storage unit 4, different configuration information is read from the plurality of configuration information stored in the memory 20 and read. Configuration information is set in FPGA3. As a result, the FPGA 3 can provide the configuration information corresponding to the characteristic change of the storage unit 4 because the read configuration information is set.

  Further, in the configuration control process, each time the information processing apparatus 1 detects the initial configuration information “A” when the power is turned on and then detects the “NG” memory NG signal, the configuration information “B” → the configuration information “C”. Switch settings in the order of "". As a result, configuration information “A” → configuration information “B” → configuration information “C” can be provided in this order. When the power-on of the information processing apparatus 1 is detected again, the setting information is switched to the initial configuration information “A”.

  In the configuration control process, the configuration information “A” → configuration information “B” → configuration information “C” is switched and set, and the timing error in the storage unit 4 cannot be resolved by all the configuration information. The failure of the storage unit 4 is notified to the outside. As a result, the user on the information processing device 1 side can recognize the failure of the storage unit 4 based on the notification.

  Further, in the configuration control process, if the timing error in the storage unit 4 cannot be resolved even if the respective pieces of configuration information are sequentially set, the operation of the storage unit 4 is stopped. As a result, the operation of the storage unit 4 having a timing error can be automatically stopped.

  In the first embodiment, when a plurality of pieces of configuration information are stored and one piece of configuration information is set in the FPGA 3, and a memory NG signal of “H” level is detected due to an AC characteristic change in the storage unit 4, Switch to information and set the switched configuration information in the FPGA 3. As a result, even when a timing error due to the AC characteristic change in the storage unit 4 occurs, the FPGA 3 can switch the configuration information and eliminate the timing error due to the AC characteristic change in the storage unit 4. In addition, the storage control unit 5 does not require a particularly large circuit scale and has a particularly large power consumption just because it has a function of eliminating timing errors due to AC characteristic changes in the storage unit 4. Nor.

  Further, in the first embodiment, after different configuration information is switched and set, if the timing error cannot be resolved even with the configuration information that is switched and set, the operation of the storage unit 4 is stopped. As a result, the operation of the storage unit 4 having a timing error can be automatically stopped.

  In the first embodiment, since the configuration information is information for adjusting the setup time, the setup time is adjusted by switching the configuration information. As a result, since the FPGA 3 can determine and hold data before the setup time of the switched configuration information, the timing error of the storage unit 4 due to the AC characteristic change can be eliminated.

  In the first embodiment, every time the memory NG signal is detected, the configuration information “A”, the configuration information “B”, and the configuration information “C” are switched from the initial setting, and the power is turned on again after the power is stopped. When detected, the initial configuration information “A” is set in the FPGA 3. However, the storage control unit 5 includes a nonvolatile backup storage unit that backs up the configuration information being set immediately before the power is stopped, for example, the configuration information “B”. Further, when detecting the power activation, the storage control unit 5 does not set the initial configuration information “A” in which the timing error has occurred, and sets the configuration information “B” stored in the backup storage unit in the FPGA 3. You may do it.

  In the first embodiment, the configuration information corresponding to the AC characteristic change of the storage unit 4 is, for example, information for adjusting the setup time, but may be information for adjusting the hold time, for example.

  Moreover, it is good also as information which adjusts the output timing of the control signal which outputs the data memorize | stored in the memory | storage part 4 as structure information externally. The FPGA 3 adjusts the timing for reading data from the storage unit 4 by adjusting the output timing of the control signal by switching and setting different configuration information. As a result, the FPGA 3 can eliminate the timing error due to the AC characteristic change of the storage unit 4. For example, the timing error due to the AC characteristic change of the storage unit 4 can be eliminated by switching and setting the configuration information that advances the output timing of the chip select signal that is the control signal output from the FPGA 3 to the storage unit 4.

  Further, the configuration information may be information for adjusting the phase of the clock (CLK) used by the FPGA 3 for adjusting the timing of access control of the storage unit 4. In this case, the FPGA 3 adjusts the access control timing of the storage unit 4 by adjusting the phase of the clock (CLK) by switching and setting different configuration information. As a result, the FPGA 3 can eliminate the timing error due to the AC characteristic change of the storage unit 4.

  In the first embodiment, when the timing error due to the AC characteristic change of the storage unit 4 occurs, the FPGA 3 switches the different configuration information to eliminate the timing error due to the AC characteristic change of the storage unit 4. However, when the memory interface 12 in the FPGA 3 itself fails, access control to the storage unit 4 cannot be performed. Accordingly, an information processing apparatus 1 that can normally control access to the storage unit 4 even when the memory interface 12 itself fails will be described below as a second embodiment.

  FIG. 6 is a block diagram illustrating an example of the inside of the information processing apparatus according to the second embodiment. The same components as those of the information processing apparatus 1 according to the first embodiment are denoted by the same reference numerals, and the description of the overlapping configuration and operation is omitted. An information processing apparatus 1A illustrated in FIG. 6 includes a CPU 2, an FPGA 3A, a storage unit 4, and a storage control unit 5A. The CPU 2 controls the entire information processing apparatus 1A and controls access to the storage unit 4 via the FPGA 3A. The FPGA 3A is disposed between the CPU 2 and the storage unit 4 and controls access to the storage unit 4. The FPGA 3A includes a CPU interface 11, a memory interface 12A, and a memory controller 13B.

  The memory interface 12A is an interface that connects the memory controller 13B and the storage unit 4. The memory interface 12 </ b> A includes an operation mode setting unit 61, a low speed mode setting unit 62, and a SEL (Selector) 63. The operation mode setting unit 61 sets the operation mode at the normal speed, which is faster than the later-described low-speed mode, as the communication speed with the storage unit 4. The low speed mode setting unit 62 sets the low speed mode in which the communication speed is slower than the normal speed in the operation mode. The SEL 63 sets the communication speed to the operation mode or the low-speed mode by switching the operation mode setting unit 61 or the low-speed mode setting unit 62 according to the mode control signal of the switching control of the memory controller 13B. Note that when the low speed mode is set, the communication speed of the memory interface 12A is generally reduced, so that a margin is generated in the setup time and hold time of the AC timing, and the timing error can be eliminated.

  The memory controller 13B controls access to the storage unit 4 based on the configuration information being set. Furthermore, the memory controller 13B includes a failure determination unit 13C that determines a failure of the memory interface 12A in addition to the check unit 13A. The failure determination unit 13C switches from the operation mode to the low speed mode by switching control of the SEL 63 according to a predetermined timing. The predetermined timing is, for example, a case where the check result of the check unit 13A is not in an OK state, that is, when an NG state is detected.

  For example, when the check unit 13A detects an NG state, the failure determination unit 13C executes a failure determination process for switching from the operation mode to the low speed mode to determine a failure of the memory interface 12A. The failure determination unit 13C determines that the memory interface 12A is normal when the low speed mode is set and the check result is OK. On the other hand, the failure determination unit 13C determines that the memory interface 12A has failed when the check result remains in the NG state despite being set to the low speed mode. Then, the failure determination unit 13C outputs an interface NG signal to the instruction unit 30 when it is determined that the memory interface 12A has failed.

  FIG. 7 is an explanatory diagram showing an example of the bank configuration of the FPGA 3A. The FPGA 3A shown in FIG. 7 has, for example, banks having a total of 16 I / Os from Bank a to Bank p. Each bank is based on the set configuration information, for example, the memory interface 12A or the memory controller. Functions (configures) as each circuit such as 13B. Then, the FPGA 3A reserves an empty bank. For example, Bank a in the FPGA 3A functions as the memory interface 12A, for example, and Bank b in the FPGA 3A is an unused free area.

  The storage control unit 5A includes a memory 20A, an instruction unit 30A, and a configuration control unit 40A. For example, the memory 20A stores configuration information of the memory interface 12A in the FPGA 3A. In the memory 20A, the configuration information “A” of Bank a in the FPGA 3A is stored in the storage area of addresses “0000” to “0FFF”. Furthermore, the configuration information “B” of Bank a in the FPGA 3A is stored in the storage area of the addresses “1000” to “1FFF” in the memory 20A. Further, the configuration information “C” of Bank a in the FPGA 3A is stored in the storage area of the addresses “2000” to “2FFF” in the memory 20A.

  Further, the configuration information “A” of Bank b in the FPGA 3A is stored in the storage area of the addresses “3000” to “3FFF” in the memory 20A. Further, the configuration information “B” of Bank b in the FPGA 3A is stored in the storage area of addresses “4000” to “4FFF” in the memory 20A. Further, the configuration information “C” of Bank b in the FPGA 3A is stored in the storage area of the addresses “5000” to “5FFF” in the memory 20A.

  In addition to the generation unit 32, the instruction unit 30A includes a selection unit 31A. When the selection unit 31A detects an “H” level memory NG signal from the memory controller 13B, the selection unit 31A outputs a first selection signal for selecting a bank to be switched to among the banks stored in the memory 20A. Further, when the selection unit 31A detects the memory NG signal at the “H” level, the selection unit 31A selects the configuration information of the switching destination from the configuration information “A” to “C” of the switching destination Bank stored in the memory 20A. 2 selection signals are output. Upon detecting the “H” level memory NG signal and the “H” level interface NG signal, the generation unit 32 reconfigures the signal based on the timings of the “H” level memory NG signal and the “H” level interface NG signal. Is generated. The reconfiguration signal is used to generate a configuration signal when other configuration information is reset in the FPGA 3A.

  When the configuration control unit 40A detects a selection signal for selecting the switching destination bank and the switching destination configuration information from the selection unit 31A, the configuration control unit 40A reads the configuration information of the designated bank from the memory 20A. The selection signal includes a first selection signal for selecting a switching destination bank and a second selection signal for selecting switching destination configuration information.

  The configuration control unit 40A includes a Bank specifying unit 41A, an upper specifying unit 41B, a lower specifying unit 42A, and a bit combining unit 43A. When the first selection signal is detected from the selection unit 31A, the Bank designation unit 41A designates the bank to be switched to. The bank designating unit 41A designates Bank a when the first selection signal “0” is detected, and designates Bank b when the first selection signal “1” is detected.

  Further, when the second selection signal is detected from the selection unit 31A, the higher-level specification unit 41B specifies the configuration information of the switching destination. For example, when the second selection signal “0” is detected, the higher-level specifying unit 41B specifies the configuration information “A”. For example, when the second selection signal “1” is detected, the higher-level designation unit 41B designates the configuration information “B”. For example, when the second selection signal “2” is selected, the higher-order specifying unit 41B specifies the configuration information “C”.

  The lower specification unit 42A specifies the lower bits of the address of the storage area in the memory 20A. The bit combination unit 43A combines the upper bit and the lower bit to specify the address of the configuration information to be read. For example, when the bank specifying unit 41A is “0” and the upper specifying unit 41B is “0”, the bit combining unit 43A specifies the upper address “0” of the configuration information “A” of Bank a and the lower specifying unit Designate the lower address “000” of 42A. The configuration control unit 40A combines the upper address “0” and the lower address “000”, specifies the address “0000”, and reads the configuration information “A” of Bank a from the memory 20A.

  In addition, when the bank specifying unit 41A is “0” and the upper specifying unit 41B is “1”, the bit combining unit 43A specifies the upper address “1” of the configuration information “B” of Bank a and the lower specifying unit Designate the lower address “000” of 42A. The configuration control unit 40A combines the upper address “1” and the lower address “000”, specifies the address “1000”, and reads the configuration information “B” of Bank a from the memory 20A.

  In addition, when the bank specifying unit 41A is “0” and the upper specifying unit 41B is “2”, the bit combining unit 43A specifies the upper address “2” of the configuration information “C” of Bank a and the lower specifying unit Designate the lower address “000” of 42A. The configuration control unit 40A combines the upper address “2” and the lower address “000”, specifies the address “2000”, and reads the configuration information “C” of Bank a from the memory 20A.

  For example, when the bank specifying unit 41A is “1” and the upper specifying unit 41B is “0”, the bit combining unit 43A specifies the upper address “3” of the configuration information “A” of Bank b and the lower The lower address “000” of the designating part 42A is designated. The configuration control unit 40A combines the upper address “3” and the lower address “000”, specifies the address “3000”, and reads the configuration information “A” of Bank b from the memory 20A.

  For example, when the bank specifying unit 41A is “1” and the upper specifying unit 41B is “1”, the bit combining unit 43A specifies the upper address “4” of the configuration information “B” of Bank b, and the lower The lower address “000” of the designating part 42A is designated. The configuration control unit 40A combines the upper address “4” and the lower address “000”, specifies the address “4000”, and reads the configuration information “B” of Bank b from the memory 20A.

  For example, when the bank specifying unit 41A is “1” and the upper specifying unit 41B is “2”, the bit combining unit 43A specifies the upper address “5” of the configuration information “C” of Bank b and the lower The lower address “000” of the designating part 42A is designated. The configuration control unit 40A combines the upper address “5” and the lower address “000”, specifies the address “5000”, and reads the configuration information “C” of Bank b from the memory 20A.

  The configuration control unit 40A reads configuration information from the memory 20A based on the address signal from the bit combination unit 43A. Furthermore, when the configuration control unit 40A detects the reconfiguration signal from the generation unit 32, the configuration control unit 40A outputs a configuration signal for setting the read designated configuration information in the FPGA 3A to the FPGA 3A. When the FPGA 3A detects the configuration signal, the FPGA 3A sets the configuration information.

  That is, when the configuration information of Bank b is read from the memory 20A, the configuration control unit 40A sets the configuration information in the storage area of Bank b. As a result, the FPGA 3A causes the new memory interface 12A of Bank b to function instead of the memory interface 12A of Bank a in the FPGA 3A.

  Next, the operation of the information processing apparatus 1A according to the second embodiment will be described. FIG. 8 is a flowchart illustrating an example of processing operations of the FPGA 3A and the configuration control unit 40A related to the configuration control process. In FIG. 8, the configuration control unit 40A sets the configuration information “A” of the initially set Bank a stored in the memory 20A when the information processing apparatus 1A is powered on, to Bank a in the FPGA 3A (step S31). The FPGA 3A reads, for example, data written in the storage unit 4 during normal operation (step S32).

  The check unit 13A of the memory controller 13B of the FPGA 3A determines whether or not the check result of the storage unit 4 is in an OK state (step S33). The check unit 13A determines, for example, whether or not the normal conditions for the setup time and the hold time are satisfied. If the normal conditions are satisfied, the check result is set to an OK state, and if the normal conditions are not satisfied, the check result is determined. Is not in the OK state and is in the NG state. If the check result is OK (Yes at Step S33), the check unit 13A proceeds to Step S32 in order to read the data written in the storage unit 4.

  Also, the failure determination unit 13C of the memory controller 13B determines whether or not the memory interface 12A is defective based on the determination result of failure determination processing in FIG. Determination is made (step S34). If the memory interface 12A is not in failure (No at Step S34), the failure determination unit 13C outputs an “H” level memory NG signal to the selection unit 31A (Step S35).

  When the selection unit 31A detects the memory NG signal at the “H” level, the selection unit 31A outputs a selection signal for selecting the configuration information of the switching destination to the configuration control unit 40A among the configuration information of Bank a (step S36). The selection signal includes a first selection signal “0” and a second selection signal. Further, when detecting the “NG” level memory NG signal, the generation unit 32 outputs a reconfiguration signal to the configuration control unit 40A based on the timing of the memory NG signal (step S37).

  The configuration control unit 40A determines whether or not the configuration information of Bank a currently set in the FPGA 3A is “C” (step S38). When the configuration information of Bank a currently set in the FPGA 3A is not “C” (No at Step S38), the configuration control unit 40A outputs a configuration signal to the FPGA 3A when detecting a reconfiguration signal. When the FPGA 3A detects the configuration signal, the FPGA 3A resets the configuration information of the bank a switching destination to the FPGA 3A (step S39). Note that the memory controller 13A in the FPGA 3A sets the initial configuration information “A” of the bank a when the information processing apparatus 1A is powered on, and detects the memory NG signal at the “H” level each time the memory controller 13A detects the memory NG signal in the bank a. The configuration information is changed from “B” to configuration information “C”. Then, when the configuration information of Bank a is reset by the configuration signal, the memory controller 13B of the FPGA 3A proceeds to step S32.

  In addition, when the configuration information of Bank a currently set in the FPGA 3A is “C” (Yes in Step S38), the configuration control unit 40A determines that the check result is NG even if all the configuration information in the memory 20A is set. Judged as a state. As a result, the configuration control unit 40A notifies the failure of the storage unit 4 to the outside (step S40). Note that the user on the information processing apparatus 1A side can recognize a failure of the storage unit 4 by an external notification such as a sound output or a lighting output of a failure alarm. Furthermore, when the configuration control unit 40A notifies the failure of the storage unit 4 to the outside, the configuration control unit 40A stops the operation of the storage unit 4 (step S41) and ends the processing operation illustrated in FIG.

  If the memory interface 12A has a failure (Yes at step S34), the failure determination unit 13C outputs an “H” level interface NG signal to the selection unit 31A (step S42). The configuration control unit 40A reads the configuration information “A” of Bank b from the memory 20A in accordance with an instruction from the selection unit 31A (step S43). The configuration control unit 40A sets the read configuration information “A” of Bank b to Bank b in the FPGA 3A (step S44).

  For example, the FPGA 3A reads the data written in the storage unit 4 (step S45). The check unit 13A determines whether or not the check result in the storage unit 4 is in an OK state (step S46). If the check result is OK (Yes at Step S46), the check unit 13A proceeds to Step S45 in order to read the data written in the storage unit 4.

  Further, when the check result is not in the OK state (No at Step S46), the check unit 13A outputs an “H” level memory NG signal to the selection unit 31A (Step S47). When the selection unit 31A detects the memory NG signal at the “H” level, the selection unit 31A outputs a selection signal for selecting the configuration information of the switching destination to the configuration control unit 40A (step S48). The selection signal includes a first selection signal “1” and a second selection signal. Further, when detecting the “NG” level memory NG signal, the generation unit 32 outputs a reconfiguration signal to the configuration control unit 40A based on the timing of the memory NG signal (step S49).

  The configuration control unit 40A determines whether or not the configuration information of Bank b currently being set in the FPGA 3A is “C” (step S50). When the configuration information of Bank b currently being set in the FPGA 3A is not “C” (No in Step S50), the configuration control unit 40A outputs a configuration signal to the FPGA 3A when detecting a reconfiguration signal. When detecting the configuration signal, the FPGA 3A resets the configuration information of the switching destination of Bank b to the FPGA 3A (step S51). When the memory controller 13A sets the configuration information “A” of Bank b set at the time of determining the failure of the memory interface 12A, the memory controller 13A detects the “NG” memory NG signal every time the memory controller 13A detects the configuration information “B” in Bank b. “→ Switch to configuration information“ C ”. Then, when the configuration information of Bank b is reset by the configuration signal, the memory controller 13B of the FPGA 3A proceeds to Step S45.

  In addition, when the configuration information of Bank b currently being set in the FPGA 3A is “C” (Yes at Step S50), the configuration control unit 40A determines that the check result is NG even if all the configuration information in the memory 20A is set. Judged as a state. As a result, the configuration control unit 40A proceeds to step S40 so as to notify the outside of the failure of the FPGA 3A.

  In the configuration control process shown in FIG. 8, when it is determined that the memory interface 12A is out of order, the configuration information of Bank b stored in the memory 20A is read, and the read configuration information is set to Bank b in the FPGA 3A. . The FPGA 3A sets a new memory interface 12A in Bank b. As a result, the FPGA 3A can substitute Bank a's faulty memory interface 12A in the FPGA 3A for Bank b's new memory interface 12A in the FPGA 3A.

  In the configuration control process, after determining the failure of the memory interface 12A, after setting the configuration information “A” of Bank b, each time the “NG” memory NG signal is detected, the configuration information “B” → the configuration information “C”. Switch settings in the order of "". As a result, the configuration information of Bank b can be provided in the order of configuration information “A” → configuration information “B” → configuration information “C”.

  In the configuration control process, if the error cannot be resolved even if the configuration information “A” → configuration information “B” → configuration information “C” of Bank b is switched and set, the failure of the FPGA 3A Is notified externally. As a result, the user on the information processing apparatus 1A side can recognize the failure of the FPGA 3A based on the external notification.

  Further, in the configuration control process, if the failure of the memory interface 12A cannot be resolved even if the configuration information of Bank b is sequentially set, the operation of the storage unit 4 is stopped. As a result, the operation of the storage unit 4 connected to the failed memory interface 12A can be automatically stopped.

  FIG. 9 is a flowchart illustrating an example of processing operation of the failure determination unit 13C related to failure determination processing. The failure determination process shown in FIG. 9 is a process for determining a failure of the memory interface 12A in the FPGA 3A.

  In FIG. 9, the failure determination unit 13C determines whether or not it is a predetermined timing (step S61). The predetermined timing is, for example, a timing at which the check result of the check unit 13A is determined not to be in an OK state, that is, as an NG state. The failure determination unit 13C sets the memory interface 12A to the low speed mode at the predetermined timing (Yes at Step S61) (Step S62). The failure determination unit 13C selects and switches the operation mode setting unit 61 to the low speed mode setting unit 62 for the SEL 63 in the memory interface 12A, and sets the memory interface 12A to the low speed mode.

  After setting the low-speed mode, the failure determination unit 13C determines whether the check result is in an OK state through the check unit 13A (step S63). If the check result is OK (Yes at Step S63), the failure determination unit 13C determines that the currently used memory interface 12A is normal (Step S64). When it is determined that the memory interface 12A is normal, the failure determination unit 13C sets the memory interface 12A to the operation mode (step S65) and ends the processing operation illustrated in FIG.

  If the check result is not OK (No at Step S63), the failure determination unit 13C determines that the currently used memory interface 12A itself is failed (Step S66), and sets the memory interface 12A to the operation mode. Control goes to step S65.

  In the failure determination process illustrated in FIG. 9, when the check result is NG even though the communication speed with the storage unit 4 is low, the memory interface 12A in the FPGA 3A itself is determined to be defective. As a result, the failure determination unit 13C of the FPGA 3A can recognize the failure of the memory interface 12A in the Bank.

  In the failure determination process, if the check result is OK by reducing the communication speed with the storage unit 4, it is determined that the memory interface 12A in the FPGA 3A is normal. As a result, the failure determination unit 13C of the FPGA 3A can recognize the normality of the memory interface 12A in the Bank.

  In the information processing apparatus 1A according to the second embodiment, when the bank a memory interface 12A itself in the FPGA 3A fails, a new memory interface 12A is configured by setting the configuration information of Bank b in the bank b in the FPGA 3A. As a result, the FPGA 3A can replace the failed memory interface 12A of Bank a with the memory interface 12A of Bank b, so that the timing error due to the failure of the FPGA 3A can be eliminated.

  In the information processing apparatus 1A according to the second embodiment, a plurality of pieces of configuration information are stored for each bank. Then, the information processing apparatus 1A sets the configuration information of another bank in the FPGA 3A, and then detects an “H” level memory NG signal based on the AC characteristic change in the storage unit 4, and then sets the other information in the same bank. Switch to the configuration information and set the switched configuration information in the FPGA 3A. As a result, even when a timing error due to the AC characteristic change of the storage unit 4 occurs, the FPGA 3A can switch the configuration information in the same Bank and eliminate the timing error due to the AC characteristic change of the storage unit 4.

  In the failure determination process of the second embodiment, for example, the timing at which the check result by the check unit 13A is determined to be NG is illustrated as the predetermined timing in step S61. However, the timing is not limited to this timing. For example, the timing may be a time period when the FPGA 3A has less access to the storage unit 4.

  Moreover, in the said Example, although the structure information memorize | stored in the memory 20 (20A) was made into three types of structure information, it is not limited to the number. Further, the configuration information may be stored in a memory device such as FeRAM, MRAM, PRAM, ReRAM, DRAM, or SRAM.

  In addition, each component of each part illustrated does not necessarily need to be physically configured as illustrated. In other words, the specific form of distribution / integration of each part is not limited to the one shown in the figure, and all or a part thereof may be functionally or physically distributed / integrated in arbitrary units according to various loads and usage conditions. Can be configured.

  Furthermore, various processing functions performed in each device are performed on a CPU (Central Processing Unit) (or a microcomputer such as an MPU (Micro Processing Unit), MCU (Micro Controller Unit), etc.) in whole or in part. You may make it perform. Various processing functions may be executed entirely or arbitrarily on a program that is analyzed and executed by a CPU (or a microcomputer such as an MPU or MCU) or hardware based on wired logic. Needless to say.

  By the way, various processes described in the present embodiment can be realized by executing a program prepared in advance by a computer. In the following, an example of a computer that executes a program having the same function as that of the above embodiment will be described with reference to FIG. FIG. 10 is an explanatory diagram of a computer that executes a storage control program.

  As shown in FIG. 10, in a computer 100 as a storage control program, an HDD (Hard Disk Drive) 110, a RAM (Random Access Memory) 120, a ROM (Read Only Memory) 130, and a CPU 140 are connected via a bus 150. . Further, the computer 100 is connected to the FPGA 160 that controls access to the storage unit 170 via the bus 150.

  The ROM 130 or the HDD 110 stores in advance a storage control program that exhibits the same function as in the above-described embodiment. The storage control program may be recorded on a computer-readable recording medium with a drive (not shown) instead of the ROM 130 and the HDD 110. The recording medium may be, for example, a portable recording medium such as a CD-ROM, a DVD disk, or a USB memory, or a semiconductor memory such as a flash memory. The storage control program is a setting program 131 as shown in FIG. Note that the setting program 131 may be integrated or distributed as appropriate, similarly to each component of the storage controller 5 shown in FIG.

  Then, the CPU 140 reads the setting program 131 from the ROM 130 and executes it. The setting program 131 functions as a setting process 141.

  The CPU 140 sets configuration information in the FPGA 160 from the RAM 120 that stores a plurality of configuration information corresponding to the access control characteristics of the storage unit 170 related to the FPGA 160 that controls access to the storage unit 170. Furthermore, after setting one piece of configuration information stored in the RAM 120 in the FPGA 160 and detecting a timing error in the storage unit 170, the CPU 140 switches to different configuration information stored in the RAM 120, and the changed configuration information is transferred to the FPGA 160. Set to. As a result, the FPGA 160 can switch the configuration information and eliminate the timing error due to the characteristic change of the storage unit 170 even when the timing error due to the characteristic change of the storage unit 170 occurs.

  As described above, the following supplementary notes are further disclosed regarding the embodiment including the present example.

(Supplementary Note 1) A control unit that includes a plurality of banks and configures a circuit in the bank based on the set configuration information;
A configuration storage unit that stores the configuration information corresponding to the bank;
A setting unit that reads the configuration information from the configuration storage unit and sets the configuration information in a bank related to the read configuration information;
The circuit is determined to be faulty when an error in timing adjustment between the storage unit and the circuit connected to the storage unit configured in the bank based on the configuration information set by the setting unit is detected. And a failure determination unit.

(Appendix 2) The setting unit
When the failure determination unit determines that the circuit is faulty, the configuration information configuring the circuit connected to the storage unit is set in another bank in the control unit,
The controller is
The storage control device according to appendix 1, wherein the circuit is configured in the bank based on the configuration information set by the setting unit.

(Supplementary Note 3) The setting unit
When the failure determination unit determines that the circuit is faulty, the unused bank in the control unit is set to the configuration information that configures the circuit connected to the storage unit,
The controller is
The storage control device according to appendix 1, wherein the circuit is configured in the unused bank based on the configuration information set by the setting unit.

(Appendix 4) The failure determination unit
Determining whether or not the timing adjustment error is detected by reducing the communication speed between the circuit and the storage unit from the operation speed, and if the timing adjustment error is detected, Judgment and
The storage control device according to any one of appendices 1 to 3, wherein the circuit is determined to be normal when the communication speed is reduced and the timing adjustment error is not detected.

(Supplementary Note 5) A plurality of banks, based on set configuration information, a control unit that configures a circuit in the bank, a configuration storage unit that stores the configuration information corresponding to the bank, and the configuration storage unit A storage control method for a storage control device, comprising: a setting unit that reads the configuration information from the bank and sets the configuration information in a bank related to the read configuration information,
The storage controller is
The circuit is determined to be faulty when an error in timing adjustment between the storage unit and the circuit connected to the storage unit configured in the bank based on the configuration information set by the setting unit is detected. A storage control method characterized by:

1,1A information processing device 3,3A FPGA
4 storage unit 5, 5A storage control unit 13, 13B memory controller 13A check unit 13C failure determination unit 20, 20A memory 30, 30A instruction unit 31, 31A selection unit 32 generation unit 40, 40A configuration control unit

Claims (8)

A configuration storage unit that stores a plurality of configuration information corresponding to the characteristics of the access control of the storage unit, related to a control unit that performs access control of the storage unit;
A setting unit that sets the configuration information in the control unit;
The setting unit
After one configuration information stored in the configuration storage unit is set in the control unit, when a control error of the storage unit is detected, the configuration is switched to different configuration information stored in the configuration storage unit. A storage control device characterized in that information is set in the control unit.   After the setting unit switches and sets different configuration information stored in the configuration storage unit, the operation of the storage unit is stopped when the control error of the storage unit is detected for each switched configuration information. The storage control device according to claim 1, further comprising a stop unit. A backup storage unit that stores the configuration information that is being set immediately before the storage unit is powered off;
The setting unit
3. The storage control device according to claim 1, wherein when the activation of the power source is detected, the configuration information stored in the backup storage unit is set in the control unit. The configuration information is
The control unit is information for adjusting the setup time of the storage unit,
The setting unit
3. The storage control device according to claim 1, wherein the setup time of the control unit is adjusted to adjust the data write timing to the storage unit by switching and setting different configuration information. The configuration information is
Information for adjusting the output timing of a control signal for externally outputting the data stored in the storage unit by the control unit,
The setting unit
3. The storage control device according to claim 1, wherein the control unit adjusts the output timing to adjust the data output timing from the storage unit by switching and setting different configuration information. The configuration information is
Information for adjusting a clock phase used by the control unit for timing adjustment of access control of the storage unit,
The setting unit
The storage control device according to claim 1, wherein the control unit adjusts the clock phase and adjusts the access control timing of the storage unit by switching and setting different configuration information. A storage control method of a storage control device for setting configuration information in a control unit that controls access to a storage unit,
The storage controller is
The configuration information is set in the control unit from a configuration storage unit that stores a plurality of configuration information corresponding to the access control characteristics of the storage unit, and is stored in the configuration storage unit. After configuration information is set in the control unit, when a control error in the storage unit is detected, the configuration information is switched to different configuration information stored in the configuration storage unit, and the switched configuration information is set in the control unit. A storage control method. On the computer,
The configuration information is set in the control unit from a configuration storage unit that stores a plurality of configuration information corresponding to the access control characteristics of the storage unit related to the control unit that performs access control of the storage unit, and the configuration storage unit After setting one configuration information stored in the control unit, upon detecting a control error in the storage unit, the configuration information is switched to different configuration information stored in the configuration storage unit, and the switched configuration information is transferred to the control unit. A storage control program characterized by causing each process to be set to be executed.

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