CN111599389A - Data access method, data access circuit, chip and electronic equipment - Google Patents
Data access method, data access circuit, chip and electronic equipment Download PDFInfo
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- CN111599389A CN111599389A CN202010402933.9A CN202010402933A CN111599389A CN 111599389 A CN111599389 A CN 111599389A CN 202010402933 A CN202010402933 A CN 202010402933A CN 111599389 A CN111599389 A CN 111599389A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a data access method, a data access circuit, a chip and electronic equipment, and relates to the field of FIFO data storage. The data access method is applied to a data access circuit, the data access circuit comprises a byte counter, a data write-in storage unit and a data read-out storage unit, and the byte counter is used for acquiring the number of current bytes; the method comprises the following steps: when the number of the current bytes is smaller than the first storage bit width, the data writing storage unit shifts the current data written in the data writing storage unit to the data reading storage unit; and when the number of the current bytes is greater than or equal to the first storage bit width, the data reading storage unit outputs data according to the first storage bit width. And the total number of bytes of all data in the data writing storage unit and the data reading storage unit is determined by using the byte counter, and the data reading storage unit is used for outputting according to the first storage bit width, so that the design area of the FIFO is saved, and the design risk of the FIFO is reduced.
Description
Technical Field
The invention relates to the field of data storage of a First-in First-out (FIFO) queue, in particular to a data access method, a data access circuit, a chip and electronic equipment.
Background
At present, in order to write and read data, at least two groups of input bit wide memory cells are used, each memory cell having an output bit for outputting data.
When the data is written into the storage unit, the writing position of each data in the storage unit needs to be recorded, so that the data can be output according to the writing position of the data in the storage unit when the storage unit outputs the data; in order to determine the position to be written of the next write data in the storage unit, it is further required to record the current storage position of the remaining data in the storage unit, and determine whether the data to be written can be written into the storage unit. Therefore, in the prior art, data storage of the FIFO needs a write circuit for complex branch judgment and a read circuit for complex branch judgment, and there are multiple links that are prone to error in the design process, such as calculating bit width conversion rules, enumerating read/write judgment cases, and designing the number of storage circuit groups.
Disclosure of Invention
The present invention provides a data access method, a data access circuit, a chip and an electronic device.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
in a first aspect, the present invention provides a data access method applied to a data access circuit, where the data access circuit includes a byte counter, a data write storage unit, and a data read storage unit, where the byte counter is used to obtain a current byte number, and the current byte number is a total number of bytes of all data in the data write storage unit and the data read storage unit. The method comprises the following steps: when the number of the current bytes is smaller than a first storage bit width, the data writing storage unit shifts the current data in the data writing storage unit to the data reading storage unit; the first storage bit width is a fixed bit width of output data of the data reading storage unit; and when the number of the current bytes is greater than or equal to a first storage bit width, the data reading storage unit outputs data according to the first storage bit width.
In an alternative embodiment, the data access circuit further comprises a data read circuit. When the number of the current bytes is greater than or equal to a first storage bit width, the data reading storage unit outputs data according to the first storage bit width, including: the data reading circuit judges whether the current byte quantity is greater than or equal to the first storage bit width; and if so, the data reading storage unit outputs data according to the first storage bit width.
In an optional embodiment, the method further comprises: the data writing storage unit receives data to be written; the number of the first bytes of the data to be written is less than or equal to a second storage bit width, and the maximum number of bytes stored by the data writing storage unit is the second storage bit width.
In an alternative embodiment, the data access circuit further comprises a data shifter. When the number of the current bytes is smaller than a first storage bit width, the data writing storage unit shifts the current data in the data writing storage unit to the data reading storage unit, and the method includes: when the number of the current bytes is smaller than a first storage bit width, the data shifter shifts the current data to the data reading storage unit; the data shifter shifts the first second byte number of bytes in the data to be written to the data reading storage unit, and splices the first second byte number of bytes behind the current data; wherein the second byte number is less than or equal to the first byte number, and a sum of the current byte number and the second byte number is the first storage bit width.
In an optional embodiment, after outputting data according to the first storage bit width, the method further includes: and the byte counter subtracts the first storage bit width from the current byte number to obtain the updated current byte number.
In an optional embodiment, after the data writing storage unit receives data to be written, the method further includes: and the byte counter adds the current byte number to the first byte number to obtain the updated current byte number.
In a second aspect, the present invention provides a data access circuit comprising a byte counter, a data write memory cell, and a data read memory cell. The byte counter is used for acquiring the number of the current bytes; the current byte number is the total number of bytes of all data in the data writing storage unit and the data reading storage unit. The data writing storage unit is used for shifting the current data in the data writing storage unit to the data reading storage unit when the current byte number is smaller than a first storage bit width; the first storage bit width is a fixed bit width of the output data of the data reading storage unit. And the data reading storage unit is used for outputting data according to the first storage bit width when the current byte number is greater than or equal to the first storage bit width.
In an alternative embodiment, the data access circuit further comprises a data read circuit. The data reading circuit is used for judging whether the current byte number is greater than or equal to the first storage bit width; and the data reading storage unit is further used for outputting data according to a first storage bit width when the number of the current bytes in the data reading storage unit is greater than or equal to the first storage bit width.
In an optional embodiment, the data write storage unit is further configured to receive data to be written; the number of the first bytes of the data to be written is less than or equal to a second storage bit width, and the maximum number of bytes stored by the data writing storage unit is the second storage bit width.
In an alternative embodiment, the data access circuit further comprises a data shifter. The data shifter is used for shifting the current data to the data reading storage unit when the current byte number is smaller than a first storage bit width; the data shifter is further configured to shift a first second byte number of bytes in the data to be written to the data reading storage unit, and splice the first second byte number of bytes behind the current data; wherein the second byte number is less than or equal to the first byte number, and a sum of the current byte number and the second byte number is the first storage bit width.
In a third aspect, the present invention provides a chip comprising the data access circuit of any one of the previous embodiments.
In a fourth aspect, the present invention provides an electronic device comprising the chip of the foregoing embodiment.
Compared with the prior art, the invention provides a data access method, a data access circuit, a chip and electronic equipment, and relates to the field of FIFO data storage. The data access method is applied to a data access circuit, wherein the data access circuit comprises a byte counter, a data writing storage unit and a data reading storage unit, the byte counter is used for acquiring the current byte number, and the current byte number is the total number of all data bytes in the data writing storage unit and the data reading storage unit; the method comprises the following steps: when the number of the current bytes is smaller than a first storage bit width, the data writing storage unit shifts the current data in the data writing storage unit to the data reading storage unit; the first storage bit width is a fixed bit width of output data of the data reading storage unit; and when the number of the current bytes is greater than or equal to a first storage bit width, the data reading storage unit outputs data according to the first storage bit width. And determining the total number of bytes of all data in the data writing storage unit and the data reading storage unit by using a byte counter, and outputting according to the first storage bit width by using the data reading storage unit, so that the design area of the FIFO is saved, and the design risk of the FIFO is reduced.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a data access circuit according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating a data access method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another data access circuit according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating another data access method according to an embodiment of the present invention;
FIG. 5 is a flow chart illustrating another data access method according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of another data access circuit according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating another data access method according to an embodiment of the present invention;
fig. 8 is a schematic diagram of data access according to an embodiment of the present invention.
Icon: data access circuit-30, data write circuit 31, data read circuit-32, byte counter-33, data write memory cell-34, data read memory cell-35, and data shifter-36.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
When the data is written into the storage unit, the writing position of each data in the storage unit needs to be recorded, so that the data can be output according to the writing position of the data in the storage unit when the storage unit outputs the data; in order to determine the position to be written of the next write data in the storage unit, it is further required to record the current storage position of the remaining data in the storage unit, and determine whether the data to be written can be written into the storage unit. Therefore, in the prior art, data storage of the FIFO needs a write circuit for complex branch judgment and a read circuit for complex branch judgment, and there are multiple links that are prone to error in the design process, such as calculating bit width conversion rules, enumerating read/write judgment cases, and designing the number of storage circuit groups.
To solve at least the above problems and the disadvantages of the prior art, a data access circuit is disclosed, referring to fig. 1, wherein fig. 1 is a schematic structural diagram of a data access circuit according to an embodiment of the present invention. The data access circuit 30 includes a byte counter 33, a data write storage unit 34, and a data read storage unit 35, where the byte counter 33 is used to obtain the current byte number, which is the total number of bytes of all data in the data write storage unit 34 and the data read storage unit 35.
The data writing storage unit 34 is configured to shift the current data written in the data writing storage unit 34 to the data reading storage unit 35 when the current byte number is smaller than the first storage bit width. The first storage bit width is a fixed bit width of the output data of the data reading storage unit 35, for example, the output bit width of the data reading storage unit 35 is fixed to 10 bytes (bit).
The data reading storage unit 35 is configured to output data according to the first storage bit width when the current number of bytes is greater than or equal to the first storage bit width. For example, the data of the data access circuit 30 is output at 10 bits.
It should be understood that although fig. 1 illustrates the data access circuit 30 as including 2 memory cells, those skilled in the art may use more memory cells to obtain the data access circuit so as to implement the data access method provided by the present invention.
Referring to fig. 2, fig. 2 is a flow chart illustrating a data access method according to an embodiment of the present invention, based on the data access circuit 30 shown in fig. 1. The data access method is applied to the data access circuit 30, and comprises the following steps:
and S41, when the number of the current bytes is less than the first storage bit width, the data writing storage unit shifts the current data in the data writing storage unit to the data reading storage unit.
The first storage bit width is a fixed bit width of output data of the data reading storage unit. It should be understood that, with the data access method provided in the embodiments of the present invention, the current data written in the storage unit can be shifted to the data reading storage unit, compared with the prior art that the storage location of the current data is recorded, and the rule is calculated according to the storage location of the current data and the data to be written, which reduces more calculation amount and reduces the risk of FIFO data storage.
And S42, when the number of the current bytes is greater than or equal to the first storage bit width, the data reading storage unit outputs data according to the first storage bit width.
For example, when the number of the current bytes is greater than or equal to the first storage bit width, the data reading storage unit outputs data in a format corresponding to the high and low bits according to the first storage bit width. It should be understood that in the design process of the data access circuit of the FIFO, the output bit width of the data reading storage unit is fixed as the first storage bit width, so that the design area of the FIFO is greatly saved, and the bit width conversion rule does not need to be calculated during data output, thereby reducing the design risk of the FIFO.
It should be understood that the byte counter 33, the data write storage unit 34, and the data read storage unit 35 may cooperatively implement the above-described S41-S42 and possible sub-steps thereof.
In an alternative embodiment, there may be a case where the data writing storage unit and the data reading storage unit store more data and data writing cannot be achieved, and to solve the problem, on the basis of fig. 1, taking the data access circuit further includes a data reading circuit as an example, please refer to fig. 3, and fig. 3 is a schematic structural diagram of another data access circuit provided in an embodiment of the present invention.
The data access circuit 30 also includes a data write circuit 31 and a data read circuit 32. The byte counter 33 is connected to the data write circuit 31 and the data read circuit 32, respectively, the data write circuit 31 is connected to the data write memory cell 34 and the data read memory cell 35, respectively, the data write circuit 31 has a timing signal terminal (clock), a write enable terminal (en _ wr) and a data write terminal (da _ wr [ N1-1:0]), and the data read circuit has a read enable terminal (en _ rd) and a data read terminal (da _ rd [ N2-1:0 ]).
Taking the data access circuit 30 shown in fig. 3 as an example, in order to achieve smooth reading and writing of data, a possible implementation manner is provided on the basis of fig. 2, please refer to fig. 4, and fig. 4 is a flowchart illustrating another data access method provided by an embodiment of the present invention. The above 42 may include:
s421, the data reading circuit determines whether the current byte number is greater than or equal to the first storage bit width.
If yes, go to S422; if the current byte number is less than the first storage bit width, S421 is performed.
S422, the data reading storage unit outputs data according to the first storage bit width.
It can be understood that, if the number of the current bytes is greater than or equal to the first storage bit width, it indicates that the current data written in the data writing storage unit and the data reading storage unit is the output condition of the data access circuit, so that the data reading circuit reads the data in the data reading storage unit according to the first storage bit width. It is contemplated that the data reading circuit may periodically perform S421 described above.
It should be understood that the data reading circuit 32 and the data reading storage unit 35 described above may implement the above-described S421 to S422 and possible sub-steps thereof in cooperation.
In many cases, the data reading speed is faster than the data writing speed, and in order to make the data reading and writing more effective, a possible implementation manner is given on the basis of fig. 4, please refer to fig. 5, and fig. 5 is a flowchart illustrating another data access method provided in the embodiment of the present invention. The data access method may further include:
s43, the data writing storage unit receives the data to be written.
The number of the first bytes of the data to be written is less than or equal to the second storage bit width, and the maximum number of bytes stored by the data written into the storage unit is the second storage bit width. The number of the first bytes of the data to be written is less than or equal to the second storage bit width, so that the data to be written can be smoothly written into the storage unit. The data write circuit 31 and the data write memory unit 34 described above may implement a process of writing the received data to be written to the data write memory unit in cooperation. For example, when the clock signal provided by the clock is present and the en _ wr write enable is active, the data to be written is written to the data write memory cells by da _ wr [ N1-1:0 ].
It should be appreciated that in one possible embodiment, the first storage bit width may be less than or equal to the second storage bit width, such that the data access circuitry provided by the present invention may be a FIFO design circuit that converts read and write data from a multi-bit width to a small bit width; in another possible embodiment, the first storage bit width may be greater than the second storage bit width, so that the data access circuit provided by the present invention may be a FIFO design circuit that converts read and write data from a small bit width to a large bit width.
In order to reduce the read circuit for complicated branch judgment in the FIFO design, a possible implementation is given on the basis of fig. 3, please refer to fig. 6, and fig. 6 is a schematic structural diagram of another data access circuit according to an embodiment of the present invention. The data access circuit 30 also includes a data shifter 36.
The data shifter 36 is used to shift the current data to the data read memory unit when the current number of bytes is less than the first memory bit width. The data shifter 36 is further configured to shift the first second byte number of bytes in the data to be written to the data reading storage unit, and splice the first second byte number of bytes after the current data. And the sum of the current byte quantity and the second byte quantity is the first storage bit width.
It should be understood that, since the fixed bit width of the data output by the data reading storage unit 35 is the first storage bit width, in order to enable the data reading storage unit to output the data smoothly each time, it is necessary to shift the current data to the data storage unit, and splice the first second bytes in the data to be written after the current data, so that the current data and the data to be written form one data that can be output by the data reading storage unit according to the first storage bit width.
Taking the data access circuit 30 shown in fig. 6 as an example, a possible implementation manner is given on the basis of fig. 5, please refer to fig. 7, and fig. 7 is a flowchart illustrating another data access method according to an embodiment of the present invention. The above S41 may include:
s411, when the number of the current bytes is smaller than the first storage bit width, the data shifter shifts the current data to the data reading storage unit.
It can be understood that shifting the current data to the data reading storage unit can reduce the influence of the data writing storage unit receiving the data to be written. For example, since it is not necessary to record the remaining data of the data write memory unit, the data write memory unit can write and store the data to be written in according to the high-low order, which significantly reduces the need for a write circuit with complex branch judgment in the prior art (if the bit widths of the input and output data have no multiple relationship, the data access circuit needs to perform a lot of judgments according to the input bit and the output bit, thereby judging which bit positions of the memory unit the data is written in).
S412, the data shifter shifts the first second byte number of bytes in the data to be written to the data reading storage unit, and splices the first second byte number of bytes behind the current data.
And the sum of the current byte quantity and the second byte quantity is the first storage bit width.
It can be understood that, the current data (i.e. the remaining data) and the data to be written in the data writing storage unit and the data reading storage unit are spliced, so that the data can be output in a first-in first-out manner. It should be noted that, with the data access method provided by the present invention, because the output bit width of the data reading storage unit is fixed (the first storage bit width), a reading circuit that needs complex branch judgment in the prior art is reduced (if there is no multiple relation between the bit widths of the input and output data, the reading circuit needs to perform a lot of judgments according to the input bit and the output bit, so as to judge which bit positions of the storage unit are read), and the processing load of calculating the bit width conversion rule and enumerating the number of read/write judgments and design storage circuit groups is reduced.
In an optional embodiment, after outputting the data according to the first storage bit width, the data access method may further include: and the byte counter subtracts the first storage bit width from the current byte number to obtain the updated current byte number.
In an alternative embodiment, after the data writing storage unit receives the data to be written, the data access method may further include: the byte counter adds the current byte number to the first byte number to obtain an updated current byte number.
For example, if the current byte number is M0, the first storage bit width is M1: when reading a piece of data, the current byte number becomes (M0-M1); when one data (the number of bytes is M2) is written, the current number of bytes becomes (M0+ M2).
Next, on the basis of the data access circuit shown in fig. 6, in order to facilitate understanding of the above data access method, please refer to fig. 8, and fig. 8 is a schematic diagram of data access according to an embodiment of the present invention. The data access circuit comprises a data write-in storage unit and a data read-out storage unit, and the total number of the storage units is 24 (14 input bit widths and 10 output bit widths); the byte counter is used for recording the number of bits left after data is written or read, namely the number of current bytes.
Write circuitry that splices and shifts the write data and the remaining data (i.e., the current data) to a fixed memory cell location according to a byte counter, see the process of "shift 2 → input bus write 2 → shift 3".
The data reading circuit reads the stored values of the fixed memory cell (data reading memory cell) corresponding to the high and low bits of the output bit width, and the output contents of the shift 1 → output bus read 1 are bit 4-bit 13.
And each clock edge of the byte counter calculates the total residual bit data of the data writing storage unit and the data reading storage unit according to the en _ wr writing enable and the reading enable. When 1 data is written (the number of bytes is N1), adding N1 to the current number of bytes in the byte counter, and subtracting N2 from the counter when 1 data is read (the number of bytes is N2);
the data writing circuit is enabled at each clock edge and en _ wr write, and according to the last reading of the remaining data bit and the current writing and splicing of the da _ wr data by the byte counter (the remaining data is spliced to a high bit), the data is written into the data reading storage unit and the data writing storage unit (the spliced data is sequentially written into the high bit to the low bit of the data reading storage unit from the high bit to the low bit, exceeds the storage range of the data reading storage unit, and is then stored into the data writing storage unit from the high bit to the low bit, such as the process of 'input bus writing 1 → shifting 1' shown in fig. 8).
The data reading circuit determines whether to read the data in the data reading memory cell once according to whether the value of the byte counter is greater than the first storage bit width (10 bits shown in fig. 8).
If the byte counter value is 0, it indicates that there is no remaining stored data in the storage unit (i.e., the data read storage unit and the data write storage unit) of the FIFO, and when a piece of data is written, the data is written into the storage unit according to the bit-high bit of the data read storage unit and the bit-low bit of the data write storage unit, and the data to be written is stored, as shown in "input bus write 1" in fig. 8.
If the byte counter value is not 0, the FIFO memory cell (i.e. the data read memory cell and the data write memory cell) has the remaining stored data (i.e. the current data), and when data is written, the remaining data of the data read memory cell and the newly written data are spliced (the data in the cell is spliced at the high bit and the newly written data is spliced at the low bit) according to the byte counter value, and the spliced data is stored in the format of "input bus read 1 → shift 2 → input bus write 2 → shift 3" in fig. 8 according to the data read memory cell bit high bit and the data write memory cell bit low bit.
When the value of the byte counter is greater than the bit width of the output data (i.e., the first storage bit width), the process of reading the data of the data reading storage unit according to the format corresponding to the high and low bits is fixed, as shown in fig. 8, corresponding to "shift 1 → output bus read 1", and "shift 3 → output bus read 2".
It should be understood that the FIFO is a buffer circuit between input and output data, and generally includes a memory cell with a certain capacity, and it is more complicated to design a write-read circuit, and the present invention makes the design of the FIFO fixed at multiple places: the fixed FIFO memory cell bit number is the sum of the first memory bit width and the second memory bit width; writing into a fixed memory cell; reading the fixed storage unit; greatly saves the design area of the FIFO and reduces the design risk of the FIFO.
In addition, an embodiment of the present invention further provides a chip, where the chip includes the data access circuit in the above embodiment. The chip has signal processing capability, and may be, but is not limited to, a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. The chip can be applied to electronic equipment needing displaying, such as mobile phones, tablet computers, notebook computers, servers, intelligent wearable equipment, intelligent household appliances and the like, and can also be applied to routers, network switching equipment and the like with a displaying function.
The embodiment of the invention also provides electronic equipment, which comprises the chip in the embodiment. The electronic device may be, but is not limited to, a Mobile phone, a tablet Computer, a wearable device, an in-vehicle device, an Augmented Reality (AR)/Virtual Reality (VR) device, a notebook Computer, an Ultra-Mobile Personal Computer (UMPC), a netbook, a Personal Digital Assistant (PDA), and other electronic devices, and the embodiment of the present application does not set any limitation to specific types of the electronic device. Wearable devices may include, but are not limited to, smart watches, smart bracelets, smart glasses, and the like.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, the functional modules in the embodiments of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In summary, the present invention provides a data access method, a data access circuit, a chip and an electronic device, and relates to the field of FIFO data storage. The data access method is applied to a data access circuit, the data access circuit comprises a byte counter, a data write-in storage unit and a data read-out storage unit, the byte counter is used for acquiring the current byte number, and the current byte number is the total number of bytes of all data in the data write-in storage unit and the data read-out storage unit; the data access method comprises the following steps: when the number of the current bytes is smaller than the first storage bit width, the data writing storage unit shifts the current data written in the data writing storage unit to the data reading storage unit; the first storage bit width is a fixed bit width of output data of the data reading storage unit; and when the number of the current bytes is greater than or equal to the first storage bit width, the data reading storage unit outputs data according to the first storage bit width. And the total number of bytes of all data in the data writing storage unit and the data reading storage unit is determined by using the byte counter, and the data reading storage unit is used for outputting according to the first storage bit width, so that the design area of the FIFO is saved, and the design risk of the FIFO is reduced.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A data access method is characterized by being applied to a data access circuit, wherein the data access circuit comprises a byte counter, a data writing storage unit and a data reading storage unit, the byte counter is used for acquiring the current byte number, and the current byte number is the total number of bytes of all data in the data writing storage unit and the data reading storage unit; the method comprises the following steps:
when the number of the current bytes is smaller than a first storage bit width, the data writing storage unit shifts the current data in the data writing storage unit to the data reading storage unit; the first storage bit width is a fixed bit width of output data of the data reading storage unit;
and when the number of the current bytes is greater than or equal to a first storage bit width, the data reading storage unit outputs data according to the first storage bit width.
2. The method of claim 1, wherein the data access circuit further comprises a data read circuit;
when the number of the current bytes is greater than or equal to a first storage bit width, the data reading storage unit outputs data according to the first storage bit width, including:
the data reading circuit judges whether the current byte quantity is greater than or equal to the first storage bit width;
and if so, the data reading storage unit outputs data according to the first storage bit width.
3. The method of claim 2, further comprising:
the data writing storage unit receives data to be written;
the number of the first bytes of the data to be written is less than or equal to a second storage bit width, and the maximum number of bytes stored by the data writing storage unit is the second storage bit width.
4. The method of claim 3, wherein the data access circuit further comprises a data shifter;
when the number of the current bytes is smaller than a first storage bit width, the data writing storage unit shifts the current data in the data writing storage unit to the data reading storage unit, and the method includes:
when the number of the current bytes is smaller than a first storage bit width, the data shifter shifts the current data to the data reading storage unit;
the data shifter shifts the first second byte number of bytes in the data to be written to the data reading storage unit, and splices the first second byte number of bytes behind the current data;
wherein the second byte number is less than or equal to the first byte number, and a sum of the current byte number and the second byte number is the first storage bit width.
5. A data access circuit comprises a byte counter, a data write storage unit and a data read storage unit;
the byte counter is used for acquiring the number of the current bytes; the current byte number is the total number of bytes of all data in the data writing storage unit and the data reading storage unit;
the data writing storage unit is used for shifting the current data in the data writing storage unit to the data reading storage unit when the number of the current bytes is smaller than a first storage bit width; the first storage bit width is a fixed bit width of output data of the data reading storage unit;
and the data reading storage unit is used for outputting data according to the first storage bit width when the current byte number is greater than or equal to the first storage bit width.
6. The data access circuit of claim 5, wherein the data access circuit further comprises a data read circuit;
the data reading circuit is used for judging whether the current byte number is greater than or equal to the first storage bit width;
and the data reading storage unit is further used for outputting data according to a first storage bit width when the number of the current bytes in the data reading storage unit is greater than or equal to the first storage bit width.
7. The data access circuit of claim 6, wherein the data write memory cell is further configured to receive data to be written;
the number of the first bytes of the data to be written is less than or equal to a second storage bit width, and the maximum number of bytes stored by the data writing storage unit is the second storage bit width.
8. The data access circuit of claim 7, wherein the data access circuit further comprises a data shifter;
the data shifter is used for shifting the current data to the data reading storage unit when the number of the current bytes is smaller than a first storage bit width;
the data shifter is further configured to shift a first second byte number of bytes in the data to be written to the data reading storage unit, and splice the first second byte number of bytes behind the current data;
wherein the second byte number is less than or equal to the first byte number, and a sum of the current byte number and the second byte number is the first storage bit width.
9. A chip comprising a data access circuit as claimed in any one of claims 5 to 8.
10. An electronic device comprising the chip of claim 9.
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