JP2010086321A - Memory control system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To quickly carry out decompression processing of a compressed program by using hardware when transferring the compressed program stored in a low-speed memory device to a high-speed memory device. <P>SOLUTION: A reversibly compressed program is read from a program memory 2 as the low-speed memory device by a read DMAC 12 to be decompressed by a pipeline circuit 8. In the pipeline circuit 8, decompression is carried out by pipeline processing to prevent failure in following of input of the compressed data due to low speed of decompression processing. Thereby decompression processing of the compressed program read from the program memory 2 is carried out continuously, the program can be transferred from the program memory 2 to a main memory 3 as the high-speed memory device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory control system for transferring a program stored in a low-speed memory device to a high-speed memory device at high speed.

  In order for a CPU to execute a program stored in a low-speed memory device such as a NOR flash memory, a NAND flash memory, an SRAM, or a hard disk device, the program is transferred to a high-speed memory device such as a DRAM. When the program is transferred as it is, since the read operation from the low-speed memory device is performed at a low speed, the transfer takes time and the system cannot be speeded up. In addition, the program may be stored in a low-speed memory device in a compressed state in order to improve memory utilization efficiency. In this case, since the expansion is performed by software when the program is transferred to the high-speed memory device, the transfer often takes longer than when the program is not compressed.

On the other hand, Patent Document 1 describes that a compressed program is decompressed by hardware. In this configuration, the compressed program read from the ROM is decompressed by decompression hardware provided in the ROM interface and stored in the RAM, and then the CPU is activated.
JP 2007-148865 A (released on June 14, 2007)

  Patent Document 1 discloses that a program compressed by hardware is decompressed, but a specific decompression method is not disclosed. When decompressing a program by hardware, it takes a longer time to decompress the compressed program than it takes to retrieve the compressed program read from the ROM, and reading of the compressed program is delayed. This becomes more conspicuous as the compression algorithm becomes complicated and the size of input data to the decompression circuit changes dynamically. For this reason, there arises an inconvenience that the activation of the CPU is delayed.

  The present invention has been made in view of the above-described problems. When a compressed program stored in a low-speed memory device is transferred to the high-speed memory device, the decompression process of the compressed program is performed at high speed using hardware. An object of the present invention is to provide a memory control system.

  In order to solve the above problems, a memory control system according to the present invention includes a first memory device that stores a compressed program and an uncompressed program for activation, and a second memory device that operates at a higher speed than the first memory device. And a transfer circuit for decompressing the compressed program read from the first memory device and transferring it to the second memory device, and executing the decompressed compressed program transferred to the second memory device And a CPU that executes the uncompressed program at startup, and the transfer circuit includes a decompression circuit that decompresses the compressed program by pipeline processing after the CPU is activated.

  In the above configuration, when the compressed circuit is transferred from the first memory device to the second memory device by the transfer circuit, the CPU is first activated by the uncompressed program read from the first memory device, that is, the activation program. Is done. Thereafter, the program read from the first memory device is executed by pipeline processing by the decompression circuit. Specifically, for example, the decompression circuit determines a read address based on a first step of holding the compressed program read from the first memory device and an appearance frequency of instructions in the compressed program. Two steps and a third step of reading a value before compression corresponding to the encoded code of the compression program based on the read address are sequentially executed in parallel.

  Thereby, a series of processes in which the decompression process is composed of a plurality of stages (a plurality of processes) are repeatedly performed in parallel. Therefore, the time required for the decompression process can be shortened.

  In addition, since the decompression circuit decompresses the compressed program after the CPU is activated, priority is given to the activation of the CPU, so that a delay in the activation of the CPU can be avoided.

  In the memory control system, the uncompressed program is preferably smaller than the compressed program. Since the activation program is used only for activation of the CPU, it is generally smaller than the program before compression of the compression program transferred to the second memory device, and in many cases can be created extremely small. For this reason, the start of decompression of the compression program can be accelerated.

  The memory control system preferably includes a read DMAC that reads the compressed program stored in the first memory device to the decompression circuit. As a result, the compressed program can be read from the first memory device to the decompression circuit at high speed.

  The memory control system includes a FIFO memory that stores the program decompressed from the compressed program by the decompression circuit, and a write DMAC that writes the program output from the FIFO memory to the second memory device. Is preferred. As a result, even if the bandwidth of the program output from the decompression circuit changes dynamically, it can be absorbed and the write timing to the second memory device can be adjusted. Further, by using the write DMAC, the program can be written from the FIFO memory to the second memory device at a high speed.

  As described above, the memory control system according to the present invention includes the first memory device that stores the compressed program and the uncompressed program for activation, the second memory device that operates at a higher speed than the first memory device, and the first memory device. A transfer circuit that decompresses the compressed program read from one memory device and transfers it to the second memory device; executes the decompressed compressed program transferred to the second memory device; A CPU that executes an uncompressed program, and the transfer circuit includes a decompression circuit that decompresses the compressed program by pipeline processing after the CPU is activated. Thereby, the time required for the decompression process can be shortened. Therefore, in the memory control system, in the process of transferring the compressed program from the first memory device to the second memory device, the decompression process of the compressed program can be performed at high speed using hardware without delaying the activation of the CPU. There is an effect that can be done.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 5 as follows.

  In FIG. 1 and FIG. 2, the connection lines between the circuits are such that a thick solid line represents a multi-bit signal line and a thin solid line represents a 1-bit signal line.

  As shown in FIG. 1, the memory control system 1 according to the present embodiment includes a program memory 2, a main memory 3, a CPU 4, a transfer circuit 5, and three-state buffers 6 and 7.

  The program memory 2 (first memory device) is composed of a low-speed memory device such as a NOR flash memory, a NAND flash memory, an SRAM, and a hard disk device. The program memory 2 stores a compressed program and an uncompressed program. When the read address is given to the address terminal ADD by the CPU 4, the program memory 2 outputs the stored uncompressed program from the data output terminal DATA. Further, when the read address is given to the address terminal ADD by a read DMAC 12 (see FIG. 2) described later, the program memory 2 outputs the stored compressed program from the data output terminal DATA.

  The compression program is a program such as an application program, and is transferred to the main memory 3 and stored in order to be executed by the CPU 4. The compression program is reversibly compressed by, for example, a Huffman code. This compressed program consists of normal instructions and high frequency instructions.

  The normal instruction is an instruction having the lowest appearance frequency in the program before compression, and is not compressed. The reason why the normal instruction is not compressed is that since the appearance frequency is the lowest, the influence on the reduction of the compression degree of the entire compression program is low, and the compression and decompression efficiency can be improved. This normal instruction is composed of 5 bytes, and the first 1 byte (first byte) is a code “00h” representing the normal instruction, and the remaining 4 bytes are a code representing the instruction body.

  A high-frequency instruction is an instruction that appears more frequently than a normal instruction. In this high-frequency instruction, a 32-bit (4 byte) instruction is compressed to 1 byte, and is configured with a value other than the above-mentioned “00h”.

  The uncompressed program is a program for starting up the CPU 4 (for operation after reset), and is not transferred to the main memory 3. The uncompressed program sets and activates the read DMAC 12 to be described later, and also detects the end of the operation of the read DMAC 12. Such an uncompressed program is smaller than the compressed program, and in many cases has an extremely small size, and has a short execution time. Therefore, from the start of the CPU 4 to the completion of the transfer process of the compressed program described later. The total processing time is not prolonged.

  The main memory 3 (second memory device) is a high-speed memory device such as a DRAM and operates faster than the program memory 2.

  The CPU 4 executes the above-described uncompressed program read from the program memory 2 to perform a startup process and execute the above-described compressed program that is decompressed and transferred to the main memory 3.

  The transfer circuit 5 is a circuit that transfers the compressed program stored in the program memory 2 to the main memory 3. The transfer circuit 5 reads and expands the compressed program from the program memory 2 and writes it to the main memory 3 while adjusting the write timing. The transfer circuit 5 will be described in detail later.

  The 3-state buffer 6 is a circuit for connecting and disconnecting the data bus 21 from the program memory 2, and when the bus acknowledge signal BACK from the CPU 4 becomes "L", the data bus 21 is connected and the bus acknowledge signal is connected. When the BACK becomes “H”, the data bus 21 is shut off. The 3-state buffer 7 is a circuit for connecting and disconnecting the address bus 22 to and from the program memory 2, and when the bus acknowledge signal BACK from the CPU 4 becomes "L", the address bus 22 is connected, and the bus acknowledge signal BACK When the signal becomes "H", the address bus 22 is shut off.

  Next, the transfer circuit 5 will be described in more detail.

  The transfer circuit 5 includes a pipeline circuit 8, a FIFO memory 9, a three-state buffer 10, a memory controller 11, a read DMAC 12, and a write DMAC 13. The memory control system 1 further includes a counter 14 and an AND gate 15 as shown in FIG.

  The pipeline circuit 8 is a circuit that decompresses the compressed program by performing decoding corresponding to the encoding applied to the compressed program read from the program memory 2. The pipeline circuit 8 performs the decompression by pipeline processing so as not to be in time for the input of the compression program because the decompression processing of the compression program is slow. The pipeline circuit 8 will be described in detail later.

  The FIFO memory 9 functions as a buffer memory that temporarily stores a program expanded by the pipeline circuit 8. As a result, the FIFO memory 9 absorbs even if the bandwidth (product of the data bit length and the speed) of the program output from the pipeline circuit 8 changes dynamically, The write timing can be adjusted. Further, the FIFO memory 9 is “H” when the storage area is empty (storable state), and is “L” when the storage area is not empty (output enabled state). OC is given to the write DMAC 13. The FIFO memory 9 continues to output the program during the period when the output control signal OC is “H”, stops the program storage during the period when the output control signal OC is “L”, and reads out the program. Do.

  The three-state buffer 10 is a circuit for connecting and disconnecting the data bus 21 from the FIFO memory 9, and when the bus acknowledge signal BACK from the CPU 4 becomes "H", the data bus 21 is connected and the bus acknowledge signal is connected. When the BACK becomes “L”, the data bus 21 is shut off.

  The memory controller 11 is a circuit that controls writing of a program from the FIFO memory 9 to the main memory 3 and reading of the program from the main memory 3 to the CPU 4.

  The read DMAC 12 is a circuit that controls reading of the compressed program from the program memory 2 to the pipeline circuit 8. The read DMAC 12 sets the bus request signal BREQ to “H” when acquiring the bus right from the CPU 4, and sets the bus request signal BREQ to “L” when transferring the bus right to the CPU 4. The read DMAC 12 gives a control signal for controlling the expansion to the pipeline circuit 8.

  The write DMAC 13 is a circuit that controls reading of a program from the FIFO memory 9 to the memory controller 11. The write DMAC 13 outputs a read address to the address bus 22 when the output control signal OC from the FIFO memory 9 becomes “L”. The write DMAC 13 sets the bus request signal BREQ to “H” when acquiring the bus right from the CPU 4, and sets the bus request signal BREQ to “L” when delivering the bus right to the CPU 4. Further, when the output control signal OC from the FIFO memory 9 becomes “H”, the write DMAC 13 does not output the program from the FIFO memory 9 and therefore does not output the read address, but the output control signal OC becomes “L”. In some cases, since the program is output from the FIFO memory 9, the read address is output to the main memory 3.

  The memory controller 11 gives a program read from the FIFO memory 9 via the three-state buffer 10 to the main memory 3 together with a read address output from the write DMAC 13 to control program writing. Further, the memory controller 11 gives the read address from the CPU 4 to the main memory 3, thereby reading the program stored in the main memory 3 to the data bus and giving it to the CPU 4.

  Subsequently, the pipeline circuit 8 will be described in detail.

  As shown in FIG. 2, the pipeline circuit 8 includes selectors 81 and 82, registers 83 to 85, a NOR gate 86, a state machine 87, and a table ROM 88.

  The selector 81 outputs the compressed program (compressed 8-bit data) output from the program memory 2 when the value of the S terminal is “1”, while the value of the S terminal is “0”. At this time, the output data of the register 83 is output. The value input to the S terminal is generated by the counter 14 and the AND gate 15.

  The counter 14 is a 2-bit binary counter that counts the base clock signal BCLK. The AND gate 15 outputs “1” for one clock period each time the counter 14 counts the base clock signal BCLK for four clocks and outputs “11”. The output of the AND gate 15 is used as a ready signal RDY that controls reading of the program memory 2 by the read DMAC 12. In response to the ready signal RDY, the read DMAC 12 outputs the read address to the program memory 2 and changes the reset signal applied to the counter 14 from “1” to “0”. When the counter 14 is reset by this reset signal, the counter 14 is restarted.

  The NOR gate 86 outputs “1” only when the least significant bit of the 8-bit compressed program output from the program memory 2 is “0” and the above-described reset signal from the read DMAC 12 is “0”. .

  Register 83 holds the compression program output from selector 81 and the outputs of AND gate 15 and NOR gate 86 at the timing of base clock signal BCLK. The register 84 holds the compression program held in the register 83 at the timing of the base clock signal BCLK.

  The state machine 87 has an address output from the TBLADR terminal according to the combination of the state of the ready signal RDY input to the ROMRDY1 terminal and the compression program input from the NOR gate 86 input to the NCT terminal, from the NCEN terminal. This is a digital circuit that outputs the selector control signal to be output and the write control signal to be output from the WRTEN terminal at the timing based on the same base clock signal BCLK as the timing at which the register 83 holds the compressed program. The state machine 87 includes a 3-bit internal counter (not shown) that increments 1 each time each byte (first to fifth bytes) of the normal instruction is input from the NCT terminal. Recognize which byte is currently input. This internal counter is initialized when the fifth byte is counted.

  The process executed by the state machine 87 is performed to decode the Huffman code as shown in FIG. This decoding process will be described in detail later.

  In the table ROM 88, 8-bit data from the register 84 is input as the upper 8 bits (A9-A2) of the table address, and the address output from the TBLADR terminal of the state machine 87 is the lower 2 bits (A0, A0, It is input as A1). The table ROM 88 outputs 8-bit data (D7-D0) corresponding to the 10-bit table address (A9-A0) input as described above as write data. Specifically, as shown in FIG. 4, the table ROM 88 does not use the 4-byte area from the table address (A9-A0) from “000” to “003”, and the subsequent 4 bytes × 8 bits ( A 32-bit high frequency instruction (expanded code) expanded as one machine language is stored for each (1 word) area (a total of 255).

  The code obtained by the Huffman coding method has a smaller number of bits as the appearance frequency increases. When the compressed program is compressed by the Huffman coding method, the table ROM 88 is configured as a decoding table of Huffman-coded codes, and codes are stored in each table address in ascending order of the number of bits. Yes.

  The selector 82 outputs 8-bit data from the register 84 when the value of the S terminal becomes “1”, while the 8-bit data output from the table ROM 88 when the value of the S terminal becomes “0”. Output the data.

  The register 83 holds the data output from the selector 82 and the write control signal output from the WRTEN terminal of the state machine 87 at the timing of the base clock signal BCLK, and supplies the same to the FIFO memory 9.

  Next, state transition in the state machine 87 will be described. Here, an example will be described in which decoding is performed when a program is compressed using Huffman codes.

  As shown in FIG. 3, first, in the wait state of the program memory 2, when the value of the ROMRDY1 terminal is “0”, the value of the NCEN terminal, the value of the WRTEN terminal, the value of the TBLADR terminal, and the count value CNT of the internal counter The values of all become “0”. In this case, since the compressed program is not read from the program memory 2, the wait state is maintained.

[State transition (1)]
“(ROMRDY1 & NCT) = 1” indicates that the value of the ROMRDY1 terminal is “1” and the byte input to the NCT terminal is “00h” (normal instruction). In this case, the value of the NCEN terminal is “1”, while the count value CNT of the WRTEN terminal and the internal counter is “0”. In this case, the state transits to the normal instruction output process, and the first byte (00h) of the normal instruction held in the register 84 is output from the selector 82 and held in the register 85. However, “00h” is a code indicating that it is a normal instruction and is not an instruction main body, and therefore writing to the FIFO memory 9 is not performed.

[State transition (2)]
In the normal instruction output process, “(ROMRDY1 = 1) && (CNT! = 4)” indicates that the second to fourth bytes of the normal instruction are input. In this case, the value of the WRTEN terminal is set to “1”, and the count value CNT is incremented by one every time the second to fourth bytes are input. In this case, as in the state transition (1), the value of the value of the NCEN terminal is maintained at “1”, so the second to fourth bytes of the normal instruction output from the selector 82 are held in the register 84. And written in the FIFO memory 9.

[State transition (3)]
In the normal instruction output process, “(ROMRDY1 = 1) && (CNT = 4)” indicates that the fifth byte of the normal instruction is input. In this case, the value of the WRTEN terminal is set to “1”, and the count value CNT is initialized to prepare for the next count. In this case, as in the state transition (1), the value of the value of the NCEN terminal is maintained at “1”, so the fifth byte of the normal instruction output from the selector 82 is held in the register 84, It is written in the FIFO memory 9. Then, the state is returned to the wait state of the memory program 2.

[State transition (4)]
In the normal instruction output process, if the value of the ROMRDY1 terminal is “0”, the value of the WRTEN terminal is “0”. In this case, since the compressed program is not read from the program memory 2, writing to the FIFO memory 9 is not performed.

[State transition (5)]
“(ROMRDY1 & ^ NCT) = 1” indicates that the value of the ROMRDY1 terminal is “1” and the byte input to the NCT terminal is a code other than “00h” (normal instruction). In this case, the value of the NCEN terminal and the value of the TBLADR terminal are “0” (“00”), while the value of the WRTEN terminal is “1”. In this case, the state transitions to the high-frequency instruction decompression process, and the decompression code is read from the table ROM 88 based on the table address composed of the bytes input via the register 84 and the value of the TBLADR terminal. This decompressed code is held in the register 85 via the selector 82 and written into the FIFO memory 9.

[State transition (6)]
In the decompression process of the high-frequency instruction, when the value of the ROMRDY1 terminal is “0”, 1 is added to the value of the TBLADR terminal and output. In this case, since a new compressed program is not read, the table ROM 88 outputs a decompressed code at a table address obtained by adding 1 to the previous table address.

[State transition (7)]
In the decompression process of the high-frequency instruction, as in the state transition (5), when the byte input to the NCT terminal is a code other than the normal instruction as represented by “(ROMRDY1 & ^ NCT) = 1”, Maintain the decompression status of high-frequency instructions.

[State transition (8)]
In the high-frequency instruction decompression process, as in the state transition (1), when the byte input to the NCT terminal represents a normal instruction as represented by "(ROMRDY1 & NCT) = 1", the normal instruction output Transition to the processing state.

[State transition (9)]
In the decompression process of the high-frequency instruction, as in the state transition (5), when the byte input to the NCT terminal is a code other than the normal instruction as represented by “(ROMRDY1 & ^ NCT) = 1”, Transitions to the high-frequency instruction decompression processing state.

  Here, the program transfer operation of the memory control system 1 configured as described above will be described.

  First, when the CPU 4 is reset, the CPU 4 sets the bus acknowledge signal BACK to “L”, so that the 3-state buffer 6 connects the data bus 21 to the CPU 4 side and the 3-state buffer 7 connects the address bus 22 to the CPU 4 side. Connect to. As a result, the CPU 4 gives the read address to the program memory 2 so as to read the uncompressed program from the program memory 2. Then, the uncompressed program is read from the program memory 2 to the CPU 4 and executed by the CPU 4.

  The uncompressed program is defined to activate the read DMAC 12 when the execution is completed. Thus, when the activation process of the CPU 4 is completed, the read DMAC 12 is activated and sets the bus request signal BREQ to “H” so as to acquire the bus right from the CPU 4. Then, the CPU 4 sets the bus acknowledge signal BACK to “H” and transfers the bus right to the read DMAC 12. At this time, the 3-state buffer 6 disconnects the data bus 21 from the CPU 4 side, and the 3-state buffer 7 disconnects the address bus 22 from the CPU 4 side. The 3-state buffer 10 connects the data bus 21 between the FIFO memory 9 and the memory controller 11 side.

  In this state, the read DMAC 12 gives a read address to the program memory 2 and reads the compressed program to the pipeline circuit 8. In the pipeline circuit 8, decompression processing of the compressed program is performed by pipeline processing, and the compressed program is restored to the program before compression. Thereby, since the decompression process is parallelized, the time required for the parallel process is shortened, and the speed of the decompression process can be matched with the input speed of the compression program. Therefore, the compressed program can be read without interruption.

  The program decompressed (restored) by the pipeline circuit 8 is temporarily stored in the FIFO memory 9. At this time, since the write DMAC 13 is activated by the “H” bus acknowledge signal BACK, the program is read from the FIFO memory 9 during the period when the output control signal OC from the FIFO memory 9 is “L”. The write DMAC 13 also outputs a read address to the memory controller 11. The read program is output to the memory controller 11 via the three-state buffer 10, and is written by the memory controller 11 in an area specified by the read address of the main memory 3. By temporarily storing the program expanded by the pipeline circuit 8 in the FIFO memory 9, even if the bandwidth of the output of the pipeline circuit 8 changes dynamically, it can be absorbed.

  Next, the decompression operation in the pipeline circuit 8 will be described.

  First, the compressed program (read data) read from the program memory 2 is input to the selector 81. At this time, as shown in FIG. 5, the counter 14 counts the base clock signal BCLK, and the AND gate 15 is set to “1” by the output counted by the counter 14 for four clocks from the start of counting. A ready signal RDY is output. Thereby, the selector 81 selects and outputs the read data. The clock of the base clock signal BCLK at this time is set as the first clock CL1.

  Further, when the ready signal RDY becomes “1”, the reset signal RST from the read DMAC 12 becomes “0” for one clock of the base clock signal BCLK, whereby the counter 14 is reset and the count of the base clock signal BCLK is counted. Resumed. This reset signal RST is also input to the NOR gate 86. Further, 8-bit read data from the program memory 2 is input to the NOR gate 86.

  When the read data is a normal instruction, the first first byte is input to the register 83 via the NOR gate 86. If the read data is a high-frequency instruction, the 1 byte is input to the register 83 via the NOR gate 86. The output of the NOR gate 86 is held in the register 83 together with the ready signal RDY and the read data from the selector 81 at the timing of the second clock CL2 following the first clock CL1. Thus, the process until the output of the selector 81, the output of the NOR gate 86, and the ready signal RDY are held in the register 83 is the first stage.

  The read data held in the register 83 is held in the register 84 at the timing of the third clock CL3 following the second clock CL2. The output (read data) of the NOR gate 86 and the ready signal RDY (“1”) held in the register 83 are input to the ROMRDY1 terminal and the NCT terminal of the state machine 87, respectively. In the state machine 87, the values of the NCEN terminal, the WRTEN terminal, and the TBLADR terminal are determined at the timing of the third clock CL3.

  As described above, the process from the end of the first stage to the holding of the compressed program in the register 84 and the determination of the values of the NCEN terminal, the WRTEN terminal, and the TBLADR terminal by the state machine 87 is the second stage.

  In the table ROM 88, the 8-bit read data held in the register 84 and the 2-bit value of the TBLADR terminal are given. The decompressed code (restored value) stored in the area specified by the 10-bit table address (A9-A0) is output to the selector 82 as a decompressed program, that is, output data (D7-D0).

  The selector 82 selects the output data from the table ROM 88 and outputs it to the register 85 because the value of the S terminal (the value of the NCEN terminal) is “0”. This output data is held in the register 85 together with the value of the WRTEN terminal output as a write control signal from the state machine 87 at the timing of the fourth clock CL4 following the third clock CL3. Then, the output data (program) held in the register 85 is written into the FIFO memory 9.

  Thus, the process from the end of the second stage to the data output from the table ROM 88 and the holding of the output from the selector 82 to the register 85 is the third stage.

  By performing the first to third stage processing as described above, in the case of a high-frequency instruction, one high-frequency instruction is expanded and written to the FIFO 9 in one cycle including the first to fourth clocks CL1 to CL4. It is. In the case of a normal instruction, the first byte read in the period of the first clock CL1 is held in the registers 83 to 85 in the subsequent second to fourth clocks CL2 to CL4, respectively. The fourth byte is read and held in the same manner. Accordingly, a cycle consisting of the first to fourth clocks CL1 to CL4 is repeated five times, so that one normal instruction for five bytes is written into the FIFO 9.

  Here, parallel processing in the pipeline circuit 8 will be described.

  In the period of the second clock CL2 in which the read data is taken into the register 83 in the first stage, the counter 14 resumes counting the base clock signal BCLK, and has reached the count of 4 clocks. Therefore, the ready signal RDY that is the output of the AND gate 15 becomes “0”. For this reason, read data is not read from the read DMAC 12. In addition, since the S terminal of the selector 81 is “0”, the read data held in the register 83 in the previous first stage is input to the register 83 via the selector 83 in the first stage this time. It is held again at the timing of 3 clocks CL3. Also in the second stage of this time, the value of the ROMRDY1 terminal is “0”. Therefore, in the case of high-frequency instruction decompression processing, the read data state machine 87 sets the value of the TBLADR terminal to 1 at the timing of the fourth clock CL4. Are added (state transition (6)).

  In this third stage, A0 and A1 input to the table ROM 88 are increased by 1, so that the table address is changed. As a result, the decompressed code stored in an area different from the decompressed code read from the table ROM 88 in the previous third stage is output from the selector 82 and held in the register 85 at the timing of the first clock CL1 of the next cycle. Further, it is written in the FIFO memory 9.

  As described above, in the case of a high-frequency instruction, the state machine 87 sequentially adds 1 to the value of the TBLADR terminal until the count of the base clock signal BCLK by the counter 14 reaches a count of 4 clocks. Different output data is read from the table ROM 88 even during the second to fourth clocks CL2 to CL4 during which no data is read.

  As described above, the processes of the first to third stages are repeatedly performed in parallel based on the timing of the base clock signal BCLK, so that the decompression process is performed without delaying the reading of the compressed program from the program memory 2. be able to. Therefore, when the compressed program is compressed to 1 / N, the program can be transferred from the program memory 2 to the main memory 3 at a speed approximately N times that when the compressed program is not compressed.

  In this embodiment, an example in which the compression program is encoded using the Huffman encoding method is described. However, the encoding method of the compression program is not limited to the Huffman encoding method, and other lossless types may be used. It is also possible to use the compression encoding method.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The memory control system of the present invention reads a reversibly compressed program from a low-speed memory device, decompresses it by pipeline processing, and transfers it to the high-speed memory device. It is avoided that the input is not in time, and the program can be transferred from the low-speed memory device to the high-speed memory device at high speed. For this reason, it can be suitably used for speeding up the operation of the system including the memory control system.

It is a block diagram which shows the structure of the memory control system which concerns on embodiment of this invention. It is a block diagram which shows the structure of the pipeline circuit in the said memory control system. It is a figure which shows the transition state of the process performed with the state machine in the said pipeline circuit. It is a figure which shows the structure of the data storage in the table ROM in the said pipeline circuit. It is a timing chart which shows operation | movement of the said pipeline circuit.

Explanation of symbols

1 Memory Control System 2 Program Memory (First Memory Device)
3 Main memory (second memory device)
4 CPU
5 Transfer circuit 8 Pipeline circuit (extension circuit)

Claims (5)

A first memory device for storing a compressed program and an uncompressed program for activation;
A second memory device operating at a higher speed than the first memory device;
A transfer circuit for decompressing the compressed program read from the first memory device and transferring the decompressed program to the second memory device;
A CPU for executing the decompressed compressed program transferred to the second memory device and executing the uncompressed program at the time of activation;
The memory control system, wherein the transfer circuit includes a decompression circuit that decompresses the compressed program by pipeline processing after the CPU is activated.   The memory control system according to claim 1, wherein the uncompressed program is smaller than the compressed program.   3. The memory control system according to claim 1, further comprising a read DMAC that reads the compressed program stored in the first memory device to the decompression circuit. A FIFO memory for storing a program decompressed from the compressed program by the decompression circuit;
The memory control system according to claim 3, further comprising a write DMAC that writes the program output from the FIFO memory to the second memory device.   The decompression circuit includes a first step of holding the compressed program read from the first memory device, a second step of determining a read address based on an appearance frequency of instructions in the compressed program, and the read address 5. The memory control according to claim 1, wherein a third step of reading a value before compression corresponding to an encoded code of the compression program is sequentially executed in parallel based on system.

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