SU1737440A1 - Device for software processing of digital data - Google Patents

Abstract

The invention relates to a digital data processing technique and may be used for software processing of digital information. The aim of the invention is to increase the efficiency of use by speeding up the process of processing digital information. The device operates on four clock cycles according to the program recorded in the shaper of 4 software processing commands. In the first cycle, a control word is generated, which is fed to the driver 10 of the control signals, to the address switch 8, to the switch 6 of operand A and to the decoder 5 commands. At the second cycle, the operand B is read, and the arithmetic logic processing unit 3 starts to perform the specified operation. In the third clock cycle, the arithmetic logic processing unit 3 finishes the calculation, and in the shaper 4 of the program processing commands, a new address word is recorded. In the fourth cycle, the result of processing in block 3 of arithmetic-logic processing is recorded in block 1 of the RAM and is fed through the output output direct access bus to port 2 of the output. 1 il. (Ls.

Description

The invention relates to a digital data processing technique, namely, devices for software processing of digital information.

A device for software processing of digital information is known, which contains a block of random-access memory connected to a driver of control signals and connected between input and output ports.

A disadvantage of the known device for software processing of digital information is that it does not allow to provide in some cases the required performance when processing digital information in real time.

It is also known a device for digital information processing comprising a RAM block connected by an output direct access bus to an input access direct bus of the output port and connected by an input data bus to an output data bus of an arithmetic logic processing unit connected by an output transfer bus to the input the transfer bus of the program processing command generator and the control signal connected by the input bus to the first output bus of the command decoder, the input code of the operation code of which is Connected to the output bus of the operation code of the shaper of program processing commands, the driver of operating mode control signals, the Operand A switch, the Operand B switch, the address switch and the input port1.

The disadvantage of this device for software processing of information is the low efficiency of its use, which is due to the low speed of the process of processing digital information.

The aim of the invention is to increase the efficiency of use of the device for software processing of digital information by speeding up the process of processing digital information.

To this end, in a device for digital data processing, containing a block of RAM, connected by an output bus of direct access to an input bus of direct access to an output port and connected by an input bus of a data bus to an output data bus of an arithmetic logic unit connected to an output transfer bus to the input bus of the program processing command generator and the control signal connected by the input bus to the first output bus of the command decoder, the input operation code bus of which is One to the output bus of the program code shaper command processing operations, the control signal generator modes of operation, the switch

operand A, switch operand B, the address switch and the input port, the control signal output bus and the output interface of the program processing command addresses are connected respectively to

the control input signal and the input address bus of the driver of operating mode control signals, which are connected by the first, second, third and four outputs, respectively, to the input

the input port bus, the control switch input bus of the address switch, the control switch input bus of the operand B switch, and the control port of the output port control signal bus, and the input data bus

and output tire constants shaper

processing commands are connected

respectively with the output data bus

block arithmetic logic processing and

with the input bus constant switching

operand A, connected by the input bus of the control signal and the input bus of the battery, respectively, to the second output bus of the command decoder and to the output bus of the battery of the operating memory unit and connected by the output bus to the first input bus of the arithmetic and logic processing unit, the second data bus of which connected to the output bus of the switch of the operand B, connected by the first and second input data buses, respectively, with the output bus of the input port and the output data bus of the operational memory block A bus whose address bus is connected to the output bus of the address switch connected to the first and second data input buses, respectively, to the output bus of the address of the program processing command generator and to the output bus of the index register of the RAM.

The drawing shows one of the possible variants of the proposed device for software processing of digital information.

The device contains a block of 1 RAM, connected by a direct output access bus to the input direct bus of port 2 of the output and connected by an input data bus to the output data bus of the arithmetic logic processing unit 3, a programmer 4 commands, a decoder 5 commands, a switch 6 operand A, switch 7 operand 8, switch 8 addresses.

an input port 9 and a driver 10 for operating mode control signals. The arithmetic logic processing unit 3 is connected by the output bus to the input bus of the shaper of 4 commands by the processing software and connected by the input bus of the control signal to the first output bus of the decoder 5 commands connected by the input bus of the operation code to the output bus of the operation code of the 4 commands software processing.

The control signal output bus and the output address bus of the programmable processing command 4 are connected to the control signal input bus and the input address bus of the operating mode control signal generator 10, which is connected to the input, input port bus 9, respectively, by the first, second, third output bus. control signal input bus 6 of the address switch 6, to the control signal input bus of the operand switch commutator B and to the control signal input bus of the output port 2. At the same time, the input data bus and the output bus of the programmable processing constant 4 commands are connected respectively to the output data bus of the arithmetic logic processing unit 3 and to the input bus of the constants of the switch 6 of the operand A. The switch 6 of the operand A is connected to the input bus of the control signal and the input bus of the battery respectively, to the second input bus of the decoder 5 commands and to the output bus of the battery of the RAM unit 1 and connected by the output bus to the first input data bus of the block 3 of the arithmetic logic processing. The second input data bus of the arithmetic logic processing unit 3 is connected to the output bus of the switch of the operand B, connected by the first and second data input buses, respectively, to the output bus of the input port 9 and to the output bus of the operational memory 1. The address bus of the main memory unit 1 is connected to the output bus of the address switch 8 connected by the first and second data input buses, respectively, to the output address bus of the programmer 4 command of the program processing and to the output bus of the index register of the main memory unit 1.

The operation of the proposed device for processing digital information is as follows.

The driver 10 of the operating mode control signals controls the mode of operation of the input port 9 acting on the switch 7 of the operand B. Switch 7

Operand B connects the input port 9 to the arithmetic logic processing block 3, which allows processing the input port 9 data directly through the arithmetic logic processing block 3. An external signal from the input port 9 is fed to the first input data bus of the switch 7 of operand B, the second input data bus of which is supplied with data from the main memory unit 1. In this case, the information received from the input port and the RAM unit 1, depending on the signal, on the input bus of the control signal supplied from the operating mode control signal generator 10, passes to the second input data bus of the arithmetic logic processing unit 3. The first input data bus of the arithmetic logic processing unit 3 is supplied with the output bus of the switch 6 of operand A, which is determined by signals from the output bus of the constants of the shaper 4 software processing commands or from the output bus of the battery of the main memory 1 the second output bus of the decoder 5 commands, determined by the state of the output bus of the operation code of the driver 4 software processing commands. In this case, the block 3 of arithmetic logic processing performs arithmetic logic processing of information depending on the state of the output bus of the operation code of the shaper of 4 program processing commands. The result of processing in block 3 of arithmetic logic processing is fed to the input data buses of the RAM unit 1 and the driver 4. for the program processing and for the transfer bus for the driver 4 for the program processing. The signals on the input data bus and the transfer input bus of the programmer 4 instruction generator determine the state of its output operation code bus, output constant bus, output address bus, and control output bus. In this case, the implementation of the subsequent processing of ps information is provided to a program stored in the memory of the shaper of 4 instructions for program processing.

The device operates according to the program recorded in the shaper 4 teams processing software. At the same time, the specific algorithm of each step of the program determines the control word of the driver 4 program processing commands. The device operates in four cycles. In the first cycle, a control word is formed, which is fed to the driver 10 operating mode control signals, on

switch 8 addresses on the switch b operand A and the decoder 5 commands. Depending on the contents of the operation code, the decoder 5 of the commands is adjusted, operand A is selected (battery or constant) and the operations of block 3 of arithmetic logic processing are determined. If the control word address field contains a control command tag, the operating mode control signal generator 10 generates control signals that configure the operation of input port 9, address switch 8 or operand B switch 7. Operand B is read in the second cycle, and arithmetic unit 3 is read Logical processing starts performing the specified operation. In the third clock cycle, the arithmetic logic processing unit 3 finishes the calculation, and in the shaper 4 of the program processing commands, a new address word is recorded. In the fourth cycle, the result of processing in block 3 of arithmetic-logic processing is recorded in block 1 of the RAM and is fed through the output output direct access bus to port 2 of the output. In the next first cycle, the next control word is selected and a new cycle of operation of the device begins,

Claims (1)

The proposed device can be made in the form of a microcircuit and can improve the performance in real time and the efficiency of using hardware. An apparatus for programmatically processing digital information, comprising a RAM block connected by an output direct access bus to an input access direct bus of an output port and connected by an input data bus to an output data bus of an arithmetic logic unit connected by an output transfer bus to the input the transfer bus of the program processing command generator and the control signal connected by the input bus to the first output bus of the command decoder, the input code of the operation code which connected to the output bus of the operation code of the shaper of program processing commands, the shaper of operation mode control signals, the switch of operand A, the switch of operand B, the address switch and the input port, characterized in that, in order to increase the efficiency by using the processing of digital information, the output bus of the signal The control and output bus addresses of the program processing command generator are connected respectively to the control signal input bus and the input address bus of the operating mode control signal generator, which is connected by the first, second, third and fourth outputs, respectively, to the input bus of the input port, to the input bus of the address switch control signal , to the input bus of the control signal of the switch of the operand B and to the input bus of the control signal of the output port, and the input bus of the data and output bus of the constants software processing commands are connected respectively to the output data bus of the arithmetic logic processing unit and to the input bus constants of the operand switch A connected to the input bus of control constants and the battery input bus to the second output bus of the command decoder respectively and to the output memory bus of the memory unit and connected by the output bus to the first input data bus of the block arithmetic logic processing, the second input data bus of which is connected to the output bus of the switch of the operand B, connected by the first and second input data buses, respectively with the output bus of the input port and with the output bus of the data of the RAM, whose address bus is connected to the output bus of the address switch connected by the first and second input data buses, respectively, with the output bus of the address of the shaper of software processing instructions and with the output bus of the index register of the RAM.