CN102968396A - Special data transmission module from flash chip to static random access memory (SRAM) chip - Google Patents
Special data transmission module from flash chip to static random access memory (SRAM) chip Download PDFInfo
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Abstract
The invention provides a special data transmission module from a flash chip to a static random access memory (SRAM) chip, and the special data transmission module comprises an advanced peripheral bus (APB) interface module, a flash control module and an SRAM control module; the APB interface module is used for latching an address, data and chip selection from a bus and enabling a signal to control a time sequence; the flash control module is used for interacting with the APB interface module, acquiring data from an off-chip flash and transmitting the data to the SRAM control unit; and the SRAM control unit is used for writing the received data into an SRAM. Due to the adoption of the special data transmission module, the data transmission speed can be greatly increased; the application range is wide, convenience is realized and the transferability is high; and the intermittent occupation of the SRAM is supported, and the overall working efficiency of a system on chip (SOC) can be improved.
Description
Technical field
The present invention relates to embedded system and technical field of integrated circuits, specifically, the present invention relates to a kind of data transmission module.
Background technology
Along with the development of embedded system and integrated circuit, FLASH chip (following title FLASH) just is being applied to the abbreviation of embedded system and SOC(System on Chip more and more, is called system level chip, and the title SOC (system on a chip) is also arranged) in.FLASH has the storage density height, the characteristics that sense data is fast, and per unit storage price is low, is fit to mass data storage in embedded system.And SRAM is generally as buffer memory in the sheet, and characteristics are that speed is fast, needn't cooperate the memory refresh circuit, can improve whole work efficiency and more quick, power consumption very low (particularly power consumption is extremely low under idle condition).Therefore SRAM is first-selected high for bandwidth requirement, and perhaps the power consumption requirement is low, and perhaps the two haves both at the same time.In not having the chip of integrated in-chip FLASH, often need the data transmission among the FLASH that chip is external to arrive on-chip SRAM.
Prior art is mainly based on DMA(Direct Memory Access, direct memory access) controller realizes the data transmission between the different kinds of memory.Dma controller can be considered as a kind ofly can inside and outside storer and each being had the controller that the peripheral hardware of DMA ability couples together by one group of private bus.It is to carry out transmission under the programming Control of CPU, so the support of the software such as demand motive program.The data transmission that realizes FLASH to SRAM by software expends the clock period very much, and read or write speed is lower, often is not suitable in the embedded system.
Also having at present a class technology is design FLASH controller, with the read-write operation of hardware realization to FLASH.For example: Chinese patent application 200710164187.9, Chinese patent application 200810116296.8, Chinese patent application 201010513438.1 have disclosed respectively FLASH controller implementation separately.These technology have improved data rate to a certain extent.Yet the data copy of reading from FLASH still will rely on dma controller (or similar devices) to realize to the process of SRAM, and therefore the overall data transmission speed from FLASH to SRAM still has much room for improvement.On the other hand, in the prior art, data write and will continue to take SRAM in the SRAM process, can cause so the work efficiency of whole SOC to reduce.
In sum, current in the urgent need to a kind of hard-wired directly scheme from FLASH to the SRAM the transmission of data.
Summary of the invention
For overcoming the defective of above-mentioned prior art, the present invention proposes a kind of hard-wired directly scheme from FLASH to the SRAM the transmission of data.
The present invention proposes a kind of dedicated data transmission module from Flash to SRAM, comprise APB bus interface module, FLASH control module and SRAM control module; The APB bus control module is used for latching the address that bus is come, data, and the sheet choosing, enable signal is with the control sequential; The FLASH control module be used for the APB bus interface module mutual, FLASH obtains data and sends data to the SRAM control module outside sheet; The SRAM control module is used for the data that receive are write SRAM.
Wherein, described APB bus interface module comprises: read enable register, be used for latching the Read_Enable signal of APB bus; Read the type register, be used for latching the Read_Type signal of APB bus; The FLASH address register is used for latching the first address of getting the Flash data; The SRAM address register is for the first address of latching the SRAM receive data; The address size register is used for latching the transmission data length; Flash ID register is used for latching Flash ID; Flash Identification register is used for latching FlashIdentification; And in two kinds of read states register modes, the S15-8 position of latch mode register or S7-0 position.
Wherein, the reading manner of described FLASH control module comprises: single channel is read, binary channels is read, four-way read in one or arbitrarily multinomial combination.
Wherein, the mode that reads FLASH of described FLASH control module also comprises: read FLASH ID, read FLASH Identification, read FLASH status register high eight-bit and read low eight of FLASH status register.
Wherein, the SRAM data line is 32, reads be operating as 8 of FLASH at every turn, 32 bit registers is set in the described FLASH control module preserves the FLASH data, treats that 32 bit registers are filled just data are given to described SRAM control module.
Wherein, described FLASH control module arranges in turn receive data of two 32 bit register Reg_A and Reg_B, and when one of them transferred data to the SRAM control module, another was responsible for continuing to receive the data of FLASH.
Wherein, the input signal of described SRAM control module comprises: Flash_Write_Enable, Flash_DATA, the Flash_Operation_End of the output of FLASH control module, and Flash_Write_Enable is enable signal from data to SRAM that write; Flash_DATA is the data of FLASH transmission; Flash_Operation_End is that data transmit settling signal; The input signal of described SRAM control module also comprises: by the SRAM_Addr that the APB bus control module provides, and expression SRAM initial address.
Wherein, described APB bus control module comprises that also SRAM takies register, be used for to characterize SRAM and be and continue to take or intermittently take, the input signal of described SRAM control module also comprises: the SRAM_Possession that is provided by the APB bus control module, the occupancy mode that is used for SRAM, when continuing to take in the SOC (system on a chip) other modules except described dedicated data transmission module from Flash to SRAM can not take SRAM, when intermittently taking in the SOC (system on a chip) other modules except described dedicated data transmission module from Flash to SRAM can take SRAM.
Wherein, other modules except described dedicated data transmission module from Flash to SRAM comprise CPU or bus in the described SOC (system on a chip).
Wherein, described APB bus interface module also comprises interruption and processes submodule, and described reception is by the signal of APB bus input, and the setting of interrupt register is inputted by the APB bus.
Compared with prior art, the present invention has following technique effect:
1, the present invention has set up the straight channel to SRAM by FLASH, can greatly improve data rate.
2, applied range of the present invention, convenience and portable high.
3, the present invention can support taken the intermittence of SRAM, is conducive to improve the whole work efficiency of chip (SOC).
Description of drawings
Fig. 1 shows the overall construction drawing of a kind of dedicated data transmission module from Flash to SRAM of one embodiment of the invention;
The APB bus that Fig. 2 shows in the one embodiment of the invention is read transmission time sequence;
The APB bus that Fig. 3 shows in the one embodiment of the invention is write transmission time sequence;
Fig. 4 shows the single channel of the FLASH control module in the one embodiment of the invention and reads sequential;
Fig. 5 shows the binary channels of the FLASH control module in the one embodiment of the invention and reads sequential, wherein M=0XH or other non-AXH values;
Fig. 6 shows the binary channels of the FLASH control module in the one embodiment of the invention and reads sequential, wherein M=AXH;
Fig. 7 shows the four-way of the FLASH control module in the one embodiment of the invention and reads sequential, wherein M=0XH or other non-AXH values;
Fig. 8 shows the four-way of the FLASH control module in the one embodiment of the invention and reads sequential, wherein M=AXH;
What Fig. 9 showed FLASH control module in the one embodiment of the invention reads the ID sequential;
What Figure 10 showed FLASH control module in the one embodiment of the invention reads the Identification sequential;
Figure 11 shows the read states register sequential of the FLASH control module in the one embodiment of the invention, comprises that read states register high eight-bit S15 ~ 8 sequential and read states register hang down eight S7 ~ 0 sequential;
Figure 12 shows the FLASH control module state machine state transition diagram in the one embodiment of the invention;
Figure 13 shows the SRAM control module state machine transition diagram in the one embodiment of the invention.
Embodiment
Describe the present invention below in conjunction with the drawings and specific embodiments.
According to one embodiment of present invention, provide a kind of dedicated data transmission module from Flash to SRAM, its function is that data copy with plug-in FLASH is to on-chip SRAM.For SOC, adopt plug-in FLASH will greatly reduce chip cost, when reducing cost, carry out by copying program to SRAM by FLASH, can greatly improve executing efficiency.The plug-in FLASH capacity of SOC can be very large, can store large program, and the time-delay between program segment and section is not in the very important situation, can divide the segment call program in SRAM.
General structure and submodule are divided
The general structure of the dedicated data transmission module from Flash to SRAM of present embodiment can be divided into APB bus interface module, FLASH control module and SRAM control module as shown in Figure 1.APB bus interface module sequential is according to AMBA APB bus specification, main be responsible for the APB bus between communicate by letter with mutual, as latch the address that bus is come, data, sheet selects, and enables etc.The FLASH control module mainly be responsible for the APB bus interface module mutual, FLASH obtains data and sends data to the SRAM control module outside sheet.The SRAM control module is mainly finished by the data of FLASH control module to SRAM and is transmitted.Implementation procedure is introduced in modules in detail.
AMBA APB bus interface module
FLASH control module and SRAM control module are by APB bus interface module and the communication of APB bus interface.In one embodiment of the invention, the APB bus-in singal comprises clock signal PCLK, chip selection signal PSEL, reset signal PRESETn, address signal PADDR[31:0 ］, write data signal PWDATA ［ 31:0 ］; Comprise that also control signal group: PWRITE is read-write control signal, PENABLE is enable signal.Bus-out signal comprises read data PRDATA[31:0] and look-at-me Int_Output.The read-write of APB bus is according to the requirement of APB bus read-write sequence, as shown in Figure 2.
The APB bus is once read transmission and is comprised two clock period, when first cycle begins, the PSEL chip selection signal is effective, the PWRITE read-write control signal becomes low level, the expression read operation, in first clock period, the PENABLE enable signal keeps the low level disarmed state, and this moment, PRADATE did not begin read data, and namely data are invalid, when second period arrives, PENABLE becomes high level, and stable rear PRDATE begins read data, the time spent one-period, finish read data before second clock period finishes, then PENABLE and PSEL become low level.Writing in the transmission of APB bus, PWRITE is high level, and transmission is write in expression, and PWDATA writes data and namely begins to write data in first clock period, until two end cycles are write data and finished.Write all the other signal sequences of data and to read sequential identical, as shown in Figure 3.
In a preferred embodiment, the APB bus interface module also comprises interruption and processes submodule, is mainly used in interrupting processing.Interrupt processing submodule and mainly process various interruptions.The setting of this submodule is by APB bus input (setting of each interrupt register arranges by the APB bus).Interrupt signal output Int_Output is the output of interruption processing module.Interruption processing module comprises five registers.The output Write_End(of SRAM control module represents that the SRAM write operation finishes) and the output Read_Done(of FLASH control module represent that the FLASH read operation finishes) directly or indirectly trigger as the input of interrupting submodule and interrupt.
In one embodiment of the invention, comprise a plurality of registers in the APB interface module, the function of each register (wherein comprising five registers that interrupt processing submodule) is as shown in table 1.
Table 1
| Sequence number | The | Function | |
| 1 | Read_Enable_Reg | Read enable register, latch the Read_Enable signal of |
|
| 2 | Read_Type_Reg | Read the type register, latch the Read_Type signal of APB bus |
| 3 | Flash_Addr_Reg | The FLASH address register latchs the first address of getting the Flash |
| 4 | SRAM_Addr_Reg | The SRAM address register latchs the first address of SRAM receive |
| 5 | Addr_Length_Reg | The address size register latchs the |
| 6 | Flash?ID | Flash ID register latchs Flash |
| 7 | Flash?Information | Flash Identification register |
| 8 | Read_Stetus_Reg | In two kinds of read states register modes, the S15 of latch mode register ~ 8 or S7 ~ 0 |
| 9 | SRAM_Possesion | SRAM takies register, characterizes SRAM and be to continue to take or intermittently take |
| 10 | Spi_Reader_Int_Con[0] | Interrupt enable bit enables or disabled interrupt |
| 11 | Spi_Reader_Int_Con[1] | The interrupt mask enable bit enables or the |
| 12 | Spi_Reader_Int_Flag | Whether interruption status flag register, sign interrupt being triggered |
| 13 | Spi_Reader_Int_Overflow | Whether interruption status sign overflow register, sign interrupt overflowing |
| 14 | Spi_Reader_Int_MaskF | Whether interrupt flag register, sign interrupt triggering or conductively-closed |
| 15 | Spi_Reader_Int_Clear | Interrupt the zero clearing flag register, sign interrupts whether zero clearing |
The FLASH control module
In one embodiment, the FLASH of employing is GD25Q series, supports standard SPI interface, and maximum clock frequency can reach 120MHz, the highest 240MHz and 480MHz when binary channels mode and four-way mode.This FLASH has eight pins, and the definition of its each pin is as shown in table 2.
Table 2
| Title | I/O | Describe |
| CS | I | Sheet choosing input |
| SO（IO1） | I/O | Data outputs (data input/output port 1) |
| WP（IO2） | I/O | Write-protect (data input/output port 2) |
| VSS | ? | Ground |
| SI（IO0） | I/O | Data inputs (data input/output port 0) |
| SCLK | I | The clock input |
| HOLD(IO3) | I/O | Input is hung up |
| VCC | ? | Power supply |
The FLASH control module can be read FLASH in many ways, comprises that single channel is read, binary channels is read, four-way is read, reads FLASH ID, reads FLASH Identification, reads FLASH status register high eight-bit and reads low eight the seven kinds of modes of FLASH status register.
With reference to figure 4, during single-channel mode, when the CS sheet was elected high level as, FLASH did not work, and when the CS negative edge arrives, started working.The SI of first rising edge place of SCLK began to send data when CS was low level, at first sent Command, and namely control word is controlled different read modes, and 03H represents single channel and reads.Send end from the negative edge Command in 7 cycles of the 0th cycle to the, the negative edge in the 7th cycle begins, and SI sends 24 address, negative edge to the 31st SCLK cycle finishes, meanwhile, SO begins to export 8 data, and this moment, SI upward was invalid data.
With reference to figure 5, during the binary channels mode, be sent completely unanimously with single-channel mode from the arrive Command control word of starting working of CS negative edge, control word is BBH.The negative edge in the 7th cycle begins, and SI and SO divide 38 addresses that send simultaneously 24.Negative edge since the 7th SCLK cycle, four SCLK cycles afterwards are the time that sends the 23-16 position of address bit, SI and SO send respectively 6,4,2,0 and 7,5,3,1 of address bit, and 15-8 bit address position and 7-0 bit address position send continuously with the same manner.The address is sent completely M value of rear transmission, i.e. the continuous controlling value of reading mode, and when M=AXH, next time read operation is defaulted as the binary channels mode, no longer needs to send the Command control word, as shown in Figure 6.After the M value was sent completely, SI and SO read the appropriate address data in the binary channels mode.
With reference to figure 7,8, during the four-way mode, be sent completely unanimously with single-channel mode and binary channels from the arrive Command control word of starting working of CS negative edge, control word is EBH.When address transmission, the transmission of M value and data were exported, the four-way mode as input/output port, was responsible for respectively the input and output of 8 bit data with SI, SO, WP and four pins of HOLD.The M value is identical with two passage modes.Before the output data, have the Dummy time in 4 SCLK cycles.
With reference to figure 9,10, reading the ID mode is respectively 90H and 9FH with the control word of reading the Identification mode, read ManufacturerID and DeviceID that the ID mode can read FLASH, if will at first read ManufacturerID when 24 bit address are 000000H, if will at first read DeviceID when 24 bit address are 000001H.Read the Identification mode and can read ManufacturerID, MemoryTypeID and CapacityID, similar with single channel, use two pins of SI and SO.
With reference to Figure 11, the read states register mode can be divided into reads S7-0 position and S15-8 position dual mode, and control word is respectively 05H and 35H, and its working method is identical with single channel.
The FLASH control module mainly be responsible for the APB bus interface module mutual, FLASH obtains data and sends data to the SRAM control module outside sheet.
In one embodiment, the SRAM data line is 32, is operating as 8 read modes and read FLASH, therefore in order to improve transfer efficiency, 32 bit registers are set in the FLASH control module preserve the FLASH data, treat that 32 bit registers are filled just can be given to the SRAM control module.For reducing the SRAM stand-by period, increase work efficiency, in turn receive data of two 32 bit register Reg_A and Reg_B is set here, be the Data_Recieve_Reg_A shown in Figure 12 and Data_Recieve_Reg_B.When one of them transferred data to the SRAM control module, another was responsible for continuing to receive the FLASH data.The FLASH control module realizes various read modes by state machine, and this state machine has 13 kinds of states, and its title and implication are as shown in table 3, and constitutional diagram as shown in figure 12.
Table 3
| Sequence | Title | Implication | |
| 1 | IDLE | |
|
| 2 | Send_Command | |
|
| 3 | Send_Address_S | Single channel sends the |
|
| 4 | Send_Address_D | Binary channels sends the |
|
| 5 | Send_Address_Q | Four-way sends the |
|
| 6 | Send_M | Binary channels or four-way send the |
|
| 7 | Dummy_Clock | Free time when four-way is read before the |
|
| 8 | Receive_Data_A_S | Single channel is read Reg_A register receive |
|
| 9 | Receive_Data_B_S | Single channel is read Reg_B register receive |
|
| 10 | Receive_Data_A_D | Binary channels is read Reg_A register receive |
|
| 11 | Receive_Data_B_D | Binary channels is read Reg_B register receive data |
| 12 | Receive_Data_A_Q | Four-way is read Reg_A register receive |
| 13 | Receive_Data_B_Q | Four-way is read Reg_B register receive data |
The SRAM control module
The SRAM control module is responsible for controlling SRAM and is received the data that the FLASH control module transmits.In one embodiment, Flash_Write_Enable, Flash_DATA, Flash_Operation_End in this SRAM control module input signal are the output of FLASH control module, Flash_Write_Enable is enable signal from data to SRAM that write, and high level is effective; Flash_DATA is the data of FLASH transmission; Flash_Operation_End is that data transmit settling signal, and high level is effective.Input signal SRAM_Possession and SRAM_Addr are provided by APB, represent respectively SRAM occupancy mode and SRAM initial address.
SRAM takies and is divided into two kinds of occupancy modes: continue to take with intermittence taking, represent with SRAM_Possession=1 and SRAM_Possession=0 respectively.Other modules can not take SRAM when continuing to take, and other modules can take SRAM when intermittently taking.Write_Possession in the output signal is used for indicating that SRAM is that (Write_Possession=1 represents to continue to take which kind of occupancy mode, Write_Possession=0 represents intermittently to take), other modules that need to take SRAM such as CPU or bus can judge whether to take SRAM according to this signal, can improve like this utilization factor and the whole work efficiency of SRAM.
The output of SRAM control module also has Write_End, and the expression data transmit and finish, and high level is effective.Output CEN, OEN, ADDR[11:0], WEN[3:0] and DATA[31:0], these all are the SRAM control signals.CEN and OEN are respectively sheet enable signal and output enable signal, all are that high level is effective; ADDR[11:0] be 12 bit address signals; DATA[31:0] be 32 bit data signals, form by 48, each 8 can be by writing enable signal WEN control, WEN[3:0] each control respectively among 48 of data 1.
The state transformational relation of the state machine of SRAM control module and each state implication are as shown in table 4, and its constitutional diagram as shown in figure 13.
Table 4
| Sequence number | Status Name | | Write_Possession | SRAM_CEN | |
| 1 | |
0 | 0 | 1 | |
| 2 | |
0 | 1 | 0 | |
| 3 | |
0 | 1 | 1 | |
| 4 | |
0 | 0 | 1 | |
| 5 | |
0 | 1 | 1 | |
| 6 | |
0 | 1 | 1 | |
| 7 | |
0 | 1 | 1 | |
| 8 | |
0 | 1 | 1 | |
| 9 | |
0 | 1 | 1 | |
| 10 | |
0 | 1 | 0 | |
| 11 | |
1 | 1 | 1 | |
| 12 | |
0 | 1 | 1 | |
| 13 | |
0 | 1 | 1 | |
| 14 | |
0 | 1 | 1 | |
| 15 | |
0 | 1 | 1 | |
| 16 | |
0 | 1 | 0 | |
| 17 | |
1 | 1 | 1 |
Each state takies a clock period in the control procedure, and each data write operation needs two clock period, therefore finish a data transfer with two states, transmission state occurs in pairs, Plus "0" represents first clock period in Status Name, adding " 1 " second clock period of expression, is a pair of such as Send_0 and Send_1, represents a write operation.The circulation at the Init_0_single place in a kind of special circumstances such as the constitutional diagram is arranged, and this is the situation that individual data transmits, and needs to consider separately.
The solution that the present invention proposes the slow problem of transmission speed, set up simultaneously the straight channel to SRAM by FLASH, data directly can be transferred to SRAM from FLASH.Meanwhile, realized multiple FLASH data transfer mode, comprise that single channel is read, binary channels is read, four-way is read, read FLASH ID, read FLASHIdentification, read FLASH status register high eight-bit and read low eight the seven kinds of modes of FLASH status register, what strengthened this design utilizes scope, convenience and portability.In addition, the occupancy mode at intermittence of SRAM is improved the utilization factor of SRAM, made things convenient for other modules to take SRAM, can improve the work efficiency of chip.Thisly realize that with hardware mode FLASH is more than 20 to 30 times of software mode to the data rate of SRAM, the lasting occupancy mode occupancy of SRAM is 100%, intermittently the different occupancies according to the FLASH read mode do not wait from about 3% to 13% during occupancy mode, clearly, greatly reduce holding time, provide condition for improving chip operation efficient.
It should be noted that at last, above embodiment is only in order to describe technical scheme of the present invention rather than the present technique method is limited, the present invention can extend to other modification, variation, application and embodiment on using, and therefore thinks that all such modifications, variation, application, embodiment are in spirit of the present invention and teachings.
Claims (12)
1. the dedicated data transmission module from the Flash chip to sram chip comprises APB bus interface module, FLASH control module and SRAM control module; The APB bus interface module is used for latching the next address of bus, data, sheet choosing and enable signal with the control sequential; The FLASH control module be used for the APB bus interface module mutual, FLASH obtains data and sends data to the SRAM control module outside sheet; The SRAM control module is used for the data that receive are write SRAM.
2. the dedicated data transmission module from the Flash chip to sram chip according to claim 1 is characterized in that, described APB bus interface module comprises: read enable register, be used for latching the Read_Enable signal of APB bus; Read the type register, be used for latching the Read_Type signal of APB bus; The FLASH address register is for the first address of latching the Flash data; The SRAM address register is for the first address of latching the SRAM receive data; The address size register is used for latching the transmission data length; Flash ID register is used for latching Flash ID; Flash Identification register is used for latching Flash Identification.
3. the dedicated data transmission module from the Flash chip to sram chip according to claim 1 is characterized in that the reading manner of described FLASH control module comprises: single channel is read, binary channels is read, four-way read in one or arbitrarily multinomial combination.
4. the dedicated data transmission module from the Flash chip to sram chip according to claim 3, it is characterized in that the mode that reads FLASH of described FLASH control module also comprises: read FLASH ID, read FLASH Identification, read FLASH status register high eight-bit and read low eight of FLASH status register.
5. the dedicated data transmission module from the Flash chip to sram chip according to claim 4, it is characterized in that, the SRAM data line is 32, read be operating as 8 of FLASH at every turn, 32 bit registers are set in the described FLASH control module preserve the FLASH data, treat that 32 bit registers are filled just data are given to described SRAM control module.
6. the dedicated data transmission module from the Flash chip to sram chip according to claim 5 is characterized in that, described FLASH control module arranges in turn receive data of two 32 bit register Reg_A and Reg_B; When one of them transferred data to the SRAM control module, another was responsible for continuing to receive the data of FLASH.
7. the dedicated data transmission module from the Flash chip to sram chip according to claim 6, it is characterized in that, described FLASH control module realizes various read modes by state machine, and the state of described state machine comprises: idle condition, send control word, single channel sends the address, binary channels sends the address, four-way sends the address, binary channels or four-way send the controlling value of continuous reading mode, free time when four-way is read before the transmission data, single channel is read Reg_A register receive data, single channel is read Reg_B register receive data, binary channels is read Reg_A register receive data, binary channels is read Reg_B register receive data, four-way reads Reg_A register receive data and four-way is read Reg_B register receive data.
8. the dedicated data transmission module from the Flash chip to sram chip according to claim 7, it is characterized in that, the input signal of described SRAM control module comprises: Flash_Write_Enable, Flash_DATA, the Flash_Operation_End of the output of FLASH control module, and Flash_Write_Enable is enable signal from data to SRAM that write; Flash_DATA is the data of FLASH transmission; Flash_Operation_End is that data transmit settling signal; The input signal of described SRAM control module also comprises the SRAM_Addr that is provided by the APB bus control module, expression SRAM initial address.
9. the dedicated data transmission module from the Flash chip to sram chip according to claim 8 is characterized in that, described APB bus control module comprises that also SRAM takies register, be used for to characterize SRAM and be to continue to take or intermittently take; The input signal of described SRAM control module also comprises: the SRAM_Possession that is provided by the APB bus control module, the occupancy mode that is used for SRAM: SOC (system on a chip) other modules except described dedicated data transmission module from Flash to SRAM can not take SRAM when continuing to take, when intermittently taking in the SOC (system on a chip) other modules except described dedicated data transmission module from Flash to SRAM can take SRAM.
10. the dedicated data transmission module from the Flash chip to sram chip according to claim 9 is characterized in that, other modules in the described SOC (system on a chip) except described dedicated data transmission module from Flash to SRAM comprise CPU or bus; The output of described SRAM control module comprises SRAM control signal: Write_End, CEN, OEN, ADDR[11:0], WEN[3:0] and DATA[31:0]; The expression data that are used for Write_End transmit and finish; CEN and OEN are respectively sheet enable signal and output enable signal; ADDR[11:0] be 12 bit address signals; DATA[31:0] be 32 bit data signals, form by 48, each 8 by writing enable signal WEN[3:0] in 1 control.
11. the dedicated data transmission module from the Flash chip to sram chip according to claim 1, it is characterized in that, described APB bus interface module also comprises interruption and processes submodule, and described reception is by the signal of APB bus input, and the setting of interrupt register is inputted by the APB bus.
12. the dedicated data transmission module from the Flash chip to sram chip according to claim 1 is characterized in that described FLASH adopts plug-in FLASH, copies program to SRAM by FLASH and carries out, to improve executing efficiency; And plug-in FLASH divides the segment call program in SRAM.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105573947A (en) * | 2014-10-13 | 2016-05-11 | 北京自动化控制设备研究所 | APB (Advanced Peripheral Bus) based SD/MMC (Secure Digital/ MultiMedia Card) control method |
| CN107291655A (en) * | 2017-06-14 | 2017-10-24 | 北方电子研究院安徽有限公司 | A kind of SoC bootstrapping IP circuits of band APB EBIs |
| CN108091366A (en) * | 2017-12-29 | 2018-05-29 | 中国电子科技集团公司第五十八研究所 | Flash reading circuits and read method |
| CN108132760A (en) * | 2018-01-19 | 2018-06-08 | 湖南国科微电子股份有限公司 | A kind of method and system for promoting SSD reading performances |
| CN109596167A (en) * | 2018-12-03 | 2019-04-09 | 四川虹美智能科技有限公司 | A kind of equipment production test method, system and test terminal |
| CN110187828A (en) * | 2019-04-12 | 2019-08-30 | 深圳市金泰克半导体有限公司 | The rubbish recovering method and nand flash memory of nand flash memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101000597A (en) * | 2007-01-17 | 2007-07-18 | 中山大学 | IP kernel of embedded Java processor based on AMBA |
| CN201378431Y (en) * | 2009-04-01 | 2010-01-06 | 北京泰科源科技有限责任公司 | Control circuit device based on memory of NAND gate structure |
| US8244994B1 (en) * | 2009-01-12 | 2012-08-14 | Ixys Ch Gmbh | Cooperating memory controllers that share data bus terminals for accessing wide external devices |
-
2012
- 2012-10-30 CN CN201210426423.0A patent/CN102968396B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101000597A (en) * | 2007-01-17 | 2007-07-18 | 中山大学 | IP kernel of embedded Java processor based on AMBA |
| US8244994B1 (en) * | 2009-01-12 | 2012-08-14 | Ixys Ch Gmbh | Cooperating memory controllers that share data bus terminals for accessing wide external devices |
| CN201378431Y (en) * | 2009-04-01 | 2010-01-06 | 北京泰科源科技有限责任公司 | Control circuit device based on memory of NAND gate structure |
Non-Patent Citations (4)
| Title |
|---|
| 北京三恒星科技: "8 NAND FLASH 控制器", 《HTTP://WWW.DOCIN.COM/P-201173005.HTML》, 11 May 2011 (2011-05-11) * |
| 曹阳 等: "AMBA 3．0 AXI总线接口协议的研究与应用", 《中国通信集成电路技术与应用研讨会文集》, 1 December 2006 (2006-12-01) * |
| 王洋 等: "基于AMBA APB总线NandFlash控制器的设计研究", 《电子设计工程》, vol. 19, no. 20, 21 April 2012 (2012-04-21) * |
| 蒋彭龙 等: "AMBA总线技术在片上系统(SOC)集成设计中的应用", 《电子设计工程》, vol. 24, no. 3, 21 July 2006 (2006-07-21) * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105573947A (en) * | 2014-10-13 | 2016-05-11 | 北京自动化控制设备研究所 | APB (Advanced Peripheral Bus) based SD/MMC (Secure Digital/ MultiMedia Card) control method |
| CN105573947B (en) * | 2014-10-13 | 2018-10-26 | 北京自动化控制设备研究所 | A kind of SD/MMC card control methods based on APB buses |
| CN107291655A (en) * | 2017-06-14 | 2017-10-24 | 北方电子研究院安徽有限公司 | A kind of SoC bootstrapping IP circuits of band APB EBIs |
| CN107291655B (en) * | 2017-06-14 | 2020-10-09 | 北方电子研究院安徽有限公司 | SoC bootstrap IP circuit with APB bus interface |
| CN108091366A (en) * | 2017-12-29 | 2018-05-29 | 中国电子科技集团公司第五十八研究所 | Flash reading circuits and read method |
| CN108091366B (en) * | 2017-12-29 | 2021-01-29 | 中国电子科技集团公司第五十八研究所 | Flash reading circuit and reading method |
| CN108132760A (en) * | 2018-01-19 | 2018-06-08 | 湖南国科微电子股份有限公司 | A kind of method and system for promoting SSD reading performances |
| CN108132760B (en) * | 2018-01-19 | 2021-03-12 | 湖南国科微电子股份有限公司 | Method and system for improving SSD (solid State disk) reading performance |
| CN109596167A (en) * | 2018-12-03 | 2019-04-09 | 四川虹美智能科技有限公司 | A kind of equipment production test method, system and test terminal |
| CN110187828A (en) * | 2019-04-12 | 2019-08-30 | 深圳市金泰克半导体有限公司 | The rubbish recovering method and nand flash memory of nand flash memory |
| CN110187828B (en) * | 2019-04-12 | 2023-03-28 | 深圳市金泰克半导体有限公司 | Garbage recovery method of NAND flash memory and NAND flash memory |
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